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88ced031 AB |
1 | #ifndef _ASM_POWERPC_PGTABLE_64K_H |
2 | #define _ASM_POWERPC_PGTABLE_64K_H | |
88ced031 | 3 | |
3c726f8d BH |
4 | #include <asm-generic/pgtable-nopud.h> |
5 | ||
6 | ||
7 | #define PTE_INDEX_SIZE 12 | |
8 | #define PMD_INDEX_SIZE 12 | |
9 | #define PUD_INDEX_SIZE 0 | |
10 | #define PGD_INDEX_SIZE 4 | |
11 | ||
ee7a76da | 12 | #ifndef __ASSEMBLY__ |
3c726f8d BH |
13 | #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) |
14 | #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) | |
15 | #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) | |
16 | ||
17 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
18 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
19 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
20 | ||
fa28237c PM |
21 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
22 | /* | |
23 | * For the sub-page protection option, we extend the PGD with one of | |
24 | * these. Basically we have a 3-level tree, with the top level being | |
25 | * the protptrs array. To optimize speed and memory consumption when | |
26 | * only addresses < 4GB are being protected, pointers to the first | |
27 | * four pages of sub-page protection words are stored in the low_prot | |
28 | * array. | |
29 | * Each page of sub-page protection words protects 1GB (4 bytes | |
30 | * protects 64k). For the 3-level tree, each page of pointers then | |
31 | * protects 8TB. | |
32 | */ | |
33 | struct subpage_prot_table { | |
34 | unsigned long maxaddr; /* only addresses < this are protected */ | |
35 | unsigned int **protptrs[2]; | |
36 | unsigned int *low_prot[4]; | |
37 | }; | |
38 | ||
39 | #undef PGD_TABLE_SIZE | |
40 | #define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \ | |
41 | sizeof(struct subpage_prot_table)) | |
42 | ||
43 | #define SBP_L1_BITS (PAGE_SHIFT - 2) | |
44 | #define SBP_L2_BITS (PAGE_SHIFT - 3) | |
45 | #define SBP_L1_COUNT (1 << SBP_L1_BITS) | |
46 | #define SBP_L2_COUNT (1 << SBP_L2_BITS) | |
47 | #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) | |
48 | #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) | |
49 | ||
50 | extern void subpage_prot_free(pgd_t *pgd); | |
51 | ||
52 | static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd) | |
53 | { | |
54 | return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD); | |
55 | } | |
56 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
57 | #endif /* __ASSEMBLY__ */ | |
58 | ||
7d24f0b8 DG |
59 | /* With 4k base page size, hugepage PTEs go at the PMD level */ |
60 | #define MIN_HUGEPTE_SHIFT PAGE_SHIFT | |
61 | ||
3c726f8d BH |
62 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
63 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
64 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
65 | #define PMD_MASK (~(PMD_SIZE-1)) | |
66 | ||
67 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ | |
68 | #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
69 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
70 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
71 | ||
72 | /* Additional PTE bits (don't change without checking asm in hash_low.S) */ | |
73 | #define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */ | |
74 | #define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */ | |
75 | #define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */ | |
721151d0 | 76 | #define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */ |
16c2d476 BH |
77 | |
78 | /* Note the full page bits must be in the same location as for normal | |
79 | * 4k pages as the same asssembly will be used to insert 64K pages | |
80 | * wether the kernel has CONFIG_PPC_64K_PAGES or not | |
81 | */ | |
3c726f8d BH |
82 | #define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */ |
83 | #define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */ | |
84 | ||
85 | /* PTE flags to conserve for HPTE identification */ | |
86 | #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\ | |
87 | _PAGE_COMBO) | |
88 | ||
89 | /* Shift to put page number into pte. | |
90 | * | |
c0f7c6cb PM |
91 | * That gives us a max RPN of 34 bits, which means a max of 50 bits |
92 | * of addressable physical space, or 46 bits for the special 4k PFNs. | |
3c726f8d | 93 | */ |
c0f7c6cb | 94 | #define PTE_RPN_SHIFT (30) |
3c726f8d BH |
95 | #define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT)) |
96 | #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1)) | |
97 | ||
98 | /* _PAGE_CHG_MASK masks of bits that are to be preserved accross | |
99 | * pgprot changes | |
100 | */ | |
101 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
102 | _PAGE_ACCESSED) | |
103 | ||
104 | /* Bits to mask out from a PMD to get to the PTE page */ | |
105 | #define PMD_MASKED_BITS 0x1ff | |
106 | /* Bits to mask out from a PGD/PUD to get to the PMD page */ | |
107 | #define PUD_MASKED_BITS 0x1ff | |
108 | ||
3c726f8d BH |
109 | /* Manipulate "rpte" values */ |
110 | #define __real_pte(e,p) ((real_pte_t) { \ | |
111 | (e), pte_val(*((p) + PTRS_PER_PTE)) }) | |
112 | #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ | |
113 | (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) | |
114 | #define __rpte_to_pte(r) ((r).pte) | |
115 | #define __rpte_sub_valid(rpte, index) \ | |
116 | (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index))) | |
117 | ||
118 | ||
119 | /* Trick: we set __end to va + 64k, which happens works for | |
120 | * a 16M page as well as we want only one iteration | |
121 | */ | |
122 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
123 | do { \ | |
124 | unsigned long __end = va + PAGE_SIZE; \ | |
125 | unsigned __split = (psize == MMU_PAGE_4K || \ | |
126 | psize == MMU_PAGE_64K_AP); \ | |
127 | shift = mmu_psize_defs[psize].shift; \ | |
128 | for (index = 0; va < __end; index++, va += (1 << shift)) { \ | |
129 | if (!__split || __rpte_sub_valid(rpte, index)) do { \ | |
130 | ||
131 | #define pte_iterate_hashed_end() } while(0); } } while(0) | |
132 | ||
16c2d476 | 133 | #define pte_pagesize_index(mm, addr, pte) \ |
bf72aeba | 134 | (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K) |
3c726f8d | 135 | |
721151d0 PM |
136 | #define remap_4k_pfn(vma, addr, pfn, prot) \ |
137 | remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \ | |
138 | __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)) | |
139 | ||
88ced031 | 140 | #endif /* _ASM_POWERPC_PGTABLE_64K_H */ |