Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * c 2001 PPC 64 Team, IBM Corp | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
d387899f SR |
9 | #ifndef _ASM_POWERPC_PPC_PCI_H |
10 | #define _ASM_POWERPC_PPC_PCI_H | |
88ced031 | 11 | #ifdef __KERNEL__ |
1da177e4 | 12 | |
bed59275 SR |
13 | #ifdef CONFIG_PCI |
14 | ||
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <asm/pci-bridge.h> | |
17 | ||
18 | extern unsigned long isa_io_base; | |
19 | ||
1da177e4 LT |
20 | extern void pci_setup_phb_io(struct pci_controller *hose, int primary); |
21 | extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary); | |
22 | ||
23 | ||
24 | extern struct list_head hose_list; | |
1da177e4 | 25 | |
36241ce6 | 26 | extern void find_and_init_phbs(void); |
1da177e4 | 27 | |
3d5134ee | 28 | extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */ |
1da177e4 | 29 | |
ae65a391 | 30 | /** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */ |
31 | #define BUID_HI(buid) ((buid) >> 32) | |
32 | #define BUID_LO(buid) ((buid) & 0xffffffff) | |
33 | ||
1da177e4 LT |
34 | /* PCI device_node operations */ |
35 | struct device_node; | |
36 | typedef void *(*traverse_func)(struct device_node *me, void *data); | |
37 | void *traverse_pci_devices(struct device_node *start, traverse_func pre, | |
38 | void *data); | |
39 | ||
4c9d2800 BH |
40 | extern void pci_devs_phb_init(void); |
41 | extern void pci_devs_phb_init_dynamic(struct pci_controller *phb); | |
42 | extern void scan_phb(struct pci_controller *hose); | |
1da177e4 | 43 | |
dad32bbf | 44 | /* From rtas_pci.h */ |
4c9d2800 BH |
45 | extern void init_pci_config_tokens (void); |
46 | extern unsigned long get_phb_buid (struct device_node *); | |
47 | extern int rtas_setup_phb(struct pci_controller *phb); | |
1da177e4 LT |
48 | |
49 | extern unsigned long pci_probe_only; | |
1da177e4 | 50 | |
6dee3fb9 LV |
51 | /* ---- EEH internal-use-only related routines ---- */ |
52 | #ifdef CONFIG_EEH | |
5d5a0936 LV |
53 | |
54 | void pci_addr_cache_insert_device(struct pci_dev *dev); | |
55 | void pci_addr_cache_remove_device(struct pci_dev *dev); | |
56 | void pci_addr_cache_build(void); | |
57 | struct pci_dev *pci_get_device_by_addr(unsigned long addr); | |
58 | ||
77bd7415 LV |
59 | /** |
60 | * eeh_slot_error_detail -- record and EEH error condition to the log | |
17213c3b LV |
61 | * @pdn: pci device node |
62 | * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE | |
77bd7415 | 63 | * |
59c51591 | 64 | * Obtains the EEH error details from the RTAS subsystem, |
77bd7415 LV |
65 | * and then logs these details with the RTAS error log system. |
66 | */ | |
17213c3b LV |
67 | #define EEH_LOG_TEMP_FAILURE 1 |
68 | #define EEH_LOG_PERM_FAILURE 2 | |
77bd7415 LV |
69 | void eeh_slot_error_detail (struct pci_dn *pdn, int severity); |
70 | ||
47b5c838 | 71 | /** |
9c547768 | 72 | * rtas_pci_enable - enable IO transfers for this slot |
47b5c838 LV |
73 | * @pdn: pci device node |
74 | * @function: either EEH_THAW_MMIO or EEH_THAW_DMA | |
75 | * | |
76 | * Enable I/O transfers to this slot | |
77 | */ | |
78 | #define EEH_THAW_MMIO 2 | |
79 | #define EEH_THAW_DMA 3 | |
80 | int rtas_pci_enable(struct pci_dn *pdn, int function); | |
81 | ||
6dee3fb9 LV |
82 | /** |
83 | * rtas_set_slot_reset -- unfreeze a frozen slot | |
17213c3b | 84 | * @pdn: pci device node |
6dee3fb9 LV |
85 | * |
86 | * Clear the EEH-frozen condition on a slot. This routine | |
87 | * does this by asserting the PCI #RST line for 1/8th of | |
88 | * a second; this routine will sleep while the adapter is | |
89 | * being reset. | |
b6495c0c LV |
90 | * |
91 | * Returns a non-zero value if the reset failed. | |
6dee3fb9 | 92 | */ |
b6495c0c | 93 | int rtas_set_slot_reset (struct pci_dn *); |
9c547768 | 94 | int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs); |
6dee3fb9 | 95 | |
8b553f32 LV |
96 | /** |
97 | * eeh_restore_bars - Restore device configuration info. | |
17213c3b | 98 | * @pdn: pci device node |
8b553f32 LV |
99 | * |
100 | * A reset of a PCI device will clear out its config space. | |
101 | * This routines will restore the config space for this | |
102 | * device, and is children, to values previously obtained | |
103 | * from the firmware. | |
104 | */ | |
105 | void eeh_restore_bars(struct pci_dn *); | |
106 | ||
107 | /** | |
108 | * rtas_configure_bridge -- firmware initialization of pci bridge | |
17213c3b | 109 | * @pdn: pci device node |
8b553f32 LV |
110 | * |
111 | * Ask the firmware to configure all PCI bridges devices | |
112 | * located behind the indicated node. Required after a | |
113 | * pci device reset. Does essentially the same hing as | |
114 | * eeh_restore_bars, but for brdges, and lets firmware | |
115 | * do the work. | |
116 | */ | |
117 | void rtas_configure_bridge(struct pci_dn *); | |
118 | ||
119 | int rtas_write_config(struct pci_dn *, int where, int size, u32 val); | |
7684b40c | 120 | int rtas_read_config(struct pci_dn *, int where, int size, u32 *val); |
8b553f32 | 121 | |
d9564ad1 | 122 | /** |
17213c3b LV |
123 | * eeh_mark_slot -- set mode flags for pertition endpoint |
124 | * @pdn: pci device node | |
125 | * | |
d9564ad1 LV |
126 | * mark and clear slots: find "partition endpoint" PE and set or |
127 | * clear the flags for each subnode of the PE. | |
128 | */ | |
129 | void eeh_mark_slot (struct device_node *dn, int mode_flag); | |
130 | void eeh_clear_slot (struct device_node *dn, int mode_flag); | |
131 | ||
17213c3b LV |
132 | /** |
133 | * find_device_pe -- Find the associated "Partiationable Endpoint" PE | |
134 | * @pdn: pci device node | |
135 | */ | |
9fb40eb8 LV |
136 | struct device_node * find_device_pe(struct device_node *dn); |
137 | ||
e1d04c97 LV |
138 | void eeh_sysfs_add_device(struct pci_dev *pdev); |
139 | void eeh_sysfs_remove_device(struct pci_dev *pdev); | |
140 | ||
17213c3b | 141 | #endif /* CONFIG_EEH */ |
6dee3fb9 | 142 | |
bed59275 SR |
143 | #else /* CONFIG_PCI */ |
144 | static inline void find_and_init_phbs(void) { } | |
145 | static inline void init_pci_config_tokens(void) { } | |
146 | #endif /* !CONFIG_PCI */ | |
147 | ||
88ced031 | 148 | #endif /* __KERNEL__ */ |
d387899f | 149 | #endif /* _ASM_POWERPC_PPC_PCI_H */ |