[deliverable/linux.git] / include / asm-powerpc / ppc_asm.h

/*
 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
 */
#ifndef _ASM_POWERPC_PPC_ASM_H
#define _ASM_POWERPC_PPC_ASM_H

#include <linux/stringify.h>
#include <linux/config.h>

#ifdef __ASSEMBLY__

/*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
#ifdef __powerpc64__
#define SAVE_GPR(n, base)	std	n,GPR0+8*(n)(base)
#define REST_GPR(n, base)	ld	n,GPR0+8*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_8GPRS(14, base); REST_10GPRS(22, base)
#else
#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
				SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \
				REST_10GPRS(22, base)
#endif


#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)

#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*(n)(base)
#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)
#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*(n)(base)
#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)
#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)
#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)
#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)
#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)

#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,b,base
#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,b,base
#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)
#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)

#define SAVE_EVR(n,s,base)	evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
#define SAVE_2EVRS(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
#define SAVE_4EVRS(n,s,base)	SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
#define SAVE_8EVRS(n,s,base)	SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
#define SAVE_16EVRS(n,s,base)	SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
#define SAVE_32EVRS(n,s,base)	SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
#define REST_EVR(n,s,base)	lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
#define REST_2EVRS(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)
#define REST_4EVRS(n,s,base)	REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
#define REST_8EVRS(n,s,base)	REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
#define REST_16EVRS(n,s,base)	REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
#define REST_32EVRS(n,s,base)	REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)

/* Macros to adjust thread priority for hardware multithreading */
#define HMT_VERY_LOW	or	31,31,31	# very low priority
#define HMT_LOW		or	1,1,1
#define HMT_MEDIUM_LOW  or	6,6,6		# medium low priority
#define HMT_MEDIUM	or	2,2,2
#define HMT_MEDIUM_HIGH or	5,5,5		# medium high priority
#define HMT_HIGH	or	3,3,3

/* handle instructions that older assemblers may not know */
#define RFCI		.long 0x4c000066	/* rfci instruction */
#define RFDI		.long 0x4c00004e	/* rfdi instruction */
#define RFMCI		.long 0x4c00004c	/* rfmci instruction */

#ifdef CONFIG_PPC64

#define XGLUE(a,b) a##b
#define GLUE(a,b) XGLUE(a,b)

#define _GLOBAL(name) \
	.section ".text"; \
	.align 2 ; \
	.globl name; \
	.globl GLUE(.,name); \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _KPROBE(name) \
	.section ".kprobes.text","a"; \
	.align 2 ; \
	.globl name; \
	.globl GLUE(.,name); \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _STATIC(name) \
	.section ".text"; \
	.align 2 ; \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#else /* 32-bit */

#define _GLOBAL(n)	\
	.text;		\
	.stabs __stringify(n:F-1),N_FUN,0,0,n;\
	.globl n;	\
n:

#define _KPROBE(n)	\
	.section ".kprobes.text","a";	\
	.globl	n;	\
n:

#endif

/* 
 * LOADADDR( rn, name )
 *   loads the address of 'name' into 'rn'
 *
 * LOADBASE( rn, name )
 *   loads the address (possibly without the low 16 bits) of 'name' into 'rn'
 *   suitable for base+disp addressing
 */
#ifdef __powerpc64__
#define LOADADDR(rn,name) \
	lis	rn,name##@highest;	\
	ori	rn,rn,name##@higher;	\
	rldicr	rn,rn,32,31;		\
	oris	rn,rn,name##@h;		\
	ori	rn,rn,name##@l

#define LOADBASE(rn,name)		\
	ld	rn,name@got(r2)

#define OFF(name)	0

#define SET_REG_TO_CONST(reg, value)	         	\
	lis     reg,(((value)>>48)&0xFFFF);             \
	ori     reg,reg,(((value)>>32)&0xFFFF);         \
	rldicr  reg,reg,32,31;                          \
	oris    reg,reg,(((value)>>16)&0xFFFF);         \
	ori     reg,reg,((value)&0xFFFF);

#define SET_REG_TO_LABEL(reg, label)	         	\
	lis     reg,(label)@highest;                    \
	ori     reg,reg,(label)@higher;                 \
	rldicr  reg,reg,32,31;                          \
	oris    reg,reg,(label)@h;                      \
	ori     reg,reg,(label)@l;

/* operations for longs and pointers */
#define LDL	ld
#define STL	std
#define CMPI	cmpdi

#else /* 32-bit */
#define LOADADDR(rn,name) \
	lis	rn,name@ha;	\
	addi	rn,rn,name@l

#define LOADBASE(rn,name)	\
	lis	rn,name@ha

#define OFF(name)	name@l

/* operations for longs and pointers */
#define LDL	lwz
#define STL	stw
#define CMPI	cmpwi

#endif

/* various errata or part fixups */
#ifdef CONFIG_PPC601_SYNC_FIX
#define SYNC				\
BEGIN_FTR_SECTION			\
	sync;				\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define SYNC_601			\
BEGIN_FTR_SECTION			\
	sync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601			\
BEGIN_FTR_SECTION			\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#else
#define	SYNC
#define SYNC_601
#define ISYNC_601
#endif


#ifndef CONFIG_SMP
#define TLBSYNC
#else /* CONFIG_SMP */
/* tlbsync is not implemented on 601 */
#define TLBSYNC				\
BEGIN_FTR_SECTION			\
	tlbsync;			\
	sync;				\
END_FTR_SECTION_IFCLR(CPU_FTR_601)
#endif

	
/*
 * This instruction is not implemented on the PPC 603 or 601; however, on
 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 * All of these instructions exist in the 8xx, they have magical powers,
 * and they must be used.
 */

#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
#define tlbia					\
	li	r4,1024;			\
	mtctr	r4;				\
	lis	r4,KERNELBASE@h;		\
0:	tlbie	r4;				\
	addi	r4,r4,0x1000;			\
	bdnz	0b
#endif


#ifdef CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb)	dcbt	ra, rb;
#define	PPC405_ERR77_SYNC	sync;
#else
#define PPC405_ERR77(ra,rb)
#define PPC405_ERR77_SYNC
#endif


#ifdef CONFIG_IBM440EP_ERR42
#define PPC440EP_ERR42 isync
#else
#define PPC440EP_ERR42
#endif


#if defined(CONFIG_BOOKE)
#define toreal(rd)
#define fromreal(rd)

#define tophys(rd,rs)				\
	addis	rd,rs,0

#define tovirt(rd,rs)				\
	addis	rd,rs,0

#elif defined(CONFIG_PPC64)
#define toreal(rd)		/* we can access c000... in real mode */
#define fromreal(rd)

#define tophys(rd,rs)                           \
	clrldi	rd,rs,2

#define tovirt(rd,rs)                           \
	rotldi	rd,rs,16;			\
	ori	rd,rd,((KERNELBASE>>48)&0xFFFF);\
	rotldi	rd,rd,48
#else
/*
 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 * physical base address of RAM at compile time.
 */
#define toreal(rd)	tophys(rd,rd)
#define fromreal(rd)	tovirt(rd,rd)

#define tophys(rd,rs)				\
0:	addis	rd,rs,-KERNELBASE@h;		\
	.section ".vtop_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous

#define tovirt(rd,rs)				\
0:	addis	rd,rs,KERNELBASE@h;		\
	.section ".ptov_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous
#endif

#ifdef CONFIG_PPC64
#define RFI		rfid
#define MTMSRD(r)	mtmsrd	r

#else
#define FIX_SRR1(ra, rb)
#ifndef CONFIG_40x
#define	RFI		rfi
#else
#define RFI		rfi; b .	/* Prevent prefetch past rfi */
#endif
#define MTMSRD(r)	mtmsr	r
#define CLR_TOP32(r)
#endif

/* The boring bits... */

/* Condition Register Bit Fields */

#define	cr0	0
#define	cr1	1
#define	cr2	2
#define	cr3	3
#define	cr4	4
#define	cr5	5
#define	cr6	6
#define	cr7	7


/* General Purpose Registers (GPRs) */

#define	r0	0
#define	r1	1
#define	r2	2
#define	r3	3
#define	r4	4
#define	r5	5
#define	r6	6
#define	r7	7
#define	r8	8
#define	r9	9
#define	r10	10
#define	r11	11
#define	r12	12
#define	r13	13
#define	r14	14
#define	r15	15
#define	r16	16
#define	r17	17
#define	r18	18
#define	r19	19
#define	r20	20
#define	r21	21
#define	r22	22
#define	r23	23
#define	r24	24
#define	r25	25
#define	r26	26
#define	r27	27
#define	r28	28
#define	r29	29
#define	r30	30
#define	r31	31


/* Floating Point Registers (FPRs) */

#define	fr0	0
#define	fr1	1
#define	fr2	2
#define	fr3	3
#define	fr4	4
#define	fr5	5
#define	fr6	6
#define	fr7	7
#define	fr8	8
#define	fr9	9
#define	fr10	10
#define	fr11	11
#define	fr12	12
#define	fr13	13
#define	fr14	14
#define	fr15	15
#define	fr16	16
#define	fr17	17
#define	fr18	18
#define	fr19	19
#define	fr20	20
#define	fr21	21
#define	fr22	22
#define	fr23	23
#define	fr24	24
#define	fr25	25
#define	fr26	26
#define	fr27	27
#define	fr28	28
#define	fr29	29
#define	fr30	30
#define	fr31	31

/* AltiVec Registers (VPRs) */

#define	vr0	0
#define	vr1	1
#define	vr2	2
#define	vr3	3
#define	vr4	4
#define	vr5	5
#define	vr6	6
#define	vr7	7
#define	vr8	8
#define	vr9	9
#define	vr10	10
#define	vr11	11
#define	vr12	12
#define	vr13	13
#define	vr14	14
#define	vr15	15
#define	vr16	16
#define	vr17	17
#define	vr18	18
#define	vr19	19
#define	vr20	20
#define	vr21	21
#define	vr22	22
#define	vr23	23
#define	vr24	24
#define	vr25	25
#define	vr26	26
#define	vr27	27
#define	vr28	28
#define	vr29	29
#define	vr30	30
#define	vr31	31

/* SPE Registers (EVPRs) */

#define	evr0	0
#define	evr1	1
#define	evr2	2
#define	evr3	3
#define	evr4	4
#define	evr5	5
#define	evr6	6
#define	evr7	7
#define	evr8	8
#define	evr9	9
#define	evr10	10
#define	evr11	11
#define	evr12	12
#define	evr13	13
#define	evr14	14
#define	evr15	15
#define	evr16	16
#define	evr17	17
#define	evr18	18
#define	evr19	19
#define	evr20	20
#define	evr21	21
#define	evr22	22
#define	evr23	23
#define	evr24	24
#define	evr25	25
#define	evr26	26
#define	evr27	27
#define	evr28	28
#define	evr29	29
#define	evr30	30
#define	evr31	31

/* some stab codes */
#define N_FUN	36
#define N_RSYM	64
#define N_SLINE	68
#define N_SO	100

#define ASM_CONST(x) x
#else
  #define __ASM_CONST(x) x##UL
  #define ASM_CONST(x) __ASM_CONST(x)
#endif /*  __ASSEMBLY__ */

#endif /* _ASM_POWERPC_PPC_ASM_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4	3	*/
5f7c6907 KG	4	#ifndef _ASM_POWERPC_PPC_ASM_H
	5	#define _ASM_POWERPC_PPC_ASM_H
	6
40ef8cbc PM	7	#include <linux/stringify.h>
	8	#include <linux/config.h>
	9
5f7c6907	10	#ifdef __ASSEMBLY__
1da177e4 LT	11
	12	/*
	13	* Macros for storing registers into and loading registers from
	14	* exception frames.
	15	*/
5f7c6907 KG	16	#ifdef __powerpc64__
	17	#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
	18	#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
	19	#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
	20	#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
	21	#else
1da177e4	22	#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907 KG	23	#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
	24	#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
	25	SAVE_10GPRS(22, base)
	26	#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
	27	REST_10GPRS(22, base)
	28	#endif
	29
	30
1da177e4 LT	31	#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
	32	#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
	33	#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
	34	#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4 LT	35	#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
	36	#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
	37	#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
	38	#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
	39
1da177e4 LT	40	#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
	41	#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
	42	#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
	43	#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
	44	#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
	45	#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
	46	#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
	47	#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
	48	#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
	49	#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
	50	#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
	51	#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
	52
	53	#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
5f7c6907 KG	54	#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
	55	#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
	56	#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
	57	#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
	58	#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
1da177e4	59	#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
5f7c6907 KG	60	#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
	61	#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
	62	#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
	63	#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
	64	#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 LT	65
1da177e4 LT	66	#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
5f7c6907 KG	67	#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
	68	#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
	69	#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
	70	#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
	71	#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
1da177e4	72	#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
5f7c6907 KG	73	#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
	74	#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
	75	#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
	76	#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
	77	#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
	78
8c71632f ME	79	/* Macros to adjust thread priority for hardware multithreading */
	80	#define HMT_VERY_LOW or 31,31,31 # very low priority
	81	#define HMT_LOW or 1,1,1
	82	#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
	83	#define HMT_MEDIUM or 2,2,2
	84	#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
	85	#define HMT_HIGH or 3,3,3
5f7c6907 KG	86
	87	/* handle instructions that older assemblers may not know */
	88	#define RFCI .long 0x4c000066 /* rfci instruction */
	89	#define RFDI .long 0x4c00004e /* rfdi instruction */
	90	#define RFMCI .long 0x4c00004c /* rfmci instruction */
	91
40ef8cbc PM	92	#ifdef CONFIG_PPC64
	93
	94	#define XGLUE(a,b) a##b
	95	#define GLUE(a,b) XGLUE(a,b)
	96
	97	#define _GLOBAL(name) \
	98	.section ".text"; \
	99	.align 2 ; \
	100	.globl name; \
	101	.globl GLUE(.,name); \
	102	.section ".opd","aw"; \
	103	name: \
	104	.quad GLUE(.,name); \
	105	.quad .TOC.@tocbase; \
	106	.quad 0; \
	107	.previous; \
	108	.type GLUE(.,name),@function; \
	109	GLUE(.,name):
	110
	111	#define _KPROBE(name) \
	112	.section ".kprobes.text","a"; \
	113	.align 2 ; \
	114	.globl name; \
	115	.globl GLUE(.,name); \
	116	.section ".opd","aw"; \
	117	name: \
	118	.quad GLUE(.,name); \
	119	.quad .TOC.@tocbase; \
	120	.quad 0; \
	121	.previous; \
	122	.type GLUE(.,name),@function; \
	123	GLUE(.,name):
	124
	125	#define _STATIC(name) \
	126	.section ".text"; \
	127	.align 2 ; \
	128	.section ".opd","aw"; \
	129	name: \
	130	.quad GLUE(.,name); \
	131	.quad .TOC.@tocbase; \
	132	.quad 0; \
	133	.previous; \
	134	.type GLUE(.,name),@function; \
	135	GLUE(.,name):
	136
	137	#else /* 32-bit */
	138
	139	#define _GLOBAL(n) \
	140	.text; \
	141	.stabs __stringify(n:F-1),N_FUN,0,0,n;\
	142	.globl n; \
	143	n:
	144
	145	#define _KPROBE(n) \
	146	.section ".kprobes.text","a"; \
	147	.globl n; \
	148	n:
	149
	150	#endif
	151
5f7c6907 KG	152	/*
	153	* LOADADDR( rn, name )
	154	* loads the address of 'name' into 'rn'
	155	*
	156	* LOADBASE( rn, name )
6316222e	157	* loads the address (possibly without the low 16 bits) of 'name' into 'rn'
5f7c6907 KG	158	* suitable for base+disp addressing
	159	*/
	160	#ifdef __powerpc64__
	161	#define LOADADDR(rn,name) \
	162	lis rn,name##@highest; \
	163	ori rn,rn,name##@higher; \
	164	rldicr rn,rn,32,31; \
	165	oris rn,rn,name##@h; \
	166	ori rn,rn,name##@l
	167
b85a046a	168	#define LOADBASE(rn,name) \
6316222e	169	ld rn,name@got(r2)
5f7c6907	170
b85a046a	171	#define OFF(name) 0
5f7c6907 KG	172
	173	#define SET_REG_TO_CONST(reg, value) \
	174	lis reg,(((value)>>48)&0xFFFF); \
	175	ori reg,reg,(((value)>>32)&0xFFFF); \
	176	rldicr reg,reg,32,31; \
	177	oris reg,reg,(((value)>>16)&0xFFFF); \
	178	ori reg,reg,((value)&0xFFFF);
	179
	180	#define SET_REG_TO_LABEL(reg, label) \
	181	lis reg,(label)@highest; \
	182	ori reg,reg,(label)@higher; \
	183	rldicr reg,reg,32,31; \
	184	oris reg,reg,(label)@h; \
	185	ori reg,reg,(label)@l;
b85a046a PM	186
	187	/* operations for longs and pointers */
	188	#define LDL ld
	189	#define STL std
	190	#define CMPI cmpdi
	191
	192	#else /* 32-bit */
70620186	193	#define LOADADDR(rn,name) \
cf764855	194	lis rn,name@ha; \
70620186 SR	195	addi rn,rn,name@l
70620186 SR	196
b85a046a PM	197	#define LOADBASE(rn,name) \
	198	lis rn,name@ha
	199
	200	#define OFF(name) name@l
	201
	202	/* operations for longs and pointers */
	203	#define LDL lwz
	204	#define STL stw
	205	#define CMPI cmpwi
	206
5f7c6907	207	#endif
1da177e4	208
5f7c6907	209	/* various errata or part fixups */
1da177e4 LT	210	#ifdef CONFIG_PPC601_SYNC_FIX
	211	#define SYNC \
	212	BEGIN_FTR_SECTION \
	213	sync; \
	214	isync; \
	215	END_FTR_SECTION_IFSET(CPU_FTR_601)
	216	#define SYNC_601 \
	217	BEGIN_FTR_SECTION \
	218	sync; \
	219	END_FTR_SECTION_IFSET(CPU_FTR_601)
	220	#define ISYNC_601 \
	221	BEGIN_FTR_SECTION \
	222	isync; \
	223	END_FTR_SECTION_IFSET(CPU_FTR_601)
	224	#else
	225	#define SYNC
	226	#define SYNC_601
	227	#define ISYNC_601
	228	#endif
	229
5f7c6907	230
1da177e4 LT	231	#ifndef CONFIG_SMP
	232	#define TLBSYNC
	233	#else /* CONFIG_SMP */
	234	/* tlbsync is not implemented on 601 */
	235	#define TLBSYNC \
	236	BEGIN_FTR_SECTION \
	237	tlbsync; \
	238	sync; \
	239	END_FTR_SECTION_IFCLR(CPU_FTR_601)
	240	#endif
	241
5f7c6907	242
1da177e4 LT	243	/*
	244	* This instruction is not implemented on the PPC 603 or 601; however, on
	245	* the 403GCX and 405GP tlbia IS defined and tlbie is not.
	246	* All of these instructions exist in the 8xx, they have magical powers,
	247	* and they must be used.
	248	*/
	249
	250	#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
	251	#define tlbia \
	252	li r4,1024; \
	253	mtctr r4; \
	254	lis r4,KERNELBASE@h; \
	255	0: tlbie r4; \
	256	addi r4,r4,0x1000; \
	257	bdnz 0b
	258	#endif
	259
5f7c6907 KG	260
	261	#ifdef CONFIG_IBM405_ERR77
	262	#define PPC405_ERR77(ra,rb) dcbt ra, rb;
	263	#define PPC405_ERR77_SYNC sync;
	264	#else
	265	#define PPC405_ERR77(ra,rb)
	266	#define PPC405_ERR77_SYNC
	267	#endif
	268
	269
	270	#ifdef CONFIG_IBM440EP_ERR42
	271	#define PPC440EP_ERR42 isync
	272	#else
	273	#define PPC440EP_ERR42
	274	#endif
	275
	276
	277	#if defined(CONFIG_BOOKE)
6316222e PM	278	#define toreal(rd)
	279	#define fromreal(rd)
	280
1da177e4 LT	281	#define tophys(rd,rs) \
	282	addis rd,rs,0
	283
	284	#define tovirt(rd,rs) \
	285	addis rd,rs,0
	286
5f7c6907	287	#elif defined(CONFIG_PPC64)
6316222e PM	288	#define toreal(rd) /* we can access c000... in real mode */
	289	#define fromreal(rd)
	290
5f7c6907	291	#define tophys(rd,rs) \
6316222e	292	clrldi rd,rs,2
5f7c6907 KG	293
5f7c6907 KG	294	#define tovirt(rd,rs) \
6316222e PM	295	rotldi rd,rs,16; \
	296	ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
	297	rotldi rd,rd,48
5f7c6907	298	#else
1da177e4 LT	299	/*
	300	* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
	301	* physical base address of RAM at compile time.
	302	*/
6316222e PM	303	#define toreal(rd) tophys(rd,rd)
	304	#define fromreal(rd) tovirt(rd,rd)
	305
1da177e4 LT	306	#define tophys(rd,rs) \
	307	0: addis rd,rs,-KERNELBASE@h; \
	308	.section ".vtop_fixup","aw"; \
	309	.align 1; \
	310	.long 0b; \
	311	.previous
	312
	313	#define tovirt(rd,rs) \
	314	0: addis rd,rs,KERNELBASE@h; \
	315	.section ".ptov_fixup","aw"; \
	316	.align 1; \
	317	.long 0b; \
	318	.previous
5f7c6907	319	#endif
1da177e4	320
40ef8cbc PM	321	#ifdef CONFIG_PPC64
	322	#define RFI rfid
	323	#define MTMSRD(r) mtmsrd r
1da177e4 LT	324
	325	#else
	326	#define FIX_SRR1(ra, rb)
	327	#ifndef CONFIG_40x
	328	#define RFI rfi
	329	#else
	330	#define RFI rfi; b . /* Prevent prefetch past rfi */
	331	#endif
	332	#define MTMSRD(r) mtmsr r
	333	#define CLR_TOP32(r)
c9cf73ae MP	334	#endif
c9cf73ae MP	335
1da177e4 LT	336	/* The boring bits... */
	337
	338	/* Condition Register Bit Fields */
	339
	340	#define cr0 0
	341	#define cr1 1
	342	#define cr2 2
	343	#define cr3 3
	344	#define cr4 4
	345	#define cr5 5
	346	#define cr6 6
	347	#define cr7 7
	348
	349
	350	/* General Purpose Registers (GPRs) */
	351
	352	#define r0 0
	353	#define r1 1
	354	#define r2 2
	355	#define r3 3
	356	#define r4 4
	357	#define r5 5
	358	#define r6 6
	359	#define r7 7
	360	#define r8 8
	361	#define r9 9
	362	#define r10 10
	363	#define r11 11
	364	#define r12 12
	365	#define r13 13
	366	#define r14 14
	367	#define r15 15
	368	#define r16 16
	369	#define r17 17
	370	#define r18 18
	371	#define r19 19
	372	#define r20 20
	373	#define r21 21
	374	#define r22 22
	375	#define r23 23
	376	#define r24 24
	377	#define r25 25
	378	#define r26 26
	379	#define r27 27
	380	#define r28 28
	381	#define r29 29
	382	#define r30 30
	383	#define r31 31
	384
	385
	386	/* Floating Point Registers (FPRs) */
	387
	388	#define fr0 0
	389	#define fr1 1
	390	#define fr2 2
	391	#define fr3 3
	392	#define fr4 4
	393	#define fr5 5
	394	#define fr6 6
	395	#define fr7 7
	396	#define fr8 8
	397	#define fr9 9
	398	#define fr10 10
	399	#define fr11 11
400	#define fr12 12
401	#define fr13 13
402	#define fr14 14
403	#define fr15 15
404	#define fr16 16
405	#define fr17 17
406	#define fr18 18
407	#define fr19 19
408	#define fr20 20
409	#define fr21 21
410	#define fr22 22
411	#define fr23 23
412	#define fr24 24
413	#define fr25 25
414	#define fr26 26
415	#define fr27 27
416	#define fr28 28
417	#define fr29 29
418	#define fr30 30
419	#define fr31 31
420
5f7c6907 KG	421	/* AltiVec Registers (VPRs) */
5f7c6907 KG	422
1da177e4 LT	423	#define vr0 0
	424	#define vr1 1
	425	#define vr2 2
	426	#define vr3 3
	427	#define vr4 4
	428	#define vr5 5
	429	#define vr6 6
	430	#define vr7 7
	431	#define vr8 8
	432	#define vr9 9
	433	#define vr10 10
	434	#define vr11 11
	435	#define vr12 12
	436	#define vr13 13
	437	#define vr14 14
	438	#define vr15 15
	439	#define vr16 16
	440	#define vr17 17
	441	#define vr18 18
	442	#define vr19 19
	443	#define vr20 20
	444	#define vr21 21
	445	#define vr22 22
	446	#define vr23 23
	447	#define vr24 24
	448	#define vr25 25
	449	#define vr26 26
	450	#define vr27 27
	451	#define vr28 28
	452	#define vr29 29
	453	#define vr30 30
	454	#define vr31 31
	455
5f7c6907 KG	456	/* SPE Registers (EVPRs) */
5f7c6907 KG	457
1da177e4 LT	458	#define evr0 0
	459	#define evr1 1
	460	#define evr2 2
	461	#define evr3 3
	462	#define evr4 4
	463	#define evr5 5
	464	#define evr6 6
	465	#define evr7 7
	466	#define evr8 8
	467	#define evr9 9
	468	#define evr10 10
	469	#define evr11 11
	470	#define evr12 12
	471	#define evr13 13
	472	#define evr14 14
	473	#define evr15 15
	474	#define evr16 16
	475	#define evr17 17
	476	#define evr18 18
	477	#define evr19 19
	478	#define evr20 20
	479	#define evr21 21
	480	#define evr22 22
	481	#define evr23 23
	482	#define evr24 24
	483	#define evr25 25
	484	#define evr26 26
	485	#define evr27 27
	486	#define evr28 28
	487	#define evr29 29
	488	#define evr30 30
	489	#define evr31 31
	490
	491	/* some stab codes */
	492	#define N_FUN 36
	493	#define N_RSYM 64
	494	#define N_SLINE 68
	495	#define N_SO 100
5f7c6907 KG	496
	497	#define ASM_CONST(x) x
	498	#else
	499	#define __ASM_CONST(x) x##UL
	500	#define ASM_CONST(x) __ASM_CONST(x)
	501	#endif /* __ASSEMBLY__ */
	502
	503	#endif /* _ASM_POWERPC_PPC_ASM_H */