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98658538 LY |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. | |
3 | * | |
4 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
5 | * Li Yang <leoli@freescale.com> | |
6 | * | |
7 | * Description: | |
8 | * QUICC Engine (QE) external definitions and structure. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | #ifndef _ASM_POWERPC_QE_H | |
16 | #define _ASM_POWERPC_QE_H | |
17 | #ifdef __KERNEL__ | |
18 | ||
19 | #include <asm/immap_qe.h> | |
20 | ||
21 | #define QE_NUM_OF_SNUM 28 | |
22 | #define QE_NUM_OF_BRGS 16 | |
23 | #define QE_NUM_OF_PORTS 1024 | |
24 | ||
25 | /* Memory partitions | |
26 | */ | |
27 | #define MEM_PART_SYSTEM 0 | |
28 | #define MEM_PART_SECONDARY 1 | |
29 | #define MEM_PART_MURAM 2 | |
30 | ||
7264ec44 TT |
31 | /* Clocks and BRGs */ |
32 | enum qe_clock { | |
33 | QE_CLK_NONE = 0, | |
34 | QE_BRG1, /* Baud Rate Generator 1 */ | |
35 | QE_BRG2, /* Baud Rate Generator 2 */ | |
36 | QE_BRG3, /* Baud Rate Generator 3 */ | |
37 | QE_BRG4, /* Baud Rate Generator 4 */ | |
38 | QE_BRG5, /* Baud Rate Generator 5 */ | |
39 | QE_BRG6, /* Baud Rate Generator 6 */ | |
40 | QE_BRG7, /* Baud Rate Generator 7 */ | |
41 | QE_BRG8, /* Baud Rate Generator 8 */ | |
42 | QE_BRG9, /* Baud Rate Generator 9 */ | |
43 | QE_BRG10, /* Baud Rate Generator 10 */ | |
44 | QE_BRG11, /* Baud Rate Generator 11 */ | |
45 | QE_BRG12, /* Baud Rate Generator 12 */ | |
46 | QE_BRG13, /* Baud Rate Generator 13 */ | |
47 | QE_BRG14, /* Baud Rate Generator 14 */ | |
48 | QE_BRG15, /* Baud Rate Generator 15 */ | |
49 | QE_BRG16, /* Baud Rate Generator 16 */ | |
50 | QE_CLK1, /* Clock 1 */ | |
51 | QE_CLK2, /* Clock 2 */ | |
52 | QE_CLK3, /* Clock 3 */ | |
53 | QE_CLK4, /* Clock 4 */ | |
54 | QE_CLK5, /* Clock 5 */ | |
55 | QE_CLK6, /* Clock 6 */ | |
56 | QE_CLK7, /* Clock 7 */ | |
57 | QE_CLK8, /* Clock 8 */ | |
58 | QE_CLK9, /* Clock 9 */ | |
59 | QE_CLK10, /* Clock 10 */ | |
60 | QE_CLK11, /* Clock 11 */ | |
61 | QE_CLK12, /* Clock 12 */ | |
62 | QE_CLK13, /* Clock 13 */ | |
63 | QE_CLK14, /* Clock 14 */ | |
64 | QE_CLK15, /* Clock 15 */ | |
65 | QE_CLK16, /* Clock 16 */ | |
66 | QE_CLK17, /* Clock 17 */ | |
67 | QE_CLK18, /* Clock 18 */ | |
68 | QE_CLK19, /* Clock 19 */ | |
69 | QE_CLK20, /* Clock 20 */ | |
70 | QE_CLK21, /* Clock 21 */ | |
71 | QE_CLK22, /* Clock 22 */ | |
72 | QE_CLK23, /* Clock 23 */ | |
73 | QE_CLK24, /* Clock 24 */ | |
74 | QE_CLK_DUMMY | |
75 | }; | |
76 | ||
98658538 LY |
77 | /* Export QE common operations */ |
78 | extern void qe_reset(void); | |
79 | extern int par_io_init(struct device_node *np); | |
80 | extern int par_io_of_config(struct device_node *np); | |
364f8ffc AV |
81 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
82 | int assignment, int has_irq); | |
83 | extern int par_io_data_set(u8 port, u8 pin, u8 val); | |
98658538 LY |
84 | |
85 | /* QE internal API */ | |
86 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); | |
174b0da2 | 87 | enum qe_clock qe_clock_source(const char *source); |
7264ec44 | 88 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); |
98658538 LY |
89 | int qe_get_snum(void); |
90 | void qe_put_snum(u8 snum); | |
4c35630c TT |
91 | unsigned long qe_muram_alloc(int size, int align); |
92 | int qe_muram_free(unsigned long offset); | |
93 | unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); | |
98658538 | 94 | void qe_muram_dump(void); |
4c35630c | 95 | void *qe_muram_addr(unsigned long offset); |
98658538 | 96 | |
bc556ba9 TT |
97 | /* Structure that defines QE firmware binary files. |
98 | * | |
99 | * See Documentation/powerpc/qe-firmware.txt for a description of these | |
100 | * fields. | |
101 | */ | |
102 | struct qe_firmware { | |
103 | struct qe_header { | |
104 | __be32 length; /* Length of the entire structure, in bytes */ | |
105 | u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ | |
106 | u8 version; /* Version of this layout. First ver is '1' */ | |
107 | } header; | |
108 | u8 id[62]; /* Null-terminated identifier string */ | |
109 | u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ | |
110 | u8 count; /* Number of microcode[] structures */ | |
111 | struct { | |
112 | __be16 model; /* The SOC model */ | |
113 | u8 major; /* The SOC revision major */ | |
114 | u8 minor; /* The SOC revision minor */ | |
115 | } __attribute__ ((packed)) soc; | |
116 | u8 padding[4]; /* Reserved, for alignment */ | |
117 | __be64 extended_modes; /* Extended modes */ | |
118 | __be32 vtraps[8]; /* Virtual trap addresses */ | |
119 | u8 reserved[4]; /* Reserved, for future expansion */ | |
120 | struct qe_microcode { | |
121 | u8 id[32]; /* Null-terminated identifier */ | |
122 | __be32 traps[16]; /* Trap addresses, 0 == ignore */ | |
123 | __be32 eccr; /* The value for the ECCR register */ | |
124 | __be32 iram_offset; /* Offset into I-RAM for the code */ | |
125 | __be32 count; /* Number of 32-bit words of the code */ | |
126 | __be32 code_offset; /* Offset of the actual microcode */ | |
127 | u8 major; /* The microcode version major */ | |
128 | u8 minor; /* The microcode version minor */ | |
129 | u8 revision; /* The microcode version revision */ | |
130 | u8 padding; /* Reserved, for alignment */ | |
131 | u8 reserved[4]; /* Reserved, for future expansion */ | |
132 | } __attribute__ ((packed)) microcode[1]; | |
133 | /* All microcode binaries should be located here */ | |
134 | /* CRC32 should be located here, after the microcode binaries */ | |
135 | } __attribute__ ((packed)); | |
136 | ||
137 | struct qe_firmware_info { | |
138 | char id[64]; /* Firmware name */ | |
139 | u32 vtraps[8]; /* Virtual trap addresses */ | |
140 | u64 extended_modes; /* Extended modes */ | |
141 | }; | |
142 | ||
143 | /* Upload a firmware to the QE */ | |
144 | int qe_upload_firmware(const struct qe_firmware *firmware); | |
145 | ||
146 | /* Obtain information on the uploaded firmware */ | |
147 | struct qe_firmware_info *qe_get_firmware_info(void); | |
148 | ||
98658538 LY |
149 | /* Buffer descriptors */ |
150 | struct qe_bd { | |
6b0b594b TT |
151 | __be16 status; |
152 | __be16 length; | |
153 | __be32 buf; | |
98658538 LY |
154 | } __attribute__ ((packed)); |
155 | ||
156 | #define BD_STATUS_MASK 0xffff0000 | |
157 | #define BD_LENGTH_MASK 0x0000ffff | |
158 | ||
6b0b594b TT |
159 | #define BD_SC_EMPTY 0x8000 /* Receive is empty */ |
160 | #define BD_SC_READY 0x8000 /* Transmit is ready */ | |
161 | #define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ | |
162 | #define BD_SC_INTRPT 0x1000 /* Interrupt on change */ | |
163 | #define BD_SC_LAST 0x0800 /* Last buffer in frame */ | |
164 | #define BD_SC_CM 0x0200 /* Continous mode */ | |
165 | #define BD_SC_ID 0x0100 /* Rec'd too many idles */ | |
166 | #define BD_SC_P 0x0100 /* xmt preamble */ | |
167 | #define BD_SC_BR 0x0020 /* Break received */ | |
168 | #define BD_SC_FR 0x0010 /* Framing error */ | |
169 | #define BD_SC_PR 0x0008 /* Parity error */ | |
170 | #define BD_SC_OV 0x0002 /* Overrun */ | |
171 | #define BD_SC_CD 0x0001 /* ?? */ | |
172 | ||
98658538 LY |
173 | /* Alignment */ |
174 | #define QE_INTR_TABLE_ALIGN 16 /* ??? */ | |
175 | #define QE_ALIGNMENT_OF_BD 8 | |
176 | #define QE_ALIGNMENT_OF_PRAM 64 | |
177 | ||
178 | /* RISC allocation */ | |
179 | enum qe_risc_allocation { | |
180 | QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ | |
181 | QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ | |
182 | QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose | |
183 | RISC 1 or RISC 2 */ | |
184 | }; | |
185 | ||
186 | /* QE extended filtering Table Lookup Key Size */ | |
187 | enum qe_fltr_tbl_lookup_key_size { | |
188 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
189 | = 0x3f, /* LookupKey parsed by the Generate LookupKey | |
190 | CMD is truncated to 8 bytes */ | |
191 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
192 | = 0x5f, /* LookupKey parsed by the Generate LookupKey | |
193 | CMD is truncated to 16 bytes */ | |
194 | }; | |
195 | ||
196 | /* QE FLTR extended filtering Largest External Table Lookup Key Size */ | |
197 | enum qe_fltr_largest_external_tbl_lookup_key_size { | |
198 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE | |
199 | = 0x0,/* not used */ | |
200 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
201 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ | |
202 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
203 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ | |
204 | }; | |
205 | ||
206 | /* structure representing QE parameter RAM */ | |
207 | struct qe_timer_tables { | |
208 | u16 tm_base; /* QE timer table base adr */ | |
209 | u16 tm_ptr; /* QE timer table pointer */ | |
210 | u16 r_tmr; /* QE timer mode register */ | |
211 | u16 r_tmv; /* QE timer valid register */ | |
212 | u32 tm_cmd; /* QE timer cmd register */ | |
213 | u32 tm_cnt; /* QE timer internal cnt */ | |
214 | } __attribute__ ((packed)); | |
215 | ||
216 | #define QE_FLTR_TAD_SIZE 8 | |
217 | ||
218 | /* QE extended filtering Termination Action Descriptor (TAD) */ | |
219 | struct qe_fltr_tad { | |
220 | u8 serialized[QE_FLTR_TAD_SIZE]; | |
221 | } __attribute__ ((packed)); | |
222 | ||
223 | /* Communication Direction */ | |
224 | enum comm_dir { | |
225 | COMM_DIR_NONE = 0, | |
226 | COMM_DIR_RX = 1, | |
227 | COMM_DIR_TX = 2, | |
228 | COMM_DIR_RX_AND_TX = 3 | |
229 | }; | |
230 | ||
98658538 LY |
231 | /* QE CMXUCR Registers. |
232 | * There are two UCCs represented in each of the four CMXUCR registers. | |
233 | * These values are for the UCC in the LSBs | |
234 | */ | |
235 | #define QE_CMXUCR_MII_ENET_MNG 0x00007000 | |
236 | #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 | |
237 | #define QE_CMXUCR_GRANT 0x00008000 | |
238 | #define QE_CMXUCR_TSA 0x00004000 | |
239 | #define QE_CMXUCR_BKPT 0x00000100 | |
240 | #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F | |
241 | ||
242 | /* QE CMXGCR Registers. | |
243 | */ | |
244 | #define QE_CMXGCR_MII_ENET_MNG 0x00007000 | |
245 | #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 | |
246 | #define QE_CMXGCR_USBCS 0x0000000f | |
247 | ||
248 | /* QE CECR Commands. | |
249 | */ | |
250 | #define QE_CR_FLG 0x00010000 | |
251 | #define QE_RESET 0x80000000 | |
252 | #define QE_INIT_TX_RX 0x00000000 | |
253 | #define QE_INIT_RX 0x00000001 | |
254 | #define QE_INIT_TX 0x00000002 | |
255 | #define QE_ENTER_HUNT_MODE 0x00000003 | |
256 | #define QE_STOP_TX 0x00000004 | |
257 | #define QE_GRACEFUL_STOP_TX 0x00000005 | |
258 | #define QE_RESTART_TX 0x00000006 | |
259 | #define QE_CLOSE_RX_BD 0x00000007 | |
260 | #define QE_SWITCH_COMMAND 0x00000007 | |
261 | #define QE_SET_GROUP_ADDRESS 0x00000008 | |
262 | #define QE_START_IDMA 0x00000009 | |
263 | #define QE_MCC_STOP_RX 0x00000009 | |
264 | #define QE_ATM_TRANSMIT 0x0000000a | |
265 | #define QE_HPAC_CLEAR_ALL 0x0000000b | |
266 | #define QE_GRACEFUL_STOP_RX 0x0000001a | |
267 | #define QE_RESTART_RX 0x0000001b | |
268 | #define QE_HPAC_SET_PRIORITY 0x0000010b | |
269 | #define QE_HPAC_STOP_TX 0x0000020b | |
270 | #define QE_HPAC_STOP_RX 0x0000030b | |
271 | #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b | |
272 | #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b | |
273 | #define QE_HPAC_START_TX 0x0000060b | |
274 | #define QE_HPAC_START_RX 0x0000070b | |
275 | #define QE_USB_STOP_TX 0x0000000a | |
276 | #define QE_USB_RESTART_TX 0x0000000b | |
277 | #define QE_QMC_STOP_TX 0x0000000c | |
278 | #define QE_QMC_STOP_RX 0x0000000d | |
279 | #define QE_SS7_SU_FIL_RESET 0x0000000e | |
280 | /* jonathbr added from here down for 83xx */ | |
281 | #define QE_RESET_BCS 0x0000000a | |
282 | #define QE_MCC_INIT_TX_RX_16 0x00000003 | |
283 | #define QE_MCC_STOP_TX 0x00000004 | |
284 | #define QE_MCC_INIT_TX_1 0x00000005 | |
285 | #define QE_MCC_INIT_RX_1 0x00000006 | |
286 | #define QE_MCC_RESET 0x00000007 | |
287 | #define QE_SET_TIMER 0x00000008 | |
288 | #define QE_RANDOM_NUMBER 0x0000000c | |
289 | #define QE_ATM_MULTI_THREAD_INIT 0x00000011 | |
290 | #define QE_ASSIGN_PAGE 0x00000012 | |
291 | #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 | |
292 | #define QE_START_FLOW_CONTROL 0x00000014 | |
293 | #define QE_STOP_FLOW_CONTROL 0x00000015 | |
294 | #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 | |
295 | ||
296 | #define QE_ASSIGN_RISC 0x00000010 | |
297 | #define QE_CR_MCN_NORMAL_SHIFT 6 | |
298 | #define QE_CR_MCN_USB_SHIFT 4 | |
299 | #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 | |
300 | #define QE_CR_SNUM_SHIFT 17 | |
301 | ||
302 | /* QE CECR Sub Block - sub block of QE command. | |
303 | */ | |
304 | #define QE_CR_SUBBLOCK_INVALID 0x00000000 | |
305 | #define QE_CR_SUBBLOCK_USB 0x03200000 | |
306 | #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 | |
307 | #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 | |
308 | #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 | |
309 | #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 | |
310 | #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 | |
311 | #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 | |
312 | #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 | |
313 | #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 | |
314 | #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 | |
315 | #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 | |
316 | #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 | |
317 | #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 | |
318 | #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 | |
319 | #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 | |
320 | #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 | |
321 | #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 | |
322 | #define QE_CR_SUBBLOCK_MCC1 0x03800000 | |
323 | #define QE_CR_SUBBLOCK_MCC2 0x03a00000 | |
324 | #define QE_CR_SUBBLOCK_MCC3 0x03000000 | |
325 | #define QE_CR_SUBBLOCK_IDMA1 0x02800000 | |
326 | #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 | |
327 | #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 | |
328 | #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 | |
329 | #define QE_CR_SUBBLOCK_HPAC 0x01e00000 | |
330 | #define QE_CR_SUBBLOCK_SPI1 0x01400000 | |
331 | #define QE_CR_SUBBLOCK_SPI2 0x01600000 | |
332 | #define QE_CR_SUBBLOCK_RAND 0x01c00000 | |
333 | #define QE_CR_SUBBLOCK_TIMER 0x01e00000 | |
334 | #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 | |
335 | ||
336 | /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ | |
337 | #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ | |
338 | #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 | |
6b0b594b TT |
339 | #define QE_CR_PROTOCOL_QMC 0x02 |
340 | #define QE_CR_PROTOCOL_UART 0x04 | |
98658538 LY |
341 | #define QE_CR_PROTOCOL_ATM_POS 0x0A |
342 | #define QE_CR_PROTOCOL_ETHERNET 0x0C | |
343 | #define QE_CR_PROTOCOL_L2_SWITCH 0x0D | |
344 | ||
98658538 LY |
345 | /* BRG configuration register */ |
346 | #define QE_BRGC_ENABLE 0x00010000 | |
347 | #define QE_BRGC_DIVISOR_SHIFT 1 | |
348 | #define QE_BRGC_DIVISOR_MAX 0xFFF | |
349 | #define QE_BRGC_DIV16 1 | |
350 | ||
351 | /* QE Timers registers */ | |
352 | #define QE_GTCFR1_PCAS 0x80 | |
353 | #define QE_GTCFR1_STP2 0x20 | |
354 | #define QE_GTCFR1_RST2 0x10 | |
355 | #define QE_GTCFR1_GM2 0x08 | |
356 | #define QE_GTCFR1_GM1 0x04 | |
357 | #define QE_GTCFR1_STP1 0x02 | |
358 | #define QE_GTCFR1_RST1 0x01 | |
359 | ||
360 | /* SDMA registers */ | |
361 | #define QE_SDSR_BER1 0x02000000 | |
362 | #define QE_SDSR_BER2 0x01000000 | |
363 | ||
364 | #define QE_SDMR_GLB_1_MSK 0x80000000 | |
365 | #define QE_SDMR_ADR_SEL 0x20000000 | |
366 | #define QE_SDMR_BER1_MSK 0x02000000 | |
367 | #define QE_SDMR_BER2_MSK 0x01000000 | |
368 | #define QE_SDMR_EB1_MSK 0x00800000 | |
369 | #define QE_SDMR_ER1_MSK 0x00080000 | |
370 | #define QE_SDMR_ER2_MSK 0x00040000 | |
371 | #define QE_SDMR_CEN_MASK 0x0000E000 | |
372 | #define QE_SDMR_SBER_1 0x00000200 | |
373 | #define QE_SDMR_SBER_2 0x00000200 | |
374 | #define QE_SDMR_EB1_PR_MASK 0x000000C0 | |
375 | #define QE_SDMR_ER1_PR 0x00000008 | |
376 | ||
377 | #define QE_SDMR_CEN_SHIFT 13 | |
378 | #define QE_SDMR_EB1_PR_SHIFT 6 | |
379 | ||
380 | #define QE_SDTM_MSNUM_SHIFT 24 | |
381 | ||
382 | #define QE_SDEBCR_BA_MASK 0x01FFFFFF | |
383 | ||
bc556ba9 TT |
384 | /* Communication Processor */ |
385 | #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ | |
386 | #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ | |
387 | #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ | |
388 | ||
389 | /* I-RAM */ | |
390 | #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ | |
391 | #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ | |
392 | ||
98658538 LY |
393 | /* UPC */ |
394 | #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ | |
395 | #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ | |
396 | #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ | |
397 | #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ | |
398 | #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ | |
399 | ||
6b0b594b | 400 | /* UCC GUEMR register */ |
98658538 | 401 | #define UCC_GUEMR_MODE_MASK_RX 0x02 |
98658538 | 402 | #define UCC_GUEMR_MODE_FAST_RX 0x02 |
98658538 | 403 | #define UCC_GUEMR_MODE_SLOW_RX 0x00 |
6b0b594b TT |
404 | #define UCC_GUEMR_MODE_MASK_TX 0x01 |
405 | #define UCC_GUEMR_MODE_FAST_TX 0x01 | |
98658538 | 406 | #define UCC_GUEMR_MODE_SLOW_TX 0x00 |
6b0b594b | 407 | #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) |
98658538 LY |
408 | #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but |
409 | must be set 1 */ | |
410 | ||
411 | /* structure representing UCC SLOW parameter RAM */ | |
412 | struct ucc_slow_pram { | |
6b0b594b TT |
413 | __be16 rbase; /* RX BD base address */ |
414 | __be16 tbase; /* TX BD base address */ | |
415 | u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ | |
416 | u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ | |
417 | __be16 mrblr; /* Rx buffer length */ | |
418 | __be32 rstate; /* Rx internal state */ | |
419 | __be32 rptr; /* Rx internal data pointer */ | |
420 | __be16 rbptr; /* rb BD Pointer */ | |
421 | __be16 rcount; /* Rx internal byte count */ | |
422 | __be32 rtemp; /* Rx temp */ | |
423 | __be32 tstate; /* Tx internal state */ | |
424 | __be32 tptr; /* Tx internal data pointer */ | |
425 | __be16 tbptr; /* Tx BD pointer */ | |
426 | __be16 tcount; /* Tx byte count */ | |
427 | __be32 ttemp; /* Tx temp */ | |
428 | __be32 rcrc; /* temp receive CRC */ | |
429 | __be32 tcrc; /* temp transmit CRC */ | |
98658538 LY |
430 | } __attribute__ ((packed)); |
431 | ||
432 | /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ | |
6b0b594b TT |
433 | #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 |
434 | #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 | |
98658538 LY |
435 | #define UCC_SLOW_GUMR_H_REVD 0x00002000 |
436 | #define UCC_SLOW_GUMR_H_TRX 0x00001000 | |
437 | #define UCC_SLOW_GUMR_H_TTX 0x00000800 | |
438 | #define UCC_SLOW_GUMR_H_CDP 0x00000400 | |
439 | #define UCC_SLOW_GUMR_H_CTSP 0x00000200 | |
440 | #define UCC_SLOW_GUMR_H_CDS 0x00000100 | |
441 | #define UCC_SLOW_GUMR_H_CTSS 0x00000080 | |
442 | #define UCC_SLOW_GUMR_H_TFL 0x00000040 | |
443 | #define UCC_SLOW_GUMR_H_RFW 0x00000020 | |
444 | #define UCC_SLOW_GUMR_H_TXSY 0x00000010 | |
445 | #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 | |
446 | #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 | |
447 | #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c | |
448 | #define UCC_SLOW_GUMR_H_RTSM 0x00000002 | |
449 | #define UCC_SLOW_GUMR_H_RSYN 0x00000001 | |
450 | ||
451 | #define UCC_SLOW_GUMR_L_TCI 0x10000000 | |
452 | #define UCC_SLOW_GUMR_L_RINV 0x02000000 | |
453 | #define UCC_SLOW_GUMR_L_TINV 0x01000000 | |
6b0b594b TT |
454 | #define UCC_SLOW_GUMR_L_TEND 0x00040000 |
455 | #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 | |
456 | #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 | |
457 | #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 | |
458 | #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 | |
459 | #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 | |
460 | #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 | |
461 | #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 | |
462 | #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 | |
463 | #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 | |
464 | #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 | |
465 | #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 | |
466 | #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 | |
467 | #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 | |
468 | #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 | |
469 | #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 | |
470 | #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 | |
471 | #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 | |
472 | #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 | |
473 | #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 | |
98658538 LY |
474 | #define UCC_SLOW_GUMR_L_ENR 0x00000020 |
475 | #define UCC_SLOW_GUMR_L_ENT 0x00000010 | |
6b0b594b TT |
476 | #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F |
477 | #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 | |
478 | #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 | |
479 | #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 | |
480 | #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 | |
98658538 LY |
481 | |
482 | /* General UCC FAST Mode Register */ | |
483 | #define UCC_FAST_GUMR_TCI 0x20000000 | |
484 | #define UCC_FAST_GUMR_TRX 0x10000000 | |
485 | #define UCC_FAST_GUMR_TTX 0x08000000 | |
486 | #define UCC_FAST_GUMR_CDP 0x04000000 | |
487 | #define UCC_FAST_GUMR_CTSP 0x02000000 | |
488 | #define UCC_FAST_GUMR_CDS 0x01000000 | |
489 | #define UCC_FAST_GUMR_CTSS 0x00800000 | |
490 | #define UCC_FAST_GUMR_TXSY 0x00020000 | |
491 | #define UCC_FAST_GUMR_RSYN 0x00010000 | |
492 | #define UCC_FAST_GUMR_RTSM 0x00002000 | |
493 | #define UCC_FAST_GUMR_REVD 0x00000400 | |
494 | #define UCC_FAST_GUMR_ENR 0x00000020 | |
495 | #define UCC_FAST_GUMR_ENT 0x00000010 | |
496 | ||
6b0b594b TT |
497 | /* UART Slow UCC Event Register (UCCE) */ |
498 | #define UCC_UART_UCCE_AB 0x0200 | |
499 | #define UCC_UART_UCCE_IDLE 0x0100 | |
500 | #define UCC_UART_UCCE_GRA 0x0080 | |
501 | #define UCC_UART_UCCE_BRKE 0x0040 | |
502 | #define UCC_UART_UCCE_BRKS 0x0020 | |
503 | #define UCC_UART_UCCE_CCR 0x0008 | |
504 | #define UCC_UART_UCCE_BSY 0x0004 | |
505 | #define UCC_UART_UCCE_TX 0x0002 | |
506 | #define UCC_UART_UCCE_RX 0x0001 | |
507 | ||
508 | /* HDLC Slow UCC Event Register (UCCE) */ | |
509 | #define UCC_HDLC_UCCE_GLR 0x1000 | |
510 | #define UCC_HDLC_UCCE_GLT 0x0800 | |
511 | #define UCC_HDLC_UCCE_IDLE 0x0100 | |
512 | #define UCC_HDLC_UCCE_BRKE 0x0040 | |
513 | #define UCC_HDLC_UCCE_BRKS 0x0020 | |
514 | #define UCC_HDLC_UCCE_TXE 0x0010 | |
515 | #define UCC_HDLC_UCCE_RXF 0x0008 | |
516 | #define UCC_HDLC_UCCE_BSY 0x0004 | |
517 | #define UCC_HDLC_UCCE_TXB 0x0002 | |
518 | #define UCC_HDLC_UCCE_RXB 0x0001 | |
519 | ||
520 | /* BISYNC Slow UCC Event Register (UCCE) */ | |
521 | #define UCC_BISYNC_UCCE_GRA 0x0080 | |
522 | #define UCC_BISYNC_UCCE_TXE 0x0010 | |
523 | #define UCC_BISYNC_UCCE_RCH 0x0008 | |
524 | #define UCC_BISYNC_UCCE_BSY 0x0004 | |
525 | #define UCC_BISYNC_UCCE_TXB 0x0002 | |
526 | #define UCC_BISYNC_UCCE_RXB 0x0001 | |
527 | ||
528 | /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ | |
529 | #define UCC_GETH_UCCE_MPD 0x80000000 | |
530 | #define UCC_GETH_UCCE_SCAR 0x40000000 | |
531 | #define UCC_GETH_UCCE_GRA 0x20000000 | |
532 | #define UCC_GETH_UCCE_CBPR 0x10000000 | |
533 | #define UCC_GETH_UCCE_BSY 0x08000000 | |
534 | #define UCC_GETH_UCCE_RXC 0x04000000 | |
535 | #define UCC_GETH_UCCE_TXC 0x02000000 | |
536 | #define UCC_GETH_UCCE_TXE 0x01000000 | |
537 | #define UCC_GETH_UCCE_TXB7 0x00800000 | |
538 | #define UCC_GETH_UCCE_TXB6 0x00400000 | |
539 | #define UCC_GETH_UCCE_TXB5 0x00200000 | |
540 | #define UCC_GETH_UCCE_TXB4 0x00100000 | |
541 | #define UCC_GETH_UCCE_TXB3 0x00080000 | |
542 | #define UCC_GETH_UCCE_TXB2 0x00040000 | |
543 | #define UCC_GETH_UCCE_TXB1 0x00020000 | |
544 | #define UCC_GETH_UCCE_TXB0 0x00010000 | |
545 | #define UCC_GETH_UCCE_RXB7 0x00008000 | |
546 | #define UCC_GETH_UCCE_RXB6 0x00004000 | |
547 | #define UCC_GETH_UCCE_RXB5 0x00002000 | |
548 | #define UCC_GETH_UCCE_RXB4 0x00001000 | |
549 | #define UCC_GETH_UCCE_RXB3 0x00000800 | |
550 | #define UCC_GETH_UCCE_RXB2 0x00000400 | |
551 | #define UCC_GETH_UCCE_RXB1 0x00000200 | |
552 | #define UCC_GETH_UCCE_RXB0 0x00000100 | |
553 | #define UCC_GETH_UCCE_RXF7 0x00000080 | |
554 | #define UCC_GETH_UCCE_RXF6 0x00000040 | |
555 | #define UCC_GETH_UCCE_RXF5 0x00000020 | |
556 | #define UCC_GETH_UCCE_RXF4 0x00000010 | |
557 | #define UCC_GETH_UCCE_RXF3 0x00000008 | |
558 | #define UCC_GETH_UCCE_RXF2 0x00000004 | |
559 | #define UCC_GETH_UCCE_RXF1 0x00000002 | |
560 | #define UCC_GETH_UCCE_RXF0 0x00000001 | |
561 | ||
562 | /* UPSMR, when used as a UART */ | |
563 | #define UCC_UART_UPSMR_FLC 0x8000 | |
564 | #define UCC_UART_UPSMR_SL 0x4000 | |
565 | #define UCC_UART_UPSMR_CL_MASK 0x3000 | |
566 | #define UCC_UART_UPSMR_CL_8 0x3000 | |
567 | #define UCC_UART_UPSMR_CL_7 0x2000 | |
568 | #define UCC_UART_UPSMR_CL_6 0x1000 | |
569 | #define UCC_UART_UPSMR_CL_5 0x0000 | |
570 | #define UCC_UART_UPSMR_UM_MASK 0x0c00 | |
571 | #define UCC_UART_UPSMR_UM_NORMAL 0x0000 | |
572 | #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 | |
573 | #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 | |
574 | #define UCC_UART_UPSMR_FRZ 0x0200 | |
575 | #define UCC_UART_UPSMR_RZS 0x0100 | |
576 | #define UCC_UART_UPSMR_SYN 0x0080 | |
577 | #define UCC_UART_UPSMR_DRT 0x0040 | |
578 | #define UCC_UART_UPSMR_PEN 0x0010 | |
579 | #define UCC_UART_UPSMR_RPM_MASK 0x000c | |
580 | #define UCC_UART_UPSMR_RPM_ODD 0x0000 | |
581 | #define UCC_UART_UPSMR_RPM_LOW 0x0004 | |
582 | #define UCC_UART_UPSMR_RPM_EVEN 0x0008 | |
583 | #define UCC_UART_UPSMR_RPM_HIGH 0x000C | |
584 | #define UCC_UART_UPSMR_TPM_MASK 0x0003 | |
585 | #define UCC_UART_UPSMR_TPM_ODD 0x0000 | |
586 | #define UCC_UART_UPSMR_TPM_LOW 0x0001 | |
587 | #define UCC_UART_UPSMR_TPM_EVEN 0x0002 | |
588 | #define UCC_UART_UPSMR_TPM_HIGH 0x0003 | |
98658538 LY |
589 | |
590 | /* UCC Transmit On Demand Register (UTODR) */ | |
591 | #define UCC_SLOW_TOD 0x8000 | |
592 | #define UCC_FAST_TOD 0x8000 | |
593 | ||
6b0b594b TT |
594 | /* UCC Bus Mode Register masks */ |
595 | /* Not to be confused with the Bundle Mode Register */ | |
596 | #define UCC_BMR_GBL 0x20 | |
597 | #define UCC_BMR_BO_BE 0x10 | |
598 | #define UCC_BMR_CETM 0x04 | |
599 | #define UCC_BMR_DTB 0x02 | |
600 | #define UCC_BMR_BDB 0x01 | |
601 | ||
98658538 LY |
602 | /* Function code masks */ |
603 | #define FC_GBL 0x20 | |
604 | #define FC_DTB_LCL 0x02 | |
605 | #define UCC_FAST_FUNCTION_CODE_GBL 0x20 | |
606 | #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 | |
607 | #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 | |
608 | ||
98658538 LY |
609 | #endif /* __KERNEL__ */ |
610 | #endif /* _ASM_POWERPC_QE_H */ |