Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
bbeb3f4c SR |
4 | #ifndef _ASM_POWERPC_SYSTEM_H |
5 | #define _ASM_POWERPC_SYSTEM_H | |
14cf11af | 6 | |
14cf11af PM |
7 | #include <linux/kernel.h> |
8 | ||
9 | #include <asm/hw_irq.h> | |
14cf11af PM |
10 | |
11 | /* | |
12 | * Memory barrier. | |
13 | * The sync instruction guarantees that all memory accesses initiated | |
14 | * by this processor have been performed (with respect to all other | |
15 | * mechanisms that access memory). The eieio instruction is a barrier | |
16 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
17 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
18 | * | |
19 | * mb() prevents loads and stores being reordered across this point. | |
20 | * rmb() prevents loads being reordered across this point. | |
21 | * wmb() prevents stores being reordered across this point. | |
22 | * read_barrier_depends() prevents data-dependent loads being reordered | |
23 | * across this point (nop on PPC). | |
24 | * | |
25 | * We have to use the sync instructions for mb(), since lwsync doesn't | |
26 | * order loads with respect to previous stores. Lwsync is fine for | |
e0da0dae AF |
27 | * rmb(), though. Note that rmb() actually uses a sync on 32-bit |
28 | * architectures. | |
14cf11af PM |
29 | * |
30 | * For wmb(), we use sync since wmb is used in drivers to order | |
31 | * stores to system memory with respect to writes to the device. | |
32 | * However, smp_wmb() can be a lighter-weight eieio barrier on | |
33 | * SMP since it is only used to order updates to system memory. | |
34 | */ | |
35 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
e0da0dae | 36 | #define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory") |
14cf11af PM |
37 | #define wmb() __asm__ __volatile__ ("sync" : : : "memory") |
38 | #define read_barrier_depends() do { } while(0) | |
39 | ||
40 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
14cf11af | 41 | |
88ced031 | 42 | #ifdef __KERNEL__ |
4f9a58d7 | 43 | #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ |
14cf11af PM |
44 | #ifdef CONFIG_SMP |
45 | #define smp_mb() mb() | |
46 | #define smp_rmb() rmb() | |
74a0ba61 | 47 | #define smp_wmb() eieio() |
14cf11af PM |
48 | #define smp_read_barrier_depends() read_barrier_depends() |
49 | #else | |
50 | #define smp_mb() barrier() | |
51 | #define smp_rmb() barrier() | |
52 | #define smp_wmb() barrier() | |
53 | #define smp_read_barrier_depends() do { } while(0) | |
54 | #endif /* CONFIG_SMP */ | |
55 | ||
5db9fa95 NL |
56 | /* |
57 | * This is a barrier which prevents following instructions from being | |
58 | * started until the value of the argument x is known. For example, if | |
59 | * x is a variable loaded from memory, this prevents following | |
60 | * instructions from being executed until the load has been performed. | |
61 | */ | |
62 | #define data_barrier(x) \ | |
63 | asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); | |
64 | ||
14cf11af PM |
65 | struct task_struct; |
66 | struct pt_regs; | |
67 | ||
7dbb922c | 68 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
14cf11af PM |
69 | |
70 | extern int (*__debugger)(struct pt_regs *regs); | |
71 | extern int (*__debugger_ipi)(struct pt_regs *regs); | |
72 | extern int (*__debugger_bpt)(struct pt_regs *regs); | |
73 | extern int (*__debugger_sstep)(struct pt_regs *regs); | |
74 | extern int (*__debugger_iabr_match)(struct pt_regs *regs); | |
75 | extern int (*__debugger_dabr_match)(struct pt_regs *regs); | |
76 | extern int (*__debugger_fault_handler)(struct pt_regs *regs); | |
77 | ||
78 | #define DEBUGGER_BOILERPLATE(__NAME) \ | |
79 | static inline int __NAME(struct pt_regs *regs) \ | |
80 | { \ | |
81 | if (unlikely(__ ## __NAME)) \ | |
82 | return __ ## __NAME(regs); \ | |
83 | return 0; \ | |
84 | } | |
85 | ||
86 | DEBUGGER_BOILERPLATE(debugger) | |
87 | DEBUGGER_BOILERPLATE(debugger_ipi) | |
88 | DEBUGGER_BOILERPLATE(debugger_bpt) | |
89 | DEBUGGER_BOILERPLATE(debugger_sstep) | |
90 | DEBUGGER_BOILERPLATE(debugger_iabr_match) | |
91 | DEBUGGER_BOILERPLATE(debugger_dabr_match) | |
92 | DEBUGGER_BOILERPLATE(debugger_fault_handler) | |
93 | ||
14cf11af PM |
94 | #else |
95 | static inline int debugger(struct pt_regs *regs) { return 0; } | |
96 | static inline int debugger_ipi(struct pt_regs *regs) { return 0; } | |
97 | static inline int debugger_bpt(struct pt_regs *regs) { return 0; } | |
98 | static inline int debugger_sstep(struct pt_regs *regs) { return 0; } | |
99 | static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } | |
100 | static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } | |
101 | static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } | |
102 | #endif | |
103 | ||
104 | extern int set_dabr(unsigned long dabr); | |
105 | extern void print_backtrace(unsigned long *); | |
106 | extern void show_regs(struct pt_regs * regs); | |
107 | extern void flush_instruction_cache(void); | |
108 | extern void hard_reset_now(void); | |
109 | extern void poweroff_now(void); | |
110 | ||
111 | #ifdef CONFIG_6xx | |
112 | extern long _get_L2CR(void); | |
113 | extern long _get_L3CR(void); | |
114 | extern void _set_L2CR(unsigned long); | |
115 | extern void _set_L3CR(unsigned long); | |
116 | #else | |
117 | #define _get_L2CR() 0L | |
118 | #define _get_L3CR() 0L | |
119 | #define _set_L2CR(val) do { } while(0) | |
120 | #define _set_L3CR(val) do { } while(0) | |
121 | #endif | |
122 | ||
123 | extern void via_cuda_init(void); | |
14cf11af PM |
124 | extern void read_rtc_time(void); |
125 | extern void pmac_find_display(void); | |
126 | extern void giveup_fpu(struct task_struct *); | |
cabb5587 | 127 | extern void disable_kernel_fp(void); |
14cf11af PM |
128 | extern void enable_kernel_fp(void); |
129 | extern void flush_fp_to_thread(struct task_struct *); | |
130 | extern void enable_kernel_altivec(void); | |
131 | extern void giveup_altivec(struct task_struct *); | |
132 | extern void load_up_altivec(struct task_struct *); | |
40ef8cbc | 133 | extern int emulate_altivec(struct pt_regs *); |
d169d140 | 134 | extern void enable_kernel_spe(void); |
14cf11af PM |
135 | extern void giveup_spe(struct task_struct *); |
136 | extern void load_up_spe(struct task_struct *); | |
137 | extern int fix_alignment(struct pt_regs *); | |
25c8a78b DG |
138 | extern void cvt_fd(float *from, double *to, struct thread_struct *thread); |
139 | extern void cvt_df(double *from, float *to, struct thread_struct *thread); | |
14cf11af | 140 | |
5388fb10 PM |
141 | #ifndef CONFIG_SMP |
142 | extern void discard_lazy_cpu_state(void); | |
143 | #else | |
144 | static inline void discard_lazy_cpu_state(void) | |
145 | { | |
146 | } | |
147 | #endif | |
148 | ||
14cf11af PM |
149 | #ifdef CONFIG_ALTIVEC |
150 | extern void flush_altivec_to_thread(struct task_struct *); | |
151 | #else | |
152 | static inline void flush_altivec_to_thread(struct task_struct *t) | |
153 | { | |
154 | } | |
155 | #endif | |
156 | ||
157 | #ifdef CONFIG_SPE | |
158 | extern void flush_spe_to_thread(struct task_struct *); | |
159 | #else | |
160 | static inline void flush_spe_to_thread(struct task_struct *t) | |
161 | { | |
162 | } | |
163 | #endif | |
164 | ||
165 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | |
166 | extern void cacheable_memzero(void *p, unsigned int nb); | |
167 | extern void *cacheable_memcpy(void *, const void *, unsigned int); | |
168 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | |
169 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
170 | extern int die(const char *, struct pt_regs *, long); | |
171 | extern void _exception(int, struct pt_regs *, int, unsigned long); | |
1d59483a JL |
172 | extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); |
173 | ||
14cf11af PM |
174 | #ifdef CONFIG_BOOKE_WDT |
175 | extern u32 booke_wdt_enabled; | |
176 | extern u32 booke_wdt_period; | |
177 | #endif /* CONFIG_BOOKE_WDT */ | |
178 | ||
14cf11af PM |
179 | struct device_node; |
180 | extern void note_scsi_host(struct device_node *, void *); | |
181 | ||
182 | extern struct task_struct *__switch_to(struct task_struct *, | |
183 | struct task_struct *); | |
184 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
185 | ||
186 | struct thread_struct; | |
187 | extern struct task_struct *_switch(struct thread_struct *prev, | |
188 | struct thread_struct *next); | |
189 | ||
190 | extern unsigned int rtas_data; | |
40ef8cbc | 191 | extern int mem_init_done; /* set on boot once kmalloc can be called */ |
cf00a8d1 | 192 | extern unsigned long memory_limit; |
49b09853 | 193 | extern unsigned long klimit; |
14cf11af | 194 | |
7b2c3c5b | 195 | extern void *alloc_maybe_bootmem(size_t size, gfp_t mask); |
5669c3cf | 196 | extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); |
7b2c3c5b | 197 | |
17a6392d PM |
198 | extern int powersave_nap; /* set if nap mode can be used in idle loop */ |
199 | ||
14cf11af PM |
200 | /* |
201 | * Atomic exchange | |
202 | * | |
203 | * Changes the memory location '*ptr' to be val and returns | |
204 | * the previous value stored there. | |
205 | */ | |
206 | static __inline__ unsigned long | |
207 | __xchg_u32(volatile void *p, unsigned long val) | |
208 | { | |
209 | unsigned long prev; | |
210 | ||
211 | __asm__ __volatile__( | |
144b9c13 | 212 | LWSYNC_ON_SMP |
14cf11af PM |
213 | "1: lwarx %0,0,%2 \n" |
214 | PPC405_ERR77(0,%2) | |
215 | " stwcx. %3,0,%2 \n\ | |
216 | bne- 1b" | |
217 | ISYNC_ON_SMP | |
e2a3d402 LT |
218 | : "=&r" (prev), "+m" (*(volatile unsigned int *)p) |
219 | : "r" (p), "r" (val) | |
14cf11af PM |
220 | : "cc", "memory"); |
221 | ||
222 | return prev; | |
223 | } | |
224 | ||
f46e477e MD |
225 | /* |
226 | * Atomic exchange | |
227 | * | |
228 | * Changes the memory location '*ptr' to be val and returns | |
229 | * the previous value stored there. | |
230 | */ | |
231 | static __inline__ unsigned long | |
232 | __xchg_u32_local(volatile void *p, unsigned long val) | |
233 | { | |
234 | unsigned long prev; | |
235 | ||
236 | __asm__ __volatile__( | |
237 | "1: lwarx %0,0,%2 \n" | |
238 | PPC405_ERR77(0,%2) | |
239 | " stwcx. %3,0,%2 \n\ | |
240 | bne- 1b" | |
241 | : "=&r" (prev), "+m" (*(volatile unsigned int *)p) | |
242 | : "r" (p), "r" (val) | |
243 | : "cc", "memory"); | |
244 | ||
245 | return prev; | |
246 | } | |
247 | ||
14cf11af PM |
248 | #ifdef CONFIG_PPC64 |
249 | static __inline__ unsigned long | |
250 | __xchg_u64(volatile void *p, unsigned long val) | |
251 | { | |
252 | unsigned long prev; | |
253 | ||
254 | __asm__ __volatile__( | |
144b9c13 | 255 | LWSYNC_ON_SMP |
14cf11af PM |
256 | "1: ldarx %0,0,%2 \n" |
257 | PPC405_ERR77(0,%2) | |
258 | " stdcx. %3,0,%2 \n\ | |
259 | bne- 1b" | |
260 | ISYNC_ON_SMP | |
e2a3d402 LT |
261 | : "=&r" (prev), "+m" (*(volatile unsigned long *)p) |
262 | : "r" (p), "r" (val) | |
14cf11af PM |
263 | : "cc", "memory"); |
264 | ||
265 | return prev; | |
266 | } | |
f46e477e MD |
267 | |
268 | static __inline__ unsigned long | |
269 | __xchg_u64_local(volatile void *p, unsigned long val) | |
270 | { | |
271 | unsigned long prev; | |
272 | ||
273 | __asm__ __volatile__( | |
274 | "1: ldarx %0,0,%2 \n" | |
275 | PPC405_ERR77(0,%2) | |
276 | " stdcx. %3,0,%2 \n\ | |
277 | bne- 1b" | |
278 | : "=&r" (prev), "+m" (*(volatile unsigned long *)p) | |
279 | : "r" (p), "r" (val) | |
280 | : "cc", "memory"); | |
281 | ||
282 | return prev; | |
283 | } | |
14cf11af PM |
284 | #endif |
285 | ||
286 | /* | |
287 | * This function doesn't exist, so you'll get a linker error | |
288 | * if something tries to do an invalid xchg(). | |
289 | */ | |
290 | extern void __xchg_called_with_bad_pointer(void); | |
291 | ||
292 | static __inline__ unsigned long | |
293 | __xchg(volatile void *ptr, unsigned long x, unsigned int size) | |
294 | { | |
295 | switch (size) { | |
296 | case 4: | |
297 | return __xchg_u32(ptr, x); | |
298 | #ifdef CONFIG_PPC64 | |
299 | case 8: | |
300 | return __xchg_u64(ptr, x); | |
301 | #endif | |
302 | } | |
303 | __xchg_called_with_bad_pointer(); | |
304 | return x; | |
305 | } | |
306 | ||
f46e477e MD |
307 | static __inline__ unsigned long |
308 | __xchg_local(volatile void *ptr, unsigned long x, unsigned int size) | |
309 | { | |
310 | switch (size) { | |
311 | case 4: | |
312 | return __xchg_u32_local(ptr, x); | |
313 | #ifdef CONFIG_PPC64 | |
314 | case 8: | |
315 | return __xchg_u64_local(ptr, x); | |
316 | #endif | |
317 | } | |
318 | __xchg_called_with_bad_pointer(); | |
319 | return x; | |
320 | } | |
14cf11af PM |
321 | #define xchg(ptr,x) \ |
322 | ({ \ | |
323 | __typeof__(*(ptr)) _x_ = (x); \ | |
324 | (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ | |
325 | }) | |
326 | ||
f46e477e MD |
327 | #define xchg_local(ptr,x) \ |
328 | ({ \ | |
329 | __typeof__(*(ptr)) _x_ = (x); \ | |
330 | (__typeof__(*(ptr))) __xchg_local((ptr), \ | |
331 | (unsigned long)_x_, sizeof(*(ptr))); \ | |
332 | }) | |
333 | ||
14cf11af PM |
334 | /* |
335 | * Compare and exchange - if *p == old, set it to new, | |
336 | * and return the old value of *p. | |
337 | */ | |
338 | #define __HAVE_ARCH_CMPXCHG 1 | |
339 | ||
340 | static __inline__ unsigned long | |
341 | __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new) | |
342 | { | |
343 | unsigned int prev; | |
344 | ||
345 | __asm__ __volatile__ ( | |
144b9c13 | 346 | LWSYNC_ON_SMP |
14cf11af PM |
347 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ |
348 | cmpw 0,%0,%3\n\ | |
349 | bne- 2f\n" | |
350 | PPC405_ERR77(0,%2) | |
351 | " stwcx. %4,0,%2\n\ | |
352 | bne- 1b" | |
353 | ISYNC_ON_SMP | |
354 | "\n\ | |
355 | 2:" | |
e2a3d402 LT |
356 | : "=&r" (prev), "+m" (*p) |
357 | : "r" (p), "r" (old), "r" (new) | |
14cf11af PM |
358 | : "cc", "memory"); |
359 | ||
360 | return prev; | |
361 | } | |
362 | ||
f46e477e MD |
363 | static __inline__ unsigned long |
364 | __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old, | |
365 | unsigned long new) | |
366 | { | |
367 | unsigned int prev; | |
368 | ||
369 | __asm__ __volatile__ ( | |
370 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ | |
371 | cmpw 0,%0,%3\n\ | |
372 | bne- 2f\n" | |
373 | PPC405_ERR77(0,%2) | |
374 | " stwcx. %4,0,%2\n\ | |
375 | bne- 1b" | |
376 | "\n\ | |
377 | 2:" | |
378 | : "=&r" (prev), "+m" (*p) | |
379 | : "r" (p), "r" (old), "r" (new) | |
380 | : "cc", "memory"); | |
381 | ||
382 | return prev; | |
383 | } | |
384 | ||
14cf11af PM |
385 | #ifdef CONFIG_PPC64 |
386 | static __inline__ unsigned long | |
3c726f8d | 387 | __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new) |
14cf11af PM |
388 | { |
389 | unsigned long prev; | |
390 | ||
391 | __asm__ __volatile__ ( | |
144b9c13 | 392 | LWSYNC_ON_SMP |
14cf11af PM |
393 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ |
394 | cmpd 0,%0,%3\n\ | |
395 | bne- 2f\n\ | |
396 | stdcx. %4,0,%2\n\ | |
397 | bne- 1b" | |
398 | ISYNC_ON_SMP | |
399 | "\n\ | |
400 | 2:" | |
e2a3d402 LT |
401 | : "=&r" (prev), "+m" (*p) |
402 | : "r" (p), "r" (old), "r" (new) | |
14cf11af PM |
403 | : "cc", "memory"); |
404 | ||
405 | return prev; | |
406 | } | |
f46e477e MD |
407 | |
408 | static __inline__ unsigned long | |
409 | __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old, | |
410 | unsigned long new) | |
411 | { | |
412 | unsigned long prev; | |
413 | ||
414 | __asm__ __volatile__ ( | |
415 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ | |
416 | cmpd 0,%0,%3\n\ | |
417 | bne- 2f\n\ | |
418 | stdcx. %4,0,%2\n\ | |
419 | bne- 1b" | |
420 | "\n\ | |
421 | 2:" | |
422 | : "=&r" (prev), "+m" (*p) | |
423 | : "r" (p), "r" (old), "r" (new) | |
424 | : "cc", "memory"); | |
425 | ||
426 | return prev; | |
427 | } | |
14cf11af PM |
428 | #endif |
429 | ||
430 | /* This function doesn't exist, so you'll get a linker error | |
431 | if something tries to do an invalid cmpxchg(). */ | |
432 | extern void __cmpxchg_called_with_bad_pointer(void); | |
433 | ||
434 | static __inline__ unsigned long | |
435 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, | |
436 | unsigned int size) | |
437 | { | |
438 | switch (size) { | |
439 | case 4: | |
440 | return __cmpxchg_u32(ptr, old, new); | |
441 | #ifdef CONFIG_PPC64 | |
442 | case 8: | |
443 | return __cmpxchg_u64(ptr, old, new); | |
444 | #endif | |
445 | } | |
446 | __cmpxchg_called_with_bad_pointer(); | |
447 | return old; | |
448 | } | |
449 | ||
f46e477e MD |
450 | static __inline__ unsigned long |
451 | __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new, | |
452 | unsigned int size) | |
453 | { | |
454 | switch (size) { | |
455 | case 4: | |
456 | return __cmpxchg_u32_local(ptr, old, new); | |
457 | #ifdef CONFIG_PPC64 | |
458 | case 8: | |
459 | return __cmpxchg_u64_local(ptr, old, new); | |
460 | #endif | |
461 | } | |
462 | __cmpxchg_called_with_bad_pointer(); | |
463 | return old; | |
464 | } | |
465 | ||
f9c4650b | 466 | #define cmpxchg(ptr, o, n) \ |
14cf11af PM |
467 | ({ \ |
468 | __typeof__(*(ptr)) _o_ = (o); \ | |
469 | __typeof__(*(ptr)) _n_ = (n); \ | |
470 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
471 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
472 | }) | |
473 | ||
f46e477e | 474 | |
f9c4650b | 475 | #define cmpxchg_local(ptr, o, n) \ |
f46e477e MD |
476 | ({ \ |
477 | __typeof__(*(ptr)) _o_ = (o); \ | |
478 | __typeof__(*(ptr)) _n_ = (n); \ | |
479 | (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ | |
480 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
481 | }) | |
482 | ||
14cf11af PM |
483 | #ifdef CONFIG_PPC64 |
484 | /* | |
485 | * We handle most unaligned accesses in hardware. On the other hand | |
486 | * unaligned DMA can be very expensive on some ppc64 IO chips (it does | |
487 | * powers of 2 writes until it reaches sufficient alignment). | |
488 | * | |
489 | * Based on this we disable the IP header alignment in network drivers. | |
025be81e AB |
490 | * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining |
491 | * cacheline alignment of buffers. | |
14cf11af | 492 | */ |
025be81e AB |
493 | #define NET_IP_ALIGN 0 |
494 | #define NET_SKB_PAD L1_CACHE_BYTES | |
f9c4650b MD |
495 | |
496 | #define cmpxchg64(ptr, o, n) \ | |
497 | ({ \ | |
498 | BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ | |
499 | cmpxchg((ptr), (o), (n)); \ | |
500 | }) | |
501 | #define cmpxchg64_local(ptr, o, n) \ | |
502 | ({ \ | |
503 | BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ | |
504 | cmpxchg_local((ptr), (o), (n)); \ | |
505 | }) | |
506 | #else | |
507 | #include <asm-generic/cmpxchg-local.h> | |
508 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | |
14cf11af PM |
509 | #endif |
510 | ||
511 | #define arch_align_stack(x) (x) | |
512 | ||
9b6b563c | 513 | /* Used in very early kernel initialization. */ |
cabb5587 | 514 | extern unsigned long reloc_offset(void); |
9b6b563c PM |
515 | extern unsigned long add_reloc_offset(unsigned long); |
516 | extern void reloc_got2(unsigned long); | |
517 | ||
518 | #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) | |
cabb5587 | 519 | |
c87ef117 ME |
520 | static inline void create_instruction(unsigned long addr, unsigned int instr) |
521 | { | |
522 | unsigned int *p; | |
523 | p = (unsigned int *)addr; | |
524 | *p = instr; | |
525 | asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p)); | |
526 | } | |
527 | ||
528 | /* Flags for create_branch: | |
529 | * "b" == create_branch(addr, target, 0); | |
530 | * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); | |
531 | * "bl" == create_branch(addr, target, BRANCH_SET_LINK); | |
532 | * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK); | |
533 | */ | |
534 | #define BRANCH_SET_LINK 0x1 | |
535 | #define BRANCH_ABSOLUTE 0x2 | |
536 | ||
537 | static inline void create_branch(unsigned long addr, | |
538 | unsigned long target, int flags) | |
539 | { | |
540 | unsigned int instruction; | |
541 | ||
542 | if (! (flags & BRANCH_ABSOLUTE)) | |
543 | target = target - addr; | |
544 | ||
545 | /* Mask out the flags and target, so they don't step on each other. */ | |
546 | instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC); | |
547 | ||
548 | create_instruction(addr, instruction); | |
549 | } | |
550 | ||
551 | static inline void create_function_call(unsigned long addr, void * func) | |
552 | { | |
553 | unsigned long func_addr; | |
554 | ||
555 | #ifdef CONFIG_PPC64 | |
556 | /* | |
557 | * On PPC64 the function pointer actually points to the function's | |
558 | * descriptor. The first entry in the descriptor is the address | |
559 | * of the function text. | |
560 | */ | |
561 | func_addr = *(unsigned long *)func; | |
562 | #else | |
563 | func_addr = (unsigned long)func; | |
564 | #endif | |
565 | create_branch(addr, func_addr, BRANCH_SET_LINK); | |
566 | } | |
567 | ||
c6622f63 PM |
568 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
569 | extern void account_system_vtime(struct task_struct *); | |
570 | #endif | |
571 | ||
94a3807c ME |
572 | extern struct dentry *powerpc_debugfs_root; |
573 | ||
14cf11af | 574 | #endif /* __KERNEL__ */ |
bbeb3f4c | 575 | #endif /* _ASM_POWERPC_SYSTEM_H */ |