[deliverable/linux.git] / include / asm-powerpc / system.h

/*
 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
 */
#ifndef _ASM_POWERPC_SYSTEM_H
#define _ASM_POWERPC_SYSTEM_H

#include <linux/kernel.h>

#include <asm/hw_irq.h>
#include <asm/atomic.h>

/*
 * Memory barrier.
 * The sync instruction guarantees that all memory accesses initiated
 * by this processor have been performed (with respect to all other
 * mechanisms that access memory).  The eieio instruction is a barrier
 * providing an ordering (separately) for (a) cacheable stores and (b)
 * loads and stores to non-cacheable memory (e.g. I/O devices).
 *
 * mb() prevents loads and stores being reordered across this point.
 * rmb() prevents loads being reordered across this point.
 * wmb() prevents stores being reordered across this point.
 * read_barrier_depends() prevents data-dependent loads being reordered
 *	across this point (nop on PPC).
 *
 * We have to use the sync instructions for mb(), since lwsync doesn't
 * order loads with respect to previous stores.  Lwsync is fine for
 * rmb(), though.  Note that lwsync is interpreted as sync by
 * 32-bit and older 64-bit CPUs.
 *
 * For wmb(), we use sync since wmb is used in drivers to order
 * stores to system memory with respect to writes to the device.
 * However, smp_wmb() can be a lighter-weight eieio barrier on
 * SMP since it is only used to order updates to system memory.
 */
#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
#define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
#define read_barrier_depends()  do { } while(0)

#define set_mb(var, value)	do { var = value; mb(); } while (0)

#ifdef __KERNEL__
#ifdef CONFIG_SMP
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	__asm__ __volatile__ ("eieio" : : : "memory")
#define smp_read_barrier_depends()	read_barrier_depends()
#else
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#define smp_read_barrier_depends()	do { } while(0)
#endif /* CONFIG_SMP */

struct task_struct;
struct pt_regs;

#ifdef CONFIG_DEBUGGER

extern int (*__debugger)(struct pt_regs *regs);
extern int (*__debugger_ipi)(struct pt_regs *regs);
extern int (*__debugger_bpt)(struct pt_regs *regs);
extern int (*__debugger_sstep)(struct pt_regs *regs);
extern int (*__debugger_iabr_match)(struct pt_regs *regs);
extern int (*__debugger_dabr_match)(struct pt_regs *regs);
extern int (*__debugger_fault_handler)(struct pt_regs *regs);

#define DEBUGGER_BOILERPLATE(__NAME) \
static inline int __NAME(struct pt_regs *regs) \
{ \
	if (unlikely(__ ## __NAME)) \
		return __ ## __NAME(regs); \
	return 0; \
}

DEBUGGER_BOILERPLATE(debugger)
DEBUGGER_BOILERPLATE(debugger_ipi)
DEBUGGER_BOILERPLATE(debugger_bpt)
DEBUGGER_BOILERPLATE(debugger_sstep)
DEBUGGER_BOILERPLATE(debugger_iabr_match)
DEBUGGER_BOILERPLATE(debugger_dabr_match)
DEBUGGER_BOILERPLATE(debugger_fault_handler)

#ifdef CONFIG_XMON
extern void xmon_init(int enable);
#endif

#else
static inline int debugger(struct pt_regs *regs) { return 0; }
static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif

extern int set_dabr(unsigned long dabr);
extern void print_backtrace(unsigned long *);
extern void show_regs(struct pt_regs * regs);
extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);

#ifdef CONFIG_6xx
extern long _get_L2CR(void);
extern long _get_L3CR(void);
extern void _set_L2CR(unsigned long);
extern void _set_L3CR(unsigned long);
#else
#define _get_L2CR()	0L
#define _get_L3CR()	0L
#define _set_L2CR(val)	do { } while(0)
#define _set_L3CR(val)	do { } while(0)
#endif

extern void via_cuda_init(void);
extern void read_rtc_time(void);
extern void pmac_find_display(void);
extern void giveup_fpu(struct task_struct *);
extern void disable_kernel_fp(void);
extern void enable_kernel_fp(void);
extern void flush_fp_to_thread(struct task_struct *);
extern void enable_kernel_altivec(void);
extern void giveup_altivec(struct task_struct *);
extern void load_up_altivec(struct task_struct *);
extern int emulate_altivec(struct pt_regs *);
extern void giveup_spe(struct task_struct *);
extern void load_up_spe(struct task_struct *);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
extern void cvt_df(double *from, float *to, struct thread_struct *thread);

#ifndef CONFIG_SMP
extern void discard_lazy_cpu_state(void);
#else
static inline void discard_lazy_cpu_state(void)
{
}
#endif

#ifdef CONFIG_ALTIVEC
extern void flush_altivec_to_thread(struct task_struct *);
#else
static inline void flush_altivec_to_thread(struct task_struct *t)
{
}
#endif

#ifdef CONFIG_SPE
extern void flush_spe_to_thread(struct task_struct *);
#else
static inline void flush_spe_to_thread(struct task_struct *t)
{
}
#endif

extern int call_rtas(const char *, int, int, unsigned long *, ...);
extern void cacheable_memzero(void *p, unsigned int nb);
extern void *cacheable_memcpy(void *, const void *, unsigned int);
extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
extern void bad_page_fault(struct pt_regs *, unsigned long, int);
extern int die(const char *, struct pt_regs *, long);
extern void _exception(int, struct pt_regs *, int, unsigned long);
#ifdef CONFIG_BOOKE_WDT
extern u32 booke_wdt_enabled;
extern u32 booke_wdt_period;
#endif /* CONFIG_BOOKE_WDT */

/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
extern unsigned char e2a(unsigned char);
extern unsigned char* strne2a(unsigned char *dest,
		const unsigned char *src, size_t n);

struct device_node;
extern void note_scsi_host(struct device_node *, void *);

extern struct task_struct *__switch_to(struct task_struct *,
	struct task_struct *);
#define switch_to(prev, next, last)	((last) = __switch_to((prev), (next)))

struct thread_struct;
extern struct task_struct *_switch(struct thread_struct *prev,
				   struct thread_struct *next);

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

extern unsigned int rtas_data;
extern int mem_init_done;	/* set on boot once kmalloc can be called */
extern unsigned long memory_limit;
extern unsigned long klimit;

extern int powersave_nap;	/* set if nap mode can be used in idle loop */

/*
 * Atomic exchange
 *
 * Changes the memory location '*ptr' to be val and returns
 * the previous value stored there.
 */
static __inline__ unsigned long
__xchg_u32(volatile void *p, unsigned long val)
{
	unsigned long prev;

	__asm__ __volatile__(
	LWSYNC_ON_SMP
"1:	lwarx	%0,0,%2 \n"
	PPC405_ERR77(0,%2)
"	stwcx.	%3,0,%2 \n\
	bne-	1b"
	ISYNC_ON_SMP
	: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
	: "r" (p), "r" (val)
	: "cc", "memory");

	return prev;
}

#ifdef CONFIG_PPC64
static __inline__ unsigned long
__xchg_u64(volatile void *p, unsigned long val)
{
	unsigned long prev;

	__asm__ __volatile__(
	LWSYNC_ON_SMP
"1:	ldarx	%0,0,%2 \n"
	PPC405_ERR77(0,%2)
"	stdcx.	%3,0,%2 \n\
	bne-	1b"
	ISYNC_ON_SMP
	: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
	: "r" (p), "r" (val)
	: "cc", "memory");

	return prev;
}
#endif

/*
 * This function doesn't exist, so you'll get a linker error
 * if something tries to do an invalid xchg().
 */
extern void __xchg_called_with_bad_pointer(void);

static __inline__ unsigned long
__xchg(volatile void *ptr, unsigned long x, unsigned int size)
{
	switch (size) {
	case 4:
		return __xchg_u32(ptr, x);
#ifdef CONFIG_PPC64
	case 8:
		return __xchg_u64(ptr, x);
#endif
	}
	__xchg_called_with_bad_pointer();
	return x;
}

#define xchg(ptr,x)							     \
  ({									     \
     __typeof__(*(ptr)) _x_ = (x);					     \
     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
  })

#define tas(ptr) (xchg((ptr),1))

/*
 * Compare and exchange - if *p == old, set it to new,
 * and return the old value of *p.
 */
#define __HAVE_ARCH_CMPXCHG	1

static __inline__ unsigned long
__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
{
	unsigned int prev;

	__asm__ __volatile__ (
	LWSYNC_ON_SMP
"1:	lwarx	%0,0,%2		# __cmpxchg_u32\n\
	cmpw	0,%0,%3\n\
	bne-	2f\n"
	PPC405_ERR77(0,%2)
"	stwcx.	%4,0,%2\n\
	bne-	1b"
	ISYNC_ON_SMP
	"\n\
2:"
	: "=&r" (prev), "+m" (*p)
	: "r" (p), "r" (old), "r" (new)
	: "cc", "memory");

	return prev;
}

#ifdef CONFIG_PPC64
static __inline__ unsigned long
__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
{
	unsigned long prev;

	__asm__ __volatile__ (
	LWSYNC_ON_SMP
"1:	ldarx	%0,0,%2		# __cmpxchg_u64\n\
	cmpd	0,%0,%3\n\
	bne-	2f\n\
	stdcx.	%4,0,%2\n\
	bne-	1b"
	ISYNC_ON_SMP
	"\n\
2:"
	: "=&r" (prev), "+m" (*p)
	: "r" (p), "r" (old), "r" (new)
	: "cc", "memory");

	return prev;
}
#endif

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static __inline__ unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
	  unsigned int size)
{
	switch (size) {
	case 4:
		return __cmpxchg_u32(ptr, old, new);
#ifdef CONFIG_PPC64
	case 8:
		return __cmpxchg_u64(ptr, old, new);
#endif
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,o,n)						 \
  ({									 \
     __typeof__(*(ptr)) _o_ = (o);					 \
     __typeof__(*(ptr)) _n_ = (n);					 \
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
				    (unsigned long)_n_, sizeof(*(ptr))); \
  })

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 * cacheline alignment of buffers.
 */
#define NET_IP_ALIGN	0
#define NET_SKB_PAD	L1_CACHE_BYTES
#endif

#define arch_align_stack(x) (x)

/* Used in very early kernel initialization. */
extern unsigned long reloc_offset(void);
extern unsigned long add_reloc_offset(unsigned long);
extern void reloc_got2(unsigned long);

#define PTRRELOC(x)	((typeof(x)) add_reloc_offset((unsigned long)(x)))

static inline void create_instruction(unsigned long addr, unsigned int instr)
{
	unsigned int *p;
	p  = (unsigned int *)addr;
	*p = instr;
	asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
}

/* Flags for create_branch:
 * "b"   == create_branch(addr, target, 0);
 * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
 * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
 */
#define BRANCH_SET_LINK	0x1
#define BRANCH_ABSOLUTE	0x2

static inline void create_branch(unsigned long addr,
		unsigned long target, int flags)
{
	unsigned int instruction;

	if (! (flags & BRANCH_ABSOLUTE))
		target = target - addr;

	/* Mask out the flags and target, so they don't step on each other. */
	instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);

	create_instruction(addr, instruction);
}

static inline void create_function_call(unsigned long addr, void * func)
{
	unsigned long func_addr;

#ifdef CONFIG_PPC64
	/*
	 * On PPC64 the function pointer actually points to the function's
	 * descriptor. The first entry in the descriptor is the address
	 * of the function text.
	 */
	func_addr = *(unsigned long *)func;
#else
	func_addr = (unsigned long)func;
#endif
	create_branch(addr, func_addr, BRANCH_SET_LINK);
}

#ifdef CONFIG_VIRT_CPU_ACCOUNTING
extern void account_system_vtime(struct task_struct *);
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_SYSTEM_H */
Commit	Line	Data
14cf11af PM	1	/*
	2	* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
	3	*/
bbeb3f4c SR	4	#ifndef _ASM_POWERPC_SYSTEM_H
bbeb3f4c SR	5	#define _ASM_POWERPC_SYSTEM_H
14cf11af	6
14cf11af PM	7	#include <linux/kernel.h>
	8
	9	#include <asm/hw_irq.h>
40ef8cbc	10	#include <asm/atomic.h>
14cf11af PM	11
	12	/*
	13	* Memory barrier.
	14	* The sync instruction guarantees that all memory accesses initiated
	15	* by this processor have been performed (with respect to all other
	16	* mechanisms that access memory). The eieio instruction is a barrier
	17	* providing an ordering (separately) for (a) cacheable stores and (b)
	18	* loads and stores to non-cacheable memory (e.g. I/O devices).
	19	*
	20	* mb() prevents loads and stores being reordered across this point.
	21	* rmb() prevents loads being reordered across this point.
	22	* wmb() prevents stores being reordered across this point.
	23	* read_barrier_depends() prevents data-dependent loads being reordered
	24	* across this point (nop on PPC).
	25	*
	26	* We have to use the sync instructions for mb(), since lwsync doesn't
	27	* order loads with respect to previous stores. Lwsync is fine for
	28	* rmb(), though. Note that lwsync is interpreted as sync by
	29	* 32-bit and older 64-bit CPUs.
	30	*
	31	* For wmb(), we use sync since wmb is used in drivers to order
	32	* stores to system memory with respect to writes to the device.
	33	* However, smp_wmb() can be a lighter-weight eieio barrier on
	34	* SMP since it is only used to order updates to system memory.
	35	*/
	36	#define mb() __asm__ __volatile__ ("sync" : : : "memory")
	37	#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
	38	#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
	39	#define read_barrier_depends() do { } while(0)
	40
	41	#define set_mb(var, value) do { var = value; mb(); } while (0)
14cf11af	42
88ced031	43	#ifdef __KERNEL__
14cf11af PM	44	#ifdef CONFIG_SMP
	45	#define smp_mb() mb()
	46	#define smp_rmb() rmb()
	47	#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
	48	#define smp_read_barrier_depends() read_barrier_depends()
	49	#else
	50	#define smp_mb() barrier()
	51	#define smp_rmb() barrier()
	52	#define smp_wmb() barrier()
	53	#define smp_read_barrier_depends() do { } while(0)
	54	#endif /* CONFIG_SMP */
	55
14cf11af PM	56	struct task_struct;
	57	struct pt_regs;
	58
	59	#ifdef CONFIG_DEBUGGER
	60
	61	extern int (__debugger)(struct pt_regs regs);
	62	extern int (__debugger_ipi)(struct pt_regs regs);
	63	extern int (__debugger_bpt)(struct pt_regs regs);
	64	extern int (__debugger_sstep)(struct pt_regs regs);
	65	extern int (__debugger_iabr_match)(struct pt_regs regs);
	66	extern int (__debugger_dabr_match)(struct pt_regs regs);
	67	extern int (__debugger_fault_handler)(struct pt_regs regs);
	68
	69	#define DEBUGGER_BOILERPLATE(__NAME) \
	70	static inline int __NAME(struct pt_regs *regs) \
	71	{ \
	72	if (unlikely(__ ## __NAME)) \
	73	return __ ## __NAME(regs); \
	74	return 0; \
	75	}
	76
	77	DEBUGGER_BOILERPLATE(debugger)
	78	DEBUGGER_BOILERPLATE(debugger_ipi)
	79	DEBUGGER_BOILERPLATE(debugger_bpt)
	80	DEBUGGER_BOILERPLATE(debugger_sstep)
	81	DEBUGGER_BOILERPLATE(debugger_iabr_match)
	82	DEBUGGER_BOILERPLATE(debugger_dabr_match)
	83	DEBUGGER_BOILERPLATE(debugger_fault_handler)
	84
	85	#ifdef CONFIG_XMON
	86	extern void xmon_init(int enable);
	87	#endif
	88
	89	#else
	90	static inline int debugger(struct pt_regs *regs) { return 0; }
	91	static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
	92	static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
	93	static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
	94	static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
	95	static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
	96	static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
	97	#endif
	98
	99	extern int set_dabr(unsigned long dabr);
	100	extern void print_backtrace(unsigned long *);
	101	extern void show_regs(struct pt_regs * regs);
	102	extern void flush_instruction_cache(void);
	103	extern void hard_reset_now(void);
	104	extern void poweroff_now(void);
	105
	106	#ifdef CONFIG_6xx
	107	extern long _get_L2CR(void);
	108	extern long _get_L3CR(void);
	109	extern void _set_L2CR(unsigned long);
	110	extern void _set_L3CR(unsigned long);
	111	#else
	112	#define _get_L2CR() 0L
	113	#define _get_L3CR() 0L
	114	#define _set_L2CR(val) do { } while(0)
	115	#define _set_L3CR(val) do { } while(0)
	116	#endif
	117
	118	extern void via_cuda_init(void);
14cf11af PM	119	extern void read_rtc_time(void);
	120	extern void pmac_find_display(void);
	121	extern void giveup_fpu(struct task_struct *);
cabb5587	122	extern void disable_kernel_fp(void);
14cf11af PM	123	extern void enable_kernel_fp(void);
	124	extern void flush_fp_to_thread(struct task_struct *);
	125	extern void enable_kernel_altivec(void);
	126	extern void giveup_altivec(struct task_struct *);
	127	extern void load_up_altivec(struct task_struct *);
40ef8cbc	128	extern int emulate_altivec(struct pt_regs *);
14cf11af PM	129	extern void giveup_spe(struct task_struct *);
	130	extern void load_up_spe(struct task_struct *);
	131	extern int fix_alignment(struct pt_regs *);
25c8a78b DG	132	extern void cvt_fd(float from, double to, struct thread_struct *thread);
25c8a78b DG	133	extern void cvt_df(double from, float to, struct thread_struct *thread);
14cf11af	134
5388fb10 PM	135	#ifndef CONFIG_SMP
	136	extern void discard_lazy_cpu_state(void);
	137	#else
	138	static inline void discard_lazy_cpu_state(void)
	139	{
	140	}
	141	#endif
	142
14cf11af PM	143	#ifdef CONFIG_ALTIVEC
	144	extern void flush_altivec_to_thread(struct task_struct *);
	145	#else
	146	static inline void flush_altivec_to_thread(struct task_struct *t)
	147	{
	148	}
	149	#endif
	150
	151	#ifdef CONFIG_SPE
	152	extern void flush_spe_to_thread(struct task_struct *);
	153	#else
	154	static inline void flush_spe_to_thread(struct task_struct *t)
	155	{
	156	}
	157	#endif
	158
	159	extern int call_rtas(const char , int, int, unsigned long , ...);
	160	extern void cacheable_memzero(void *p, unsigned int nb);
	161	extern void cacheable_memcpy(void , const void *, unsigned int);
	162	extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
	163	extern void bad_page_fault(struct pt_regs *, unsigned long, int);
	164	extern int die(const char , struct pt_regs , long);
	165	extern void _exception(int, struct pt_regs *, int, unsigned long);
	166	#ifdef CONFIG_BOOKE_WDT
	167	extern u32 booke_wdt_enabled;
	168	extern u32 booke_wdt_period;
	169	#endif /* CONFIG_BOOKE_WDT */
	170
	171	/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
	172	extern unsigned char e2a(unsigned char);
584fc6d1 ME	173	extern unsigned char* strne2a(unsigned char *dest,
584fc6d1 ME	174	const unsigned char *src, size_t n);
14cf11af PM	175
	176	struct device_node;
	177	extern void note_scsi_host(struct device_node , void );
	178
	179	extern struct task_struct __switch_to(struct task_struct ,
	180	struct task_struct *);
	181	#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
	182
	183	struct thread_struct;
	184	extern struct task_struct _switch(struct thread_struct prev,
	185	struct thread_struct *next);
	186
4dc7a0bb IM	187	/*
	188	* On SMP systems, when the scheduler does migration-cost autodetection,
	189	* it needs a way to flush as much of the CPU's caches as possible.
	190	*
	191	* TODO: fill this in!
	192	*/
	193	static inline void sched_cacheflush(void)
	194	{
	195	}
	196
14cf11af	197	extern unsigned int rtas_data;
40ef8cbc	198	extern int mem_init_done; /* set on boot once kmalloc can be called */
cf00a8d1	199	extern unsigned long memory_limit;
49b09853	200	extern unsigned long klimit;
14cf11af	201
17a6392d PM	202	extern int powersave_nap; /* set if nap mode can be used in idle loop */
17a6392d PM	203
14cf11af PM	204	/*
	205	* Atomic exchange
	206	*
	207	* Changes the memory location '*ptr' to be val and returns
	208	* the previous value stored there.
	209	*/
	210	static __inline__ unsigned long
	211	__xchg_u32(volatile void *p, unsigned long val)
	212	{
	213	unsigned long prev;
	214
	215	__asm__ __volatile__(
144b9c13	216	LWSYNC_ON_SMP
14cf11af PM	217	"1: lwarx %0,0,%2 \n"
	218	PPC405_ERR77(0,%2)
	219	" stwcx. %3,0,%2 \n\
	220	bne- 1b"
	221	ISYNC_ON_SMP
e2a3d402 LT	222	: "=&r" (prev), "+m" ((volatile unsigned int )p)
e2a3d402 LT	223	: "r" (p), "r" (val)
14cf11af PM	224	: "cc", "memory");
	225
	226	return prev;
	227	}
	228
	229	#ifdef CONFIG_PPC64
	230	static __inline__ unsigned long
	231	__xchg_u64(volatile void *p, unsigned long val)
	232	{
	233	unsigned long prev;
	234
	235	__asm__ __volatile__(
144b9c13	236	LWSYNC_ON_SMP
14cf11af PM	237	"1: ldarx %0,0,%2 \n"
	238	PPC405_ERR77(0,%2)
	239	" stdcx. %3,0,%2 \n\
	240	bne- 1b"
	241	ISYNC_ON_SMP
e2a3d402 LT	242	: "=&r" (prev), "+m" ((volatile unsigned long )p)
e2a3d402 LT	243	: "r" (p), "r" (val)
14cf11af PM	244	: "cc", "memory");
	245
	246	return prev;
	247	}
	248	#endif
	249
	250	/*
	251	* This function doesn't exist, so you'll get a linker error
	252	* if something tries to do an invalid xchg().
	253	*/
	254	extern void __xchg_called_with_bad_pointer(void);
	255
	256	static __inline__ unsigned long
	257	__xchg(volatile void *ptr, unsigned long x, unsigned int size)
	258	{
	259	switch (size) {
	260	case 4:
	261	return __xchg_u32(ptr, x);
	262	#ifdef CONFIG_PPC64
	263	case 8:
	264	return __xchg_u64(ptr, x);
	265	#endif
	266	}
	267	__xchg_called_with_bad_pointer();
	268	return x;
	269	}
	270
	271	#define xchg(ptr,x) \
	272	({ \
	273	__typeof__(*(ptr)) _x_ = (x); \
	274	(__typeof__((ptr))) __xchg((ptr), (unsigned long)_x_, sizeof((ptr))); \
	275	})
	276
	277	#define tas(ptr) (xchg((ptr),1))
	278
	279	/*
	280	* Compare and exchange - if *p == old, set it to new,
	281	* and return the old value of *p.
	282	*/
	283	#define __HAVE_ARCH_CMPXCHG 1
	284
	285	static __inline__ unsigned long
	286	__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
	287	{
	288	unsigned int prev;
	289
	290	__asm__ __volatile__ (
144b9c13	291	LWSYNC_ON_SMP
14cf11af PM	292	"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
	293	cmpw 0,%0,%3\n\
	294	bne- 2f\n"
	295	PPC405_ERR77(0,%2)
	296	" stwcx. %4,0,%2\n\
	297	bne- 1b"
	298	ISYNC_ON_SMP
	299	"\n\
	300	2:"
e2a3d402 LT	301	: "=&r" (prev), "+m" (*p)
e2a3d402 LT	302	: "r" (p), "r" (old), "r" (new)
14cf11af PM	303	: "cc", "memory");
	304
	305	return prev;
	306	}
	307
	308	#ifdef CONFIG_PPC64
	309	static __inline__ unsigned long
3c726f8d	310	__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
14cf11af PM	311	{
	312	unsigned long prev;
	313
	314	__asm__ __volatile__ (
144b9c13	315	LWSYNC_ON_SMP
14cf11af PM	316	"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
	317	cmpd 0,%0,%3\n\
	318	bne- 2f\n\
	319	stdcx. %4,0,%2\n\
	320	bne- 1b"
	321	ISYNC_ON_SMP
	322	"\n\
	323	2:"
e2a3d402 LT	324	: "=&r" (prev), "+m" (*p)
e2a3d402 LT	325	: "r" (p), "r" (old), "r" (new)
14cf11af PM	326	: "cc", "memory");
	327
	328	return prev;
	329	}
	330	#endif
	331
	332	/* This function doesn't exist, so you'll get a linker error
	333	if something tries to do an invalid cmpxchg(). */
	334	extern void __cmpxchg_called_with_bad_pointer(void);
	335
	336	static __inline__ unsigned long
	337	__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
	338	unsigned int size)
	339	{
	340	switch (size) {
	341	case 4:
	342	return __cmpxchg_u32(ptr, old, new);
	343	#ifdef CONFIG_PPC64
	344	case 8:
	345	return __cmpxchg_u64(ptr, old, new);
	346	#endif
	347	}
	348	__cmpxchg_called_with_bad_pointer();
	349	return old;
	350	}
	351
	352	#define cmpxchg(ptr,o,n) \
	353	({ \
	354	__typeof__(*(ptr)) _o_ = (o); \
	355	__typeof__(*(ptr)) _n_ = (n); \
	356	(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
	357	(unsigned long)_n_, sizeof(*(ptr))); \
	358	})
	359
	360	#ifdef CONFIG_PPC64
	361	/*
	362	* We handle most unaligned accesses in hardware. On the other hand
	363	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	364	* powers of 2 writes until it reaches sufficient alignment).
	365	*
	366	* Based on this we disable the IP header alignment in network drivers.
025be81e AB	367	* We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
025be81e AB	368	* cacheline alignment of buffers.
14cf11af	369	*/
025be81e AB	370	#define NET_IP_ALIGN 0
025be81e AB	371	#define NET_SKB_PAD L1_CACHE_BYTES
14cf11af PM	372	#endif
	373
	374	#define arch_align_stack(x) (x)
	375
9b6b563c	376	/* Used in very early kernel initialization. */
cabb5587	377	extern unsigned long reloc_offset(void);
9b6b563c PM	378	extern unsigned long add_reloc_offset(unsigned long);
	379	extern void reloc_got2(unsigned long);
	380
	381	#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
cabb5587	382
c87ef117 ME	383	static inline void create_instruction(unsigned long addr, unsigned int instr)
	384	{
	385	unsigned int *p;
	386	p = (unsigned int *)addr;
	387	*p = instr;
	388	asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
	389	}
	390
	391	/* Flags for create_branch:
	392	* "b" == create_branch(addr, target, 0);
	393	* "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
	394	* "bl" == create_branch(addr, target, BRANCH_SET_LINK);
	395	* "bla" == create_branch(addr, target, BRANCH_ABSOLUTE \| BRANCH_SET_LINK);
	396	*/
	397	#define BRANCH_SET_LINK 0x1
	398	#define BRANCH_ABSOLUTE 0x2
	399
	400	static inline void create_branch(unsigned long addr,
	401	unsigned long target, int flags)
	402	{
	403	unsigned int instruction;
	404
	405	if (! (flags & BRANCH_ABSOLUTE))
	406	target = target - addr;
	407
	408	/* Mask out the flags and target, so they don't step on each other. */
	409	instruction = 0x48000000 \| (flags & 0x3) \| (target & 0x03FFFFFC);
	410
	411	create_instruction(addr, instruction);
	412	}
	413
	414	static inline void create_function_call(unsigned long addr, void * func)
	415	{
	416	unsigned long func_addr;
	417
	418	#ifdef CONFIG_PPC64
	419	/*
	420	* On PPC64 the function pointer actually points to the function's
	421	* descriptor. The first entry in the descriptor is the address
	422	* of the function text.
	423	*/
	424	func_addr = (unsigned long )func;
	425	#else
	426	func_addr = (unsigned long)func;
	427	#endif
	428	create_branch(addr, func_addr, BRANCH_SET_LINK);
	429	}
	430
c6622f63 PM	431	#ifdef CONFIG_VIRT_CPU_ACCOUNTING
	432	extern void account_system_vtime(struct task_struct *);
	433	#endif
	434
14cf11af	435	#endif /* __KERNEL__ */
bbeb3f4c	436	#endif /* _ASM_POWERPC_SYSTEM_H */