[deliverable/linux.git] / include / asm-ppc / io.h

#ifdef __KERNEL__
#ifndef _PPC_IO_H
#define _PPC_IO_H

#include <linux/string.h>
#include <linux/types.h>

#include <asm/page.h>
#include <asm/byteorder.h>
#include <asm/synch.h>
#include <asm/mmu.h>

#define SIO_CONFIG_RA	0x398
#define SIO_CONFIG_RD	0x399

#define SLOW_DOWN_IO

#define PMAC_ISA_MEM_BASE 	0
#define PMAC_PCI_DRAM_OFFSET 	0
#define CHRP_ISA_IO_BASE 	0xf8000000
#define CHRP_ISA_MEM_BASE 	0xf7000000
#define CHRP_PCI_DRAM_OFFSET 	0
#define PREP_ISA_IO_BASE 	0x80000000
#define PREP_ISA_MEM_BASE 	0xc0000000
#define PREP_PCI_DRAM_OFFSET 	0x80000000

#if defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#elif defined(CONFIG_PPC_MPC52xx)
#include <asm/mpc52xx.h>
#elif defined(CONFIG_8xx)
#include <asm/mpc8xx.h>
#elif defined(CONFIG_8260)
#include <asm/mpc8260.h>
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
#elif defined(CONFIG_APUS)
#define _IO_BASE	0
#define _ISA_MEM_BASE	0
#define PCI_DRAM_OFFSET 0
#else /* Everyone else */
#define _IO_BASE	isa_io_base
#define _ISA_MEM_BASE	isa_mem_base
#define PCI_DRAM_OFFSET	pci_dram_offset
#endif /* Platform-dependent I/O */

#define ___IO_BASE ((void __iomem *)_IO_BASE)
extern unsigned long isa_io_base;
extern unsigned long isa_mem_base;
extern unsigned long pci_dram_offset;

/*
 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
 *
 * Read operations have additional twi & isync to make sure the read
 * is actually performed (i.e. the data has come back) before we start
 * executing any following instructions.
 */
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
	int ret;

	__asm__ __volatile__(
		"sync; lbz%U1%X1 %0,%1;\n"
		"twi 0,%0,0;\n"
		"isync" : "=r" (ret) : "m" (*addr));
	return ret;
}

extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}

extern inline int in_le16(const volatile unsigned short __iomem *addr)
{
	int ret;

	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
			     "twi 0,%0,0;\n"
			     "isync" : "=r" (ret) :
			      "r" (addr), "m" (*addr));
	return ret;
}

extern inline int in_be16(const volatile unsigned short __iomem *addr)
{
	int ret;

	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
			     "twi 0,%0,0;\n"
			     "isync" : "=r" (ret) : "m" (*addr));
	return ret;
}

extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
			      "r" (val), "r" (addr));
}

extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}

extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
{
	unsigned ret;

	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
			     "twi 0,%0,0;\n"
			     "isync" : "=r" (ret) :
			     "r" (addr), "m" (*addr));
	return ret;
}

extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
{
	unsigned ret;

	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
			     "twi 0,%0,0;\n"
			     "isync" : "=r" (ret) : "m" (*addr));
	return ret;
}

extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
			     "r" (val), "r" (addr));
}

extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
#if defined (CONFIG_8260_PCI9)
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#else
static inline __u8 readb(const volatile void __iomem *addr)
{
	return in_8(addr);
}
static inline void writeb(__u8 b, volatile void __iomem *addr)
{
	out_8(addr, b);
}
#endif

#if defined(CONFIG_APUS)
static inline __u16 readw(const volatile void __iomem *addr)
{
	return *(__force volatile __u16 *)(addr);
}
static inline __u32 readl(const volatile void __iomem *addr)
{
	return *(__force volatile __u32 *)(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
	*(__force volatile __u16 *)(addr) = b;
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
	*(__force volatile __u32 *)(addr) = b;
}
#elif defined (CONFIG_8260_PCI9)
/* Use macros if PCI9 workaround enabled */
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
#else
static inline __u16 readw(const volatile void __iomem *addr)
{
	return in_le16(addr);
}
static inline __u32 readl(const volatile void __iomem *addr)
{
	return in_le32(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
	out_le16(addr, b);
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
	out_le32(addr, b);
}
#endif /* CONFIG_APUS */

#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)

static inline __u8 __raw_readb(const volatile void __iomem *addr)
{
	return *(__force volatile __u8 *)(addr);
}
static inline __u16 __raw_readw(const volatile void __iomem *addr)
{
	return *(__force volatile __u16 *)(addr);
}
static inline __u32 __raw_readl(const volatile void __iomem *addr)
{
	return *(__force volatile __u32 *)(addr);
}
static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
{
	*(__force volatile __u8 *)(addr) = b;
}
static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
{
	*(__force volatile __u16 *)(addr) = b;
}
static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
{
	*(__force volatile __u32 *)(addr) = b;
}

#define mmiowb()

/*
 * The insw/outsw/insl/outsl macros don't do byte-swapping.
 * They are only used in practice for transferring buffers which
 * are arrays of bytes, and byte-swapping is not appropriate in
 * that case.  - paulus
 */
#define insb(port, buf, ns)	_insb((port)+___IO_BASE, (buf), (ns))
#define outsb(port, buf, ns)	_outsb((port)+___IO_BASE, (buf), (ns))
#define insw(port, buf, ns)	_insw_ns((port)+___IO_BASE, (buf), (ns))
#define outsw(port, buf, ns)	_outsw_ns((port)+___IO_BASE, (buf), (ns))
#define insl(port, buf, nl)	_insl_ns((port)+___IO_BASE, (buf), (nl))
#define outsl(port, buf, nl)	_outsl_ns((port)+___IO_BASE, (buf), (nl))

/*
 * On powermacs and 8xx we will get a machine check exception 
 * if we try to read data from a non-existent I/O port. Because
 * the machine check is an asynchronous exception, it isn't
 * well-defined which instruction SRR0 will point to when the
 * exception occurs.
 * With the sequence below (twi; isync; nop), we have found that
 * the machine check occurs on one of the three instructions on
 * all PPC implementations tested so far.  The twi and isync are
 * needed on the 601 (in fact twi; sync works too), the isync and
 * nop are needed on 604[e|r], and any of twi, sync or isync will
 * work on 603[e], 750, 74xx.
 * The twi creates an explicit data dependency on the returned
 * value which seems to be needed to make the 601 wait for the
 * load to finish.
 */

#define __do_in_asm(name, op)				\
extern __inline__ unsigned int name(unsigned int port)	\
{							\
	unsigned int x;					\
	__asm__ __volatile__(				\
		"sync\n"				\
		"0:"	op "	%0,0,%1\n"		\
		"1:	twi	0,%0,0\n"		\
		"2:	isync\n"			\
		"3:	nop\n"				\
		"4:\n"					\
		".section .fixup,\"ax\"\n"		\
		"5:	li	%0,-1\n"		\
		"	b	4b\n"			\
		".previous\n"				\
		".section __ex_table,\"a\"\n"		\
		"	.align	2\n"			\
		"	.long	0b,5b\n"		\
		"	.long	1b,5b\n"		\
		"	.long	2b,5b\n"		\
		"	.long	3b,5b\n"		\
		".previous"				\
		: "=&r" (x)				\
		: "r" (port + ___IO_BASE));		\
	return x;					\
}

#define __do_out_asm(name, op)				\
extern __inline__ void name(unsigned int val, unsigned int port) \
{							\
	__asm__ __volatile__(				\
		"sync\n"				\
		"0:" op " %0,0,%1\n"			\
		"1:	sync\n"				\
		"2:\n"					\
		".section __ex_table,\"a\"\n"		\
		"	.align	2\n"			\
		"	.long	0b,2b\n"		\
		"	.long	1b,2b\n"		\
		".previous"				\
		: : "r" (val), "r" (port + ___IO_BASE));	\
}

__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
__do_in_asm(inb, "lbzx")
__do_in_asm(inw, "lhz%U1%X1")
__do_in_asm(inl, "lwz%U1%X1")
__do_out_asm(outl,"stw%U0%X0")
__do_out_asm(outw, "sth%U0%X0")
#elif defined (CONFIG_8260_PCI9)
/* in asm cannot be defined if PCI9 workaround is used */
#define inb(port)		in_8((port)+___IO_BASE)
#define inw(port)		in_le16((port)+___IO_BASE)
#define inl(port)		in_le32((port)+___IO_BASE)
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")
#else
__do_in_asm(inb, "lbzx")
__do_in_asm(inw, "lhbrx")
__do_in_asm(inl, "lwbrx")
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")

#endif

#define inb_p(port)		inb((port))
#define outb_p(val, port)	outb((val), (port))
#define inw_p(port)		inw((port))
#define outw_p(val, port)	outw((val), (port))
#define inl_p(port)		inl((port))
#define outl_p(val, port)	outl((val), (port))

extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);


#define IO_SPACE_LIMIT ~0

#if defined (CONFIG_8260_PCI9)
#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
#else
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
	memset((void __force *)addr, val, count);
}
static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
{
	memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
	memcpy((void __force *) dst, src, count);
}
#endif

#define eth_io_copy_and_sum(a,b,c,d)		eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))

/*
 * Map in an area of physical address space, for accessing
 * I/O devices etc.
 */
extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
		       unsigned long flags);
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
#ifdef CONFIG_44x
extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
#endif
#define ioremap_nocache(addr, size)	ioremap((addr), (size))
extern void iounmap(volatile void __iomem *addr);
extern unsigned long iopa(unsigned long addr);
extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
			     unsigned int size, int flags);

/*
 * The PCI bus is inherently Little-Endian.  The PowerPC is being
 * run Big-Endian.  Thus all values which cross the [PCI] barrier
 * must be endian-adjusted.  Also, the local DRAM has a different
 * address from the PCI point of view, thus buffer addresses also
 * have to be modified [mapped] appropriately.
 */
extern inline unsigned long virt_to_bus(volatile void * address)
{
#ifndef CONFIG_APUS
        if (address == (void *)0)
		return 0;
        return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
#else
	return iopa ((unsigned long) address);
#endif
}

extern inline void * bus_to_virt(unsigned long address)
{
#ifndef CONFIG_APUS
        if (address == 0)
		return NULL;
        return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
#else
	return (void*) mm_ptov (address);
#endif
}

/*
 * Change virtual addresses to physical addresses and vv, for
 * addresses in the area where the kernel has the RAM mapped.
 */
extern inline unsigned long virt_to_phys(volatile void * address)
{
#ifndef CONFIG_APUS
	return (unsigned long) address - KERNELBASE;
#else
	return iopa ((unsigned long) address);
#endif
}

extern inline void * phys_to_virt(unsigned long address)
{
#ifndef CONFIG_APUS
	return (void *) (address + KERNELBASE);
#else
	return (void*) mm_ptov (address);
#endif
}

/*
 * Change "struct page" to physical address.
 */
#define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
#define page_to_bus(page)	(page_to_phys(page) + PCI_DRAM_OFFSET)

/* Enforce in-order execution of data I/O.
 * No distinction between read/write on PPC; use eieio for all three.
 */
#define iobarrier_rw() eieio()
#define iobarrier_r()  eieio()
#define iobarrier_w()  eieio()

static inline int check_signature(volatile void __iomem * io_addr,
	const unsigned char *signature, int length)
{
	int retval = 0;
	do {
		if (readb(io_addr) != *signature)
			goto out;
		io_addr++;
		signature++;
		length--;
	} while (length);
	retval = 1;
out:
	return retval;
}

/*
 * Here comes the ppc implementation of the IOMAP 
 * interfaces.
 */
static inline unsigned int ioread8(void __iomem *addr)
{
	return readb(addr);
}

static inline unsigned int ioread16(void __iomem *addr)
{
	return readw(addr);
}

static inline unsigned int ioread32(void __iomem *addr)
{
	return readl(addr);
}

static inline void iowrite8(u8 val, void __iomem *addr)
{
	writeb(val, addr);
}

static inline void iowrite16(u16 val, void __iomem *addr)
{
	writew(val, addr);
}

static inline void iowrite32(u32 val, void __iomem *addr)
{
	writel(val, addr);
}

static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
{
	_insb(addr, dst, count);
}

static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
{
	_insw_ns(addr, dst, count);
}

static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
{
	_insl_ns(addr, dst, count);
}

static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
{
	_outsb(addr, src, count);
}

static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
{
	_outsw_ns(addr, src, count);
}

static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
{
	_outsl_ns(addr, src, count);
}

/* Create a virtual mapping cookie for an IO port range */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *);

/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);

#endif /* _PPC_IO_H */

#ifdef CONFIG_8260_PCI9
#include <asm/mpc8260_pci9.h>
#endif

#ifdef CONFIG_NOT_COHERENT_CACHE

#define dma_cache_inv(_start,_size) \
	invalidate_dcache_range(_start, (_start + _size))
#define dma_cache_wback(_start,_size) \
	clean_dcache_range(_start, (_start + _size))
#define dma_cache_wback_inv(_start,_size) \
	flush_dcache_range(_start, (_start + _size))

#else

#define dma_cache_inv(_start,_size)		do { } while (0)
#define dma_cache_wback(_start,_size)		do { } while (0)
#define dma_cache_wback_inv(_start,_size)	do { } while (0)

#endif

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

/* access ports */
#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))

#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))

#endif /* __KERNEL__ */
Commit	Line	Data
1da177e4 LT	1	#ifdef __KERNEL__
	2	#ifndef _PPC_IO_H
	3	#define _PPC_IO_H
	4
1da177e4 LT	5	#include <linux/string.h>
	6	#include <linux/types.h>
	7
	8	#include <asm/page.h>
	9	#include <asm/byteorder.h>
feaf7cf1	10	#include <asm/synch.h>
1da177e4 LT	11	#include <asm/mmu.h>
	12
	13	#define SIO_CONFIG_RA 0x398
	14	#define SIO_CONFIG_RD 0x399
	15
	16	#define SLOW_DOWN_IO
	17
	18	#define PMAC_ISA_MEM_BASE 0
	19	#define PMAC_PCI_DRAM_OFFSET 0
	20	#define CHRP_ISA_IO_BASE 0xf8000000
	21	#define CHRP_ISA_MEM_BASE 0xf7000000
	22	#define CHRP_PCI_DRAM_OFFSET 0
	23	#define PREP_ISA_IO_BASE 0x80000000
	24	#define PREP_ISA_MEM_BASE 0xc0000000
	25	#define PREP_PCI_DRAM_OFFSET 0x80000000
	26
	27	#if defined(CONFIG_4xx)
	28	#include <asm/ibm4xx.h>
f80257a2 SM	29	#elif defined(CONFIG_PPC_MPC52xx)
f80257a2 SM	30	#include <asm/mpc52xx.h>
1da177e4 LT	31	#elif defined(CONFIG_8xx)
	32	#include <asm/mpc8xx.h>
	33	#elif defined(CONFIG_8260)
	34	#include <asm/mpc8260.h>
	35	#elif defined(CONFIG_83xx)
	36	#include <asm/mpc83xx.h>
	37	#elif defined(CONFIG_85xx)
	38	#include <asm/mpc85xx.h>
	39	#elif defined(CONFIG_APUS)
	40	#define _IO_BASE 0
	41	#define _ISA_MEM_BASE 0
	42	#define PCI_DRAM_OFFSET 0
	43	#else /* Everyone else */
	44	#define _IO_BASE isa_io_base
	45	#define _ISA_MEM_BASE isa_mem_base
	46	#define PCI_DRAM_OFFSET pci_dram_offset
	47	#endif /* Platform-dependent I/O */
	48
	49	#define ___IO_BASE ((void __iomem *)_IO_BASE)
	50	extern unsigned long isa_io_base;
	51	extern unsigned long isa_mem_base;
	52	extern unsigned long pci_dram_offset;
	53
	54	/*
	55	* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
	56	*
	57	* Read operations have additional twi & isync to make sure the read
	58	* is actually performed (i.e. the data has come back) before we start
	59	* executing any following instructions.
	60	*/
a3ca066e	61	extern inline int in_8(const volatile unsigned char __iomem *addr)
1da177e4 LT	62	{
	63	int ret;
	64
	65	__asm__ __volatile__(
f007cacf	66	"sync; lbz%U1%X1 %0,%1;\n"
1da177e4 LT	67	"twi 0,%0,0;\n"
	68	"isync" : "=r" (ret) : "m" (*addr));
	69	return ret;
	70	}
	71
	72	extern inline void out_8(volatile unsigned char __iomem *addr, int val)
	73	{
	74	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
	75	}
	76
a3ca066e	77	extern inline int in_le16(const volatile unsigned short __iomem *addr)
1da177e4 LT	78	{
	79	int ret;
	80
f007cacf	81	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
1da177e4 LT	82	"twi 0,%0,0;\n"
	83	"isync" : "=r" (ret) :
	84	"r" (addr), "m" (*addr));
	85	return ret;
	86	}
	87
a3ca066e	88	extern inline int in_be16(const volatile unsigned short __iomem *addr)
1da177e4 LT	89	{
	90	int ret;
	91
f007cacf	92	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
1da177e4 LT	93	"twi 0,%0,0;\n"
	94	"isync" : "=r" (ret) : "m" (*addr));
	95	return ret;
	96	}
	97
	98	extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
	99	{
f007cacf	100	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
1da177e4 LT	101	"r" (val), "r" (addr));
	102	}
	103
	104	extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
	105	{
f007cacf	106	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
1da177e4 LT	107	}
1da177e4 LT	108
a3ca066e	109	extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
1da177e4 LT	110	{
	111	unsigned ret;
	112
f007cacf	113	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
1da177e4 LT	114	"twi 0,%0,0;\n"
	115	"isync" : "=r" (ret) :
	116	"r" (addr), "m" (*addr));
	117	return ret;
	118	}
	119
a3ca066e	120	extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
1da177e4 LT	121	{
	122	unsigned ret;
	123
f007cacf	124	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
1da177e4 LT	125	"twi 0,%0,0;\n"
	126	"isync" : "=r" (ret) : "m" (*addr));
	127	return ret;
	128	}
	129
	130	extern inline void out_le32(volatile unsigned __iomem *addr, int val)
	131	{
f007cacf	132	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
1da177e4 LT	133	"r" (val), "r" (addr));
	134	}
	135
	136	extern inline void out_be32(volatile unsigned __iomem *addr, int val)
	137	{
f007cacf	138	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
1da177e4 LT	139	}
	140	#if defined (CONFIG_8260_PCI9)
	141	#define readb(addr) in_8((volatile u8 *)(addr))
	142	#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
	143	#else
a3ca066e	144	static inline __u8 readb(const volatile void __iomem *addr)
1da177e4 LT	145	{
	146	return in_8(addr);
	147	}
	148	static inline void writeb(__u8 b, volatile void __iomem *addr)
	149	{
	150	out_8(addr, b);
	151	}
	152	#endif
	153
	154	#if defined(CONFIG_APUS)
a3ca066e	155	static inline __u16 readw(const volatile void __iomem *addr)
1da177e4 LT	156	{
	157	return (__force volatile __u16 )(addr);
	158	}
a3ca066e	159	static inline __u32 readl(const volatile void __iomem *addr)
1da177e4 LT	160	{
	161	return (__force volatile __u32 )(addr);
	162	}
	163	static inline void writew(__u16 b, volatile void __iomem *addr)
	164	{
	165	(__force volatile __u16 )(addr) = b;
	166	}
	167	static inline void writel(__u32 b, volatile void __iomem *addr)
	168	{
	169	(__force volatile __u32 )(addr) = b;
	170	}
	171	#elif defined (CONFIG_8260_PCI9)
	172	/* Use macros if PCI9 workaround enabled */
	173	#define readw(addr) in_le16((volatile u16 *)(addr))
	174	#define readl(addr) in_le32((volatile u32 *)(addr))
	175	#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
	176	#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
	177	#else
a3ca066e	178	static inline __u16 readw(const volatile void __iomem *addr)
1da177e4 LT	179	{
	180	return in_le16(addr);
	181	}
a3ca066e	182	static inline __u32 readl(const volatile void __iomem *addr)
1da177e4 LT	183	{
	184	return in_le32(addr);
	185	}
	186	static inline void writew(__u16 b, volatile void __iomem *addr)
	187	{
	188	out_le16(addr, b);
	189	}
	190	static inline void writel(__u32 b, volatile void __iomem *addr)
	191	{
	192	out_le32(addr, b);
	193	}
	194	#endif /* CONFIG_APUS */
	195
	196	#define readb_relaxed(addr) readb(addr)
	197	#define readw_relaxed(addr) readw(addr)
	198	#define readl_relaxed(addr) readl(addr)
	199
	200	static inline __u8 __raw_readb(const volatile void __iomem *addr)
	201	{
	202	return (__force volatile __u8 )(addr);
	203	}
	204	static inline __u16 __raw_readw(const volatile void __iomem *addr)
	205	{
	206	return (__force volatile __u16 )(addr);
	207	}
	208	static inline __u32 __raw_readl(const volatile void __iomem *addr)
	209	{
	210	return (__force volatile __u32 )(addr);
	211	}
	212	static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
	213	{
	214	(__force volatile __u8 )(addr) = b;
	215	}
	216	static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
	217	{
	218	(__force volatile __u16 )(addr) = b;
	219	}
	220	static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
	221	{
	222	(__force volatile __u32 )(addr) = b;
	223	}
	224
	225	#define mmiowb()
	226
	227	/*
	228	* The insw/outsw/insl/outsl macros don't do byte-swapping.
	229	* They are only used in practice for transferring buffers which
	230	* are arrays of bytes, and byte-swapping is not appropriate in
	231	* that case. - paulus
	232	*/
	233	#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
	234	#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
	235	#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
	236	#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
	237	#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
	238	#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
	239
	240	/*
55b6332e MT	241	* On powermacs and 8xx we will get a machine check exception
	242	* if we try to read data from a non-existent I/O port. Because
	243	* the machine check is an asynchronous exception, it isn't
1da177e4 LT	244	* well-defined which instruction SRR0 will point to when the
	245	* exception occurs.
	246	* With the sequence below (twi; isync; nop), we have found that
	247	* the machine check occurs on one of the three instructions on
	248	* all PPC implementations tested so far. The twi and isync are
	249	* needed on the 601 (in fact twi; sync works too), the isync and
	250	* nop are needed on 604[e\|r], and any of twi, sync or isync will
	251	* work on 603[e], 750, 74xx.
	252	* The twi creates an explicit data dependency on the returned
	253	* value which seems to be needed to make the 601 wait for the
	254	* load to finish.
	255	*/
	256
	257	#define __do_in_asm(name, op) \
	258	extern __inline__ unsigned int name(unsigned int port) \
	259	{ \
	260	unsigned int x; \
	261	__asm__ __volatile__( \
f007cacf	262	"sync\n" \
55b6332e	263	"0:" op " %0,0,%1\n" \
1da177e4 LT	264	"1: twi 0,%0,0\n" \
	265	"2: isync\n" \
	266	"3: nop\n" \
	267	"4:\n" \
	268	".section .fixup,\"ax\"\n" \
	269	"5: li %0,-1\n" \
	270	" b 4b\n" \
	271	".previous\n" \
	272	".section __ex_table,\"a\"\n" \
	273	" .align 2\n" \
55b6332e	274	" .long 0b,5b\n" \
1da177e4 LT	275	" .long 1b,5b\n" \
	276	" .long 2b,5b\n" \
	277	" .long 3b,5b\n" \
	278	".previous" \
	279	: "=&r" (x) \
	280	: "r" (port + ___IO_BASE)); \
	281	return x; \
	282	}
	283
	284	#define __do_out_asm(name, op) \
	285	extern __inline__ void name(unsigned int val, unsigned int port) \
	286	{ \
	287	__asm__ __volatile__( \
f007cacf	288	"sync\n" \
55b6332e	289	"0:" op " %0,0,%1\n" \
1da177e4 LT	290	"1: sync\n" \
	291	"2:\n" \
	292	".section __ex_table,\"a\"\n" \
	293	" .align 2\n" \
55b6332e	294	" .long 0b,2b\n" \
1da177e4 LT	295	" .long 1b,2b\n" \
	296	".previous" \
	297	: : "r" (val), "r" (port + ___IO_BASE)); \
	298	}
	299
	300	__do_out_asm(outb, "stbx")
	301	#ifdef CONFIG_APUS
	302	__do_in_asm(inb, "lbzx")
	303	__do_in_asm(inw, "lhz%U1%X1")
	304	__do_in_asm(inl, "lwz%U1%X1")
	305	__do_out_asm(outl,"stw%U0%X0")
	306	__do_out_asm(outw, "sth%U0%X0")
	307	#elif defined (CONFIG_8260_PCI9)
	308	/* in asm cannot be defined if PCI9 workaround is used */
	309	#define inb(port) in_8((port)+___IO_BASE)
	310	#define inw(port) in_le16((port)+___IO_BASE)
	311	#define inl(port) in_le32((port)+___IO_BASE)
	312	__do_out_asm(outw, "sthbrx")
	313	__do_out_asm(outl, "stwbrx")
	314	#else
	315	__do_in_asm(inb, "lbzx")
	316	__do_in_asm(inw, "lhbrx")
	317	__do_in_asm(inl, "lwbrx")
	318	__do_out_asm(outw, "sthbrx")
	319	__do_out_asm(outl, "stwbrx")
	320
	321	#endif
	322
	323	#define inb_p(port) inb((port))
	324	#define outb_p(val, port) outb((val), (port))
	325	#define inw_p(port) inw((port))
	326	#define outw_p(val, port) outw((val), (port))
	327	#define inl_p(port) inl((port))
	328	#define outl_p(val, port) outl((val), (port))
	329
	330	extern void _insb(volatile u8 __iomem port, void buf, int ns);
	331	extern void _outsb(volatile u8 __iomem port, const void buf, int ns);
	332	extern void _insw(volatile u16 __iomem port, void buf, int ns);
	333	extern void _outsw(volatile u16 __iomem port, const void buf, int ns);
	334	extern void _insl(volatile u32 __iomem port, void buf, int nl);
	335	extern void _outsl(volatile u32 __iomem port, const void buf, int nl);
	336	extern void _insw_ns(volatile u16 __iomem port, void buf, int ns);
	337	extern void _outsw_ns(volatile u16 __iomem port, const void buf, int ns);
	338	extern void _insl_ns(volatile u32 __iomem port, void buf, int nl);
	339	extern void _outsl_ns(volatile u32 __iomem port, const void buf, int nl);
	340
1da177e4 LT	341
	342	#define IO_SPACE_LIMIT ~0
	343
	344	#if defined (CONFIG_8260_PCI9)
	345	#define memset_io(a,b,c) memset((void *)(a),(b),(c))
	346	#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
	347	#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
	348	#else
	349	static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
	350	{
	351	memset((void __force *)addr, val, count);
	352	}
	353	static inline void memcpy_fromio(void dst,const volatile void __iomem src, int count)
	354	{
	355	memcpy(dst, (void __force *) src, count);
	356	}
	357	static inline void memcpy_toio(volatile void __iomem dst, const void src, int count)
	358	{
	359	memcpy((void __force *) dst, src, count);
	360	}
	361	#endif
	362
	363	#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force )(void __iomem )(b),(c),(d))
	364
	365	/*
	366	* Map in an area of physical address space, for accessing
	367	* I/O devices etc.
	368	*/
	369	extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
	370	unsigned long flags);
	371	extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
	372	#ifdef CONFIG_44x
	373	extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
	374	#endif
	375	#define ioremap_nocache(addr, size) ioremap((addr), (size))
	376	extern void iounmap(volatile void __iomem *addr);
	377	extern unsigned long iopa(unsigned long addr);
	378	extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
	379	extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
	380	unsigned int size, int flags);
	381
	382	/*
	383	* The PCI bus is inherently Little-Endian. The PowerPC is being
	384	* run Big-Endian. Thus all values which cross the [PCI] barrier
	385	* must be endian-adjusted. Also, the local DRAM has a different
	386	* address from the PCI point of view, thus buffer addresses also
	387	* have to be modified [mapped] appropriately.
	388	*/
	389	extern inline unsigned long virt_to_bus(volatile void * address)
	390	{
	391	#ifndef CONFIG_APUS
	392	if (address == (void *)0)
	393	return 0;
	394	return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
	395	#else
	396	return iopa ((unsigned long) address);
	397	#endif
	398	}
	399
	400	extern inline void * bus_to_virt(unsigned long address)
	401	{
	402	#ifndef CONFIG_APUS
	403	if (address == 0)
	404	return NULL;
405	return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
406	#else
407	return (void*) mm_ptov (address);
408	#endif
409	}
410
411	/*
412	* Change virtual addresses to physical addresses and vv, for
413	* addresses in the area where the kernel has the RAM mapped.
414	*/
415	extern inline unsigned long virt_to_phys(volatile void * address)
416	{
417	#ifndef CONFIG_APUS
418	return (unsigned long) address - KERNELBASE;
419	#else
420	return iopa ((unsigned long) address);
421	#endif
422	}
423
424	extern inline void * phys_to_virt(unsigned long address)
425	{
426	#ifndef CONFIG_APUS
427	return (void *) (address + KERNELBASE);
428	#else
429	return (void*) mm_ptov (address);
430	#endif
431	}
432
433	/*
434	* Change "struct page" to physical address.
435	*/
436	#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
437	#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
438
1da177e4 LT	439	/* Enforce in-order execution of data I/O.
	440	* No distinction between read/write on PPC; use eieio for all three.
	441	*/
	442	#define iobarrier_rw() eieio()
	443	#define iobarrier_r() eieio()
	444	#define iobarrier_w() eieio()
	445
	446	static inline int check_signature(volatile void __iomem * io_addr,
	447	const unsigned char *signature, int length)
	448	{
	449	int retval = 0;
	450	do {
	451	if (readb(io_addr) != *signature)
	452	goto out;
	453	io_addr++;
	454	signature++;
	455	length--;
	456	} while (length);
	457	retval = 1;
	458	out:
	459	return retval;
	460	}
	461
	462	/*
	463	* Here comes the ppc implementation of the IOMAP
	464	* interfaces.
	465	*/
	466	static inline unsigned int ioread8(void __iomem *addr)
	467	{
	468	return readb(addr);
	469	}
	470
	471	static inline unsigned int ioread16(void __iomem *addr)
	472	{
	473	return readw(addr);
	474	}
	475
	476	static inline unsigned int ioread32(void __iomem *addr)
	477	{
	478	return readl(addr);
	479	}
	480
	481	static inline void iowrite8(u8 val, void __iomem *addr)
	482	{
	483	writeb(val, addr);
	484	}
	485
	486	static inline void iowrite16(u16 val, void __iomem *addr)
	487	{
	488	writew(val, addr);
	489	}
	490
	491	static inline void iowrite32(u32 val, void __iomem *addr)
	492	{
	493	writel(val, addr);
	494	}
	495
	496	static inline void ioread8_rep(void __iomem addr, void dst, unsigned long count)
	497	{
	498	_insb(addr, dst, count);
	499	}
	500
	501	static inline void ioread16_rep(void __iomem addr, void dst, unsigned long count)
	502	{
503	_insw_ns(addr, dst, count);
504	}
505
506	static inline void ioread32_rep(void __iomem addr, void dst, unsigned long count)
507	{
508	_insl_ns(addr, dst, count);
509	}
510
511	static inline void iowrite8_rep(void __iomem addr, const void src, unsigned long count)
512	{
513	_outsb(addr, src, count);
514	}
515
516	static inline void iowrite16_rep(void __iomem addr, const void src, unsigned long count)
517	{
518	_outsw_ns(addr, src, count);
519	}
520
521	static inline void iowrite32_rep(void __iomem addr, const void src, unsigned long count)
522	{
523	_outsl_ns(addr, src, count);
524	}
525
526	/* Create a virtual mapping cookie for an IO port range */
527	extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
528	extern void ioport_unmap(void __iomem *);
529
530	/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
531	struct pci_dev;
532	extern void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long max);
533	extern void pci_iounmap(struct pci_dev dev, void __iomem );
534
535	#endif /* _PPC_IO_H */
536
537	#ifdef CONFIG_8260_PCI9
538	#include <asm/mpc8260_pci9.h>
539	#endif
540
78baa2f8 SR	541	#ifdef CONFIG_NOT_COHERENT_CACHE
	542
	543	#define dma_cache_inv(_start,_size) \
	544	invalidate_dcache_range(_start, (_start + _size))
	545	#define dma_cache_wback(_start,_size) \
	546	clean_dcache_range(_start, (_start + _size))
	547	#define dma_cache_wback_inv(_start,_size) \
	548	flush_dcache_range(_start, (_start + _size))
	549
	550	#else
	551
	552	#define dma_cache_inv(_start,_size) do { } while (0)
	553	#define dma_cache_wback(_start,_size) do { } while (0)
	554	#define dma_cache_wback_inv(_start,_size) do { } while (0)
	555
	556	#endif
	557
1da177e4 LT	558	/*
	559	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	560	* access
	561	*/
	562	#define xlate_dev_mem_ptr(p) __va(p)
	563
	564	/*
	565	* Convert a virtual cached pointer to an uncached pointer
	566	*/
	567	#define xlate_dev_kmem_ptr(p) p
	568
0ce928e1 VB	569	/* access ports */
	570	#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) \| (_v))
	571	#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
	572
	573	#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) \| (_v))
	574	#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
	575
1da177e4	576	#endif /* __KERNEL__ */