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1da177e4 LT |
1 | #ifdef __KERNEL__ |
2 | #ifndef _ASM_IRQ_H | |
3 | #define _ASM_IRQ_H | |
4 | ||
5 | #include <linux/config.h> | |
6 | #include <asm/machdep.h> /* ppc_md */ | |
7 | #include <asm/atomic.h> | |
8 | ||
9 | /* | |
10 | * These constants are used for passing information about interrupt | |
11 | * signal polarity and level/edge sensing to the low-level PIC chip | |
12 | * drivers. | |
13 | */ | |
14 | #define IRQ_SENSE_MASK 0x1 | |
15 | #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ | |
16 | #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ | |
17 | ||
18 | #define IRQ_POLARITY_MASK 0x2 | |
19 | #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ | |
20 | #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ | |
21 | ||
f26fdd59 KW |
22 | /* |
23 | * IRQ line status macro IRQ_PER_CPU is used | |
24 | */ | |
25 | #define ARCH_HAS_IRQ_PER_CPU | |
26 | ||
1da177e4 LT |
27 | #if defined(CONFIG_40x) |
28 | #include <asm/ibm4xx.h> | |
29 | ||
30 | #ifndef NR_BOARD_IRQS | |
31 | #define NR_BOARD_IRQS 0 | |
32 | #endif | |
33 | ||
34 | #ifndef UIC_WIDTH /* Number of interrupts per device */ | |
35 | #define UIC_WIDTH 32 | |
36 | #endif | |
37 | ||
38 | #ifndef NR_UICS /* number of UIC devices */ | |
39 | #define NR_UICS 1 | |
40 | #endif | |
41 | ||
42 | #if defined (CONFIG_403) | |
43 | /* | |
44 | * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has | |
45 | * 32 possible interrupts, a majority of which are not implemented on | |
46 | * all cores. There are six configurable, external interrupt pins and | |
47 | * there are eight internal interrupts for the on-chip serial port | |
48 | * (SPU), DMA controller, and JTAG controller. | |
49 | * | |
50 | */ | |
51 | ||
52 | #define NR_AIC_IRQS 32 | |
53 | #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) | |
54 | ||
55 | #elif !defined (CONFIG_403) | |
56 | ||
57 | /* | |
58 | * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 | |
59 | * possible interrupts as well. There are seven, configurable external | |
60 | * interrupt pins and there are 17 internal interrupts for the on-chip | |
61 | * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. | |
62 | * | |
63 | */ | |
64 | ||
65 | ||
66 | #define NR_UIC_IRQS UIC_WIDTH | |
67 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | |
68 | #endif | |
69 | static __inline__ int | |
70 | irq_canonicalize(int irq) | |
71 | { | |
72 | return (irq); | |
73 | } | |
74 | ||
75 | #elif defined(CONFIG_44x) | |
76 | #include <asm/ibm44x.h> | |
77 | ||
78 | #define NR_UIC_IRQS 32 | |
79 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | |
80 | ||
81 | static __inline__ int | |
82 | irq_canonicalize(int irq) | |
83 | { | |
84 | return (irq); | |
85 | } | |
86 | ||
87 | #elif defined(CONFIG_8xx) | |
88 | ||
89 | /* Now include the board configuration specific associations. | |
90 | */ | |
91 | #include <asm/mpc8xx.h> | |
92 | ||
93 | /* The MPC8xx cores have 16 possible interrupts. There are eight | |
94 | * possible level sensitive interrupts assigned and generated internally | |
95 | * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. | |
96 | * There are eight external interrupts (IRQs) that can be configured | |
97 | * as either level or edge sensitive. | |
98 | * | |
99 | * On some implementations, there is also the possibility of an 8259 | |
100 | * through the PCI and PCI-ISA bridges. | |
101 | * | |
102 | * We are "flattening" the interrupt vectors of the cascaded CPM | |
103 | * and 8259 interrupt controllers so that we can uniquely identify | |
104 | * any interrupt source with a single integer. | |
105 | */ | |
106 | #define NR_SIU_INTS 16 | |
107 | #define NR_CPM_INTS 32 | |
108 | #ifndef NR_8259_INTS | |
109 | #define NR_8259_INTS 0 | |
110 | #endif | |
111 | ||
112 | #define SIU_IRQ_OFFSET 0 | |
113 | #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS) | |
114 | #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | |
115 | ||
116 | #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS) | |
117 | ||
118 | /* These values must be zero-based and map 1:1 with the SIU configuration. | |
119 | * They are used throughout the 8xx I/O subsystem to generate | |
120 | * interrupt masks, flags, and other control patterns. This is why the | |
121 | * current kernel assumption of the 8259 as the base controller is such | |
122 | * a pain in the butt. | |
123 | */ | |
124 | #define SIU_IRQ0 (0) /* Highest priority */ | |
125 | #define SIU_LEVEL0 (1) | |
126 | #define SIU_IRQ1 (2) | |
127 | #define SIU_LEVEL1 (3) | |
128 | #define SIU_IRQ2 (4) | |
129 | #define SIU_LEVEL2 (5) | |
130 | #define SIU_IRQ3 (6) | |
131 | #define SIU_LEVEL3 (7) | |
132 | #define SIU_IRQ4 (8) | |
133 | #define SIU_LEVEL4 (9) | |
134 | #define SIU_IRQ5 (10) | |
135 | #define SIU_LEVEL5 (11) | |
136 | #define SIU_IRQ6 (12) | |
137 | #define SIU_LEVEL6 (13) | |
138 | #define SIU_IRQ7 (14) | |
139 | #define SIU_LEVEL7 (15) | |
140 | ||
141 | /* The internal interrupts we can configure as we see fit. | |
142 | * My personal preference is CPM at level 2, which puts it above the | |
143 | * MBX PCI/ISA/IDE interrupts. | |
144 | */ | |
145 | #ifndef PIT_INTERRUPT | |
146 | #define PIT_INTERRUPT SIU_LEVEL0 | |
147 | #endif | |
148 | #ifndef CPM_INTERRUPT | |
149 | #define CPM_INTERRUPT SIU_LEVEL2 | |
150 | #endif | |
151 | #ifndef PCMCIA_INTERRUPT | |
152 | #define PCMCIA_INTERRUPT SIU_LEVEL6 | |
153 | #endif | |
154 | #ifndef DEC_INTERRUPT | |
155 | #define DEC_INTERRUPT SIU_LEVEL7 | |
156 | #endif | |
157 | ||
158 | /* Some internal interrupt registers use an 8-bit mask for the interrupt | |
159 | * level instead of a number. | |
160 | */ | |
161 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | |
162 | ||
163 | /* always the same on 8xx -- Cort */ | |
164 | static __inline__ int irq_canonicalize(int irq) | |
165 | { | |
166 | return irq; | |
167 | } | |
168 | ||
169 | #elif defined(CONFIG_83xx) | |
170 | #include <asm/mpc83xx.h> | |
171 | ||
172 | static __inline__ int irq_canonicalize(int irq) | |
173 | { | |
174 | return irq; | |
175 | } | |
176 | ||
177 | #define NR_IRQS (NR_IPIC_INTS) | |
178 | ||
179 | #elif defined(CONFIG_85xx) | |
180 | /* Now include the board configuration specific associations. | |
181 | */ | |
182 | #include <asm/mpc85xx.h> | |
183 | ||
65145e06 | 184 | /* The MPC8548 openpic has 48 internal interrupts and 12 external |
1da177e4 LT |
185 | * interrupts. |
186 | * | |
187 | * We are "flattening" the interrupt vectors of the cascaded CPM | |
188 | * so that we can uniquely identify any interrupt source with a | |
189 | * single integer. | |
190 | */ | |
191 | #define NR_CPM_INTS 64 | |
65145e06 | 192 | #define NR_EPIC_INTS 60 |
1da177e4 LT |
193 | #ifndef NR_8259_INTS |
194 | #define NR_8259_INTS 0 | |
195 | #endif | |
196 | #define NUM_8259_INTERRUPTS NR_8259_INTS | |
197 | ||
198 | #ifndef CPM_IRQ_OFFSET | |
199 | #define CPM_IRQ_OFFSET 0 | |
200 | #endif | |
201 | ||
202 | #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) | |
203 | ||
204 | /* Internal IRQs on MPC85xx OpenPIC */ | |
205 | ||
206 | #ifndef MPC85xx_OPENPIC_IRQ_OFFSET | |
207 | #ifdef CONFIG_CPM2 | |
208 | #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | |
209 | #else | |
210 | #define MPC85xx_OPENPIC_IRQ_OFFSET 0 | |
211 | #endif | |
212 | #endif | |
213 | ||
214 | /* Not all of these exist on all MPC85xx implementations */ | |
215 | #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
216 | #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
217 | #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
218 | #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
219 | #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
220 | #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
221 | #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
222 | #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
223 | #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
224 | #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
225 | #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
226 | #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
227 | #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
228 | #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
229 | #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
230 | #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
5b37b700 KG |
231 | #define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) |
232 | #define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
233 | #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
1da177e4 LT |
234 | #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) |
235 | #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
236 | #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
5b37b700 KG |
237 | #define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) |
238 | #define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
239 | #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
1da177e4 LT |
240 | #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) |
241 | #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
242 | #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
243 | #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
244 | #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
245 | #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
246 | #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
247 | ||
248 | /* The 12 external interrupt lines */ | |
65145e06 KG |
249 | #define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) |
250 | #define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
251 | #define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
252 | #define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
253 | #define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
254 | #define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
255 | #define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
256 | #define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
257 | #define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
258 | #define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
259 | #define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
260 | #define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) | |
1da177e4 LT |
261 | |
262 | /* CPM related interrupts */ | |
263 | #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) | |
264 | #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) | |
265 | #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) | |
266 | #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) | |
267 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) | |
268 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) | |
269 | #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) | |
270 | #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) | |
271 | #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) | |
272 | #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) | |
273 | #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) | |
274 | #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) | |
275 | #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) | |
276 | #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) | |
277 | #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) | |
278 | #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) | |
279 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) | |
280 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) | |
281 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) | |
282 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) | |
283 | #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) | |
284 | #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) | |
285 | #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) | |
286 | #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) | |
287 | #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) | |
288 | #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) | |
289 | #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) | |
290 | #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) | |
291 | #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) | |
292 | #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) | |
293 | #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) | |
294 | #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) | |
295 | #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) | |
296 | #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) | |
297 | #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) | |
298 | #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) | |
299 | ||
300 | static __inline__ int irq_canonicalize(int irq) | |
301 | { | |
302 | return irq; | |
303 | } | |
304 | ||
305 | #else /* CONFIG_40x + CONFIG_8xx */ | |
306 | /* | |
307 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) | |
308 | * so it is the max of them all | |
309 | */ | |
310 | #define NR_IRQS 256 | |
311 | ||
312 | #ifndef CONFIG_8260 | |
313 | ||
314 | #define NUM_8259_INTERRUPTS 16 | |
315 | ||
316 | #else /* CONFIG_8260 */ | |
317 | ||
318 | /* The 8260 has an internal interrupt controller with a maximum of | |
319 | * 64 IRQs. We will use NR_IRQs from above since it is large enough. | |
320 | * Don't be confused by the 8260 documentation where they list an | |
321 | * "interrupt number" and "interrupt vector". We are only interested | |
322 | * in the interrupt vector. There are "reserved" holes where the | |
323 | * vector number increases, but the interrupt number in the table does not. | |
324 | * (Document errata updates have fixed this...make sure you have up to | |
325 | * date processor documentation -- Dan). | |
326 | */ | |
327 | ||
328 | #ifndef CPM_IRQ_OFFSET | |
329 | #define CPM_IRQ_OFFSET 0 | |
330 | #endif | |
331 | ||
332 | #define NR_CPM_INTS 64 | |
333 | ||
334 | #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET) | |
335 | #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET) | |
336 | #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET) | |
337 | #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET) | |
338 | #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET) | |
339 | #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET) | |
340 | #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET) | |
341 | #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET) | |
342 | #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET) | |
343 | #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET) | |
344 | #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET) | |
8e8fff09 | 345 | #define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET) |
1da177e4 LT |
346 | #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET) |
347 | #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET) | |
348 | #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET) | |
349 | #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET) | |
350 | #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET) | |
351 | #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET) | |
352 | #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET) | |
353 | #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET) | |
354 | #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET) | |
355 | #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET) | |
356 | #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET) | |
357 | #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET) | |
358 | #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET) | |
359 | #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET) | |
360 | #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET) | |
361 | #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET) | |
362 | #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET) | |
363 | #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET) | |
364 | #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET) | |
365 | #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET) | |
366 | #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET) | |
367 | #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET) | |
368 | #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET) | |
369 | #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET) | |
370 | #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET) | |
371 | #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET) | |
372 | #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET) | |
373 | #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET) | |
374 | #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET) | |
375 | #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET) | |
376 | #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET) | |
377 | #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET) | |
378 | #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET) | |
379 | #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET) | |
380 | #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET) | |
381 | #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET) | |
382 | #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET) | |
383 | #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET) | |
384 | ||
385 | #endif /* CONFIG_8260 */ | |
386 | ||
387 | /* | |
388 | * This gets called from serial.c, which is now used on | |
389 | * powermacs as well as prep/chrp boxes. | |
390 | * Prep and chrp both have cascaded 8259 PICs. | |
391 | */ | |
392 | static __inline__ int irq_canonicalize(int irq) | |
393 | { | |
394 | if (ppc_md.irq_canonicalize) | |
395 | return ppc_md.irq_canonicalize(irq); | |
396 | return irq; | |
397 | } | |
398 | ||
399 | #endif | |
400 | ||
401 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) | |
402 | /* pedantic: these are long because they are used with set_bit --RR */ | |
403 | extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; | |
404 | extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | |
405 | extern atomic_t ppc_n_lost_interrupts; | |
406 | ||
1da177e4 LT |
407 | #endif /* _ASM_IRQ_H */ |
408 | #endif /* __KERNEL__ */ |