[deliverable/linux.git] / include / asm-ppc / irq.h

#ifdef __KERNEL__
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H

#include <linux/config.h>
#include <asm/machdep.h>		/* ppc_md */
#include <asm/atomic.h>

/*
 * These constants are used for passing information about interrupt
 * signal polarity and level/edge sensing to the low-level PIC chip
 * drivers.
 */
#define IRQ_SENSE_MASK		0x1
#define IRQ_SENSE_LEVEL		0x1	/* interrupt on active level */
#define IRQ_SENSE_EDGE		0x0	/* interrupt triggered by edge */

#define IRQ_POLARITY_MASK	0x2
#define IRQ_POLARITY_POSITIVE	0x2	/* high level or low->high edge */
#define IRQ_POLARITY_NEGATIVE	0x0	/* low level or high->low edge */

/*
 * IRQ line status macro IRQ_PER_CPU is used
 */
#define ARCH_HAS_IRQ_PER_CPU

#define get_irq_desc(irq) (&irq_desc[(irq)])

/* Define a way to iterate across irqs. */
#define for_each_irq(i) \
	for ((i) = 0; (i) < NR_IRQS; ++(i))

#if defined(CONFIG_40x)
#include <asm/ibm4xx.h>

#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif

#ifndef UIC_WIDTH /* Number of interrupts per device */
#define UIC_WIDTH 32
#endif

#ifndef NR_UICS /* number  of UIC devices */
#define NR_UICS 1
#endif

#if defined (CONFIG_403)
/*
 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
 * 32 possible interrupts, a majority of which are not implemented on
 * all cores. There are six configurable, external interrupt pins and
 * there are eight internal interrupts for the on-chip serial port
 * (SPU), DMA controller, and JTAG controller.
 *
 */

#define	NR_AIC_IRQS 32
#define	NR_IRQS	 (NR_AIC_IRQS + NR_BOARD_IRQS)

#elif !defined (CONFIG_403)

/*
 *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
 * possible interrupts as well. There are seven, configurable external
 * interrupt pins and there are 17 internal interrupts for the on-chip
 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
 *
 */


#define NR_UIC_IRQS UIC_WIDTH
#define NR_IRQS		((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
#endif
static __inline__ int
irq_canonicalize(int irq)
{
	return (irq);
}

#elif defined(CONFIG_44x)
#include <asm/ibm44x.h>

#define	NR_UIC_IRQS	32
#define	NR_IRQS		((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)

static __inline__ int
irq_canonicalize(int irq)
{
	return (irq);
}

#elif defined(CONFIG_8xx)

/* Now include the board configuration specific associations.
*/
#include <asm/mpc8xx.h>

/* The MPC8xx cores have 16 possible interrupts.  There are eight
 * possible level sensitive interrupts assigned and generated internally
 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
 * There are eight external interrupts (IRQs) that can be configured
 * as either level or edge sensitive.
 *
 * On some implementations, there is also the possibility of an 8259
 * through the PCI and PCI-ISA bridges.
 *
 * We are "flattening" the interrupt vectors of the cascaded CPM
 * and 8259 interrupt controllers so that we can uniquely identify
 * any interrupt source with a single integer.
 */
#define NR_SIU_INTS	16
#define NR_CPM_INTS	32
#ifndef NR_8259_INTS
#define NR_8259_INTS 0
#endif

#define SIU_IRQ_OFFSET		0
#define CPM_IRQ_OFFSET		(SIU_IRQ_OFFSET + NR_SIU_INTS)
#define I8259_IRQ_OFFSET	(CPM_IRQ_OFFSET + NR_CPM_INTS)

#define NR_IRQS	(NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)

/* These values must be zero-based and map 1:1 with the SIU configuration.
 * They are used throughout the 8xx I/O subsystem to generate
 * interrupt masks, flags, and other control patterns.  This is why the
 * current kernel assumption of the 8259 as the base controller is such
 * a pain in the butt.
 */
#define	SIU_IRQ0	(0)	/* Highest priority */
#define	SIU_LEVEL0	(1)
#define	SIU_IRQ1	(2)
#define	SIU_LEVEL1	(3)
#define	SIU_IRQ2	(4)
#define	SIU_LEVEL2	(5)
#define	SIU_IRQ3	(6)
#define	SIU_LEVEL3	(7)
#define	SIU_IRQ4	(8)
#define	SIU_LEVEL4	(9)
#define	SIU_IRQ5	(10)
#define	SIU_LEVEL5	(11)
#define	SIU_IRQ6	(12)
#define	SIU_LEVEL6	(13)
#define	SIU_IRQ7	(14)
#define	SIU_LEVEL7	(15)

#define MPC8xx_INT_FEC1		SIU_LEVEL1
#define MPC8xx_INT_FEC2		SIU_LEVEL3

#define MPC8xx_INT_SCC1		(CPM_IRQ_OFFSET + CPMVEC_SCC1)
#define MPC8xx_INT_SCC2		(CPM_IRQ_OFFSET + CPMVEC_SCC2)
#define MPC8xx_INT_SCC3		(CPM_IRQ_OFFSET + CPMVEC_SCC3)
#define MPC8xx_INT_SCC4		(CPM_IRQ_OFFSET + CPMVEC_SCC4)
#define MPC8xx_INT_SMC1		(CPM_IRQ_OFFSET + CPMVEC_SMC1)
#define MPC8xx_INT_SMC2		(CPM_IRQ_OFFSET + CPMVEC_SMC2)

/* The internal interrupts we can configure as we see fit.
 * My personal preference is CPM at level 2, which puts it above the
 * MBX PCI/ISA/IDE interrupts.
 */
#ifndef PIT_INTERRUPT
#define PIT_INTERRUPT		SIU_LEVEL0
#endif
#ifndef	CPM_INTERRUPT
#define CPM_INTERRUPT		SIU_LEVEL2
#endif
#ifndef	PCMCIA_INTERRUPT
#define PCMCIA_INTERRUPT	SIU_LEVEL6
#endif
#ifndef	DEC_INTERRUPT
#define DEC_INTERRUPT		SIU_LEVEL7
#endif

/* Some internal interrupt registers use an 8-bit mask for the interrupt
 * level instead of a number.
 */
#define	mk_int_int_mask(IL) (1 << (7 - (IL/2)))

/* always the same on 8xx -- Cort */
static __inline__ int irq_canonicalize(int irq)
{
	return irq;
}

#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>

static __inline__ int irq_canonicalize(int irq)
{
	return irq;
}

#define	NR_IRQS	(NR_IPIC_INTS)

#elif defined(CONFIG_85xx)
/* Now include the board configuration specific associations.
*/
#include <asm/mpc85xx.h>

/* The MPC8548 openpic has 48 internal interrupts and 12 external
 * interrupts.
 *
 * We are "flattening" the interrupt vectors of the cascaded CPM
 * so that we can uniquely identify any interrupt source with a
 * single integer.
 */
#define NR_CPM_INTS	64
#define NR_EPIC_INTS	60
#ifndef NR_8259_INTS
#define NR_8259_INTS	0
#endif
#define NUM_8259_INTERRUPTS NR_8259_INTS

#ifndef CPM_IRQ_OFFSET
#define CPM_IRQ_OFFSET	0
#endif

#define NR_IRQS	(NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)

/* Internal IRQs on MPC85xx OpenPIC */

#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
#ifdef CONFIG_CPM2
#define MPC85xx_OPENPIC_IRQ_OFFSET	(CPM_IRQ_OFFSET + NR_CPM_INTS)
#else
#define MPC85xx_OPENPIC_IRQ_OFFSET	0
#endif
#endif

/* Not all of these exist on all MPC85xx implementations */
#define MPC85xx_IRQ_L2CACHE	( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_ECM		( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DDR		( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_LBIU	( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA0	( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA1	( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA2	( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA3	( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PCI1	( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PCI2	( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_ERROR	( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_BELL	(10 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_TX	(11 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_RX	(12 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_TX	(13 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_RX	(14 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC3_TX	(15 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC3_RX	(16 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC3_ERROR	(17 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_ERROR	(18 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_TX	(19 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_RX	(20 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC4_TX	(21 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC4_RX	(22 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC4_ERROR	(23 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_ERROR	(24 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_FEC		(25 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DUART	(26 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_IIC1	(27 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PERFMON	(28 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_SEC2	(29 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_CPM		(30 + MPC85xx_OPENPIC_IRQ_OFFSET)

/* The 12 external interrupt lines */
#define MPC85xx_IRQ_EXT0        (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT1        (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT2        (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT3        (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT4        (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT5        (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT6        (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT7        (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT8        (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT9        (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT10       (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT11       (59 + MPC85xx_OPENPIC_IRQ_OFFSET)

/* CPM related interrupts */
#define	SIU_INT_ERROR		((uint)0x00+CPM_IRQ_OFFSET)
#define	SIU_INT_I2C		((uint)0x01+CPM_IRQ_OFFSET)
#define	SIU_INT_SPI		((uint)0x02+CPM_IRQ_OFFSET)
#define	SIU_INT_RISC		((uint)0x03+CPM_IRQ_OFFSET)
#define	SIU_INT_SMC1		((uint)0x04+CPM_IRQ_OFFSET)
#define	SIU_INT_SMC2		((uint)0x05+CPM_IRQ_OFFSET)
#define	SIU_INT_USB		((uint)0x0b+CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER1		((uint)0x0c+CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER2		((uint)0x0d+CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER3		((uint)0x0e+CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER4		((uint)0x0f+CPM_IRQ_OFFSET)
#define	SIU_INT_FCC1		((uint)0x20+CPM_IRQ_OFFSET)
#define	SIU_INT_FCC2		((uint)0x21+CPM_IRQ_OFFSET)
#define	SIU_INT_FCC3		((uint)0x22+CPM_IRQ_OFFSET)
#define	SIU_INT_MCC1		((uint)0x24+CPM_IRQ_OFFSET)
#define	SIU_INT_MCC2		((uint)0x25+CPM_IRQ_OFFSET)
#define	SIU_INT_SCC1		((uint)0x28+CPM_IRQ_OFFSET)
#define	SIU_INT_SCC2		((uint)0x29+CPM_IRQ_OFFSET)
#define	SIU_INT_SCC3		((uint)0x2a+CPM_IRQ_OFFSET)
#define	SIU_INT_SCC4		((uint)0x2b+CPM_IRQ_OFFSET)
#define	SIU_INT_PC15		((uint)0x30+CPM_IRQ_OFFSET)
#define	SIU_INT_PC14		((uint)0x31+CPM_IRQ_OFFSET)
#define	SIU_INT_PC13		((uint)0x32+CPM_IRQ_OFFSET)
#define	SIU_INT_PC12		((uint)0x33+CPM_IRQ_OFFSET)
#define	SIU_INT_PC11		((uint)0x34+CPM_IRQ_OFFSET)
#define	SIU_INT_PC10		((uint)0x35+CPM_IRQ_OFFSET)
#define	SIU_INT_PC9		((uint)0x36+CPM_IRQ_OFFSET)
#define	SIU_INT_PC8		((uint)0x37+CPM_IRQ_OFFSET)
#define	SIU_INT_PC7		((uint)0x38+CPM_IRQ_OFFSET)
#define	SIU_INT_PC6		((uint)0x39+CPM_IRQ_OFFSET)
#define	SIU_INT_PC5		((uint)0x3a+CPM_IRQ_OFFSET)
#define	SIU_INT_PC4		((uint)0x3b+CPM_IRQ_OFFSET)
#define	SIU_INT_PC3		((uint)0x3c+CPM_IRQ_OFFSET)
#define	SIU_INT_PC2		((uint)0x3d+CPM_IRQ_OFFSET)
#define	SIU_INT_PC1		((uint)0x3e+CPM_IRQ_OFFSET)
#define	SIU_INT_PC0		((uint)0x3f+CPM_IRQ_OFFSET)

static __inline__ int irq_canonicalize(int irq)
{
	return irq;
}

#else /* CONFIG_40x + CONFIG_8xx */
/*
 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
 * so it is the max of them all
 */
#define NR_IRQS			256

#ifndef CONFIG_8260

#define NUM_8259_INTERRUPTS	16

#else /* CONFIG_8260 */

/* The 8260 has an internal interrupt controller with a maximum of
 * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
 * Don't be confused by the 8260 documentation where they list an
 * "interrupt number" and "interrupt vector".  We are only interested
 * in the interrupt vector.  There are "reserved" holes where the
 * vector number increases, but the interrupt number in the table does not.
 * (Document errata updates have fixed this...make sure you have up to
 * date processor documentation -- Dan).
 */

#ifndef CPM_IRQ_OFFSET
#define CPM_IRQ_OFFSET	0
#endif

#define NR_CPM_INTS	64

#define	SIU_INT_ERROR		((uint)0x00 + CPM_IRQ_OFFSET)
#define	SIU_INT_I2C		((uint)0x01 + CPM_IRQ_OFFSET)
#define	SIU_INT_SPI		((uint)0x02 + CPM_IRQ_OFFSET)
#define	SIU_INT_RISC		((uint)0x03 + CPM_IRQ_OFFSET)
#define	SIU_INT_SMC1		((uint)0x04 + CPM_IRQ_OFFSET)
#define	SIU_INT_SMC2		((uint)0x05 + CPM_IRQ_OFFSET)
#define	SIU_INT_IDMA1		((uint)0x06 + CPM_IRQ_OFFSET)
#define	SIU_INT_IDMA2		((uint)0x07 + CPM_IRQ_OFFSET)
#define	SIU_INT_IDMA3		((uint)0x08 + CPM_IRQ_OFFSET)
#define	SIU_INT_IDMA4		((uint)0x09 + CPM_IRQ_OFFSET)
#define	SIU_INT_SDMA		((uint)0x0a + CPM_IRQ_OFFSET)
#define	SIU_INT_USB		((uint)0x0b + CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER1		((uint)0x0c + CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER2		((uint)0x0d + CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER3		((uint)0x0e + CPM_IRQ_OFFSET)
#define	SIU_INT_TIMER4		((uint)0x0f + CPM_IRQ_OFFSET)
#define	SIU_INT_TMCNT		((uint)0x10 + CPM_IRQ_OFFSET)
#define	SIU_INT_PIT		((uint)0x11 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ1		((uint)0x13 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ2		((uint)0x14 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ3		((uint)0x15 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ4		((uint)0x16 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ5		((uint)0x17 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ6		((uint)0x18 + CPM_IRQ_OFFSET)
#define	SIU_INT_IRQ7		((uint)0x19 + CPM_IRQ_OFFSET)
#define	SIU_INT_FCC1		((uint)0x20 + CPM_IRQ_OFFSET)
#define	SIU_INT_FCC2		((uint)0x21 + CPM_IRQ_OFFSET)
#define	SIU_INT_FCC3		((uint)0x22 + CPM_IRQ_OFFSET)
#define	SIU_INT_MCC1		((uint)0x24 + CPM_IRQ_OFFSET)
#define	SIU_INT_MCC2		((uint)0x25 + CPM_IRQ_OFFSET)
#define	SIU_INT_SCC1		((uint)0x28 + CPM_IRQ_OFFSET)
#define	SIU_INT_SCC2		((uint)0x29 + CPM_IRQ_OFFSET)
#define	SIU_INT_SCC3		((uint)0x2a + CPM_IRQ_OFFSET)
#define	SIU_INT_SCC4		((uint)0x2b + CPM_IRQ_OFFSET)
#define	SIU_INT_PC15		((uint)0x30 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC14		((uint)0x31 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC13		((uint)0x32 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC12		((uint)0x33 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC11		((uint)0x34 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC10		((uint)0x35 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC9		((uint)0x36 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC8		((uint)0x37 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC7		((uint)0x38 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC6		((uint)0x39 + CPM_IRQ_OFFSET)
#define	SIU_INT_PC5		((uint)0x3a + CPM_IRQ_OFFSET)
#define	SIU_INT_PC4		((uint)0x3b + CPM_IRQ_OFFSET)
#define	SIU_INT_PC3		((uint)0x3c + CPM_IRQ_OFFSET)
#define	SIU_INT_PC2		((uint)0x3d + CPM_IRQ_OFFSET)
#define	SIU_INT_PC1		((uint)0x3e + CPM_IRQ_OFFSET)
#define	SIU_INT_PC0		((uint)0x3f + CPM_IRQ_OFFSET)

#endif /* CONFIG_8260 */

/*
 * This gets called from serial.c, which is now used on
 * powermacs as well as prep/chrp boxes.
 * Prep and chrp both have cascaded 8259 PICs.
 */
static __inline__ int irq_canonicalize(int irq)
{
	if (ppc_md.irq_canonicalize)
		return ppc_md.irq_canonicalize(irq);
	return irq;
}

#endif

#define NR_MASK_WORDS	((NR_IRQS + 31) / 32)
/* pedantic: these are long because they are used with set_bit --RR */
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
extern atomic_t ppc_n_lost_interrupts;

#endif /* _ASM_IRQ_H */
#endif /* __KERNEL__ */
Commit	Line	Data
1da177e4 LT	1	#ifdef __KERNEL__
	2	#ifndef _ASM_IRQ_H
	3	#define _ASM_IRQ_H
	4
	5	#include <linux/config.h>
	6	#include <asm/machdep.h> /* ppc_md */
	7	#include <asm/atomic.h>
	8
	9	/*
	10	* These constants are used for passing information about interrupt
	11	* signal polarity and level/edge sensing to the low-level PIC chip
	12	* drivers.
	13	*/
	14	#define IRQ_SENSE_MASK 0x1
	15	#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
	16	#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
	17
	18	#define IRQ_POLARITY_MASK 0x2
	19	#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
	20	#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
	21
f26fdd59 KW	22	/*
	23	* IRQ line status macro IRQ_PER_CPU is used
	24	*/
	25	#define ARCH_HAS_IRQ_PER_CPU
	26
b671ad2b KG	27	#define get_irq_desc(irq) (&irq_desc[(irq)])
	28
	29	/* Define a way to iterate across irqs. */
	30	#define for_each_irq(i) \
	31	for ((i) = 0; (i) < NR_IRQS; ++(i))
	32
1da177e4 LT	33	#if defined(CONFIG_40x)
	34	#include <asm/ibm4xx.h>
	35
	36	#ifndef NR_BOARD_IRQS
	37	#define NR_BOARD_IRQS 0
	38	#endif
	39
	40	#ifndef UIC_WIDTH /* Number of interrupts per device */
	41	#define UIC_WIDTH 32
	42	#endif
	43
	44	#ifndef NR_UICS /* number of UIC devices */
	45	#define NR_UICS 1
	46	#endif
	47
	48	#if defined (CONFIG_403)
	49	/*
	50	* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
	51	* 32 possible interrupts, a majority of which are not implemented on
	52	* all cores. There are six configurable, external interrupt pins and
	53	* there are eight internal interrupts for the on-chip serial port
	54	* (SPU), DMA controller, and JTAG controller.
	55	*
	56	*/
	57
	58	#define NR_AIC_IRQS 32
	59	#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
	60
	61	#elif !defined (CONFIG_403)
	62
	63	/*
	64	* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
	65	* possible interrupts as well. There are seven, configurable external
	66	* interrupt pins and there are 17 internal interrupts for the on-chip
	67	* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
	68	*
	69	*/
	70
	71
	72	#define NR_UIC_IRQS UIC_WIDTH
	73	#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
	74	#endif
	75	static __inline__ int
	76	irq_canonicalize(int irq)
	77	{
	78	return (irq);
	79	}
	80
	81	#elif defined(CONFIG_44x)
	82	#include <asm/ibm44x.h>
	83
	84	#define NR_UIC_IRQS 32
	85	#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
	86
	87	static __inline__ int
	88	irq_canonicalize(int irq)
	89	{
	90	return (irq);
	91	}
	92
	93	#elif defined(CONFIG_8xx)
	94
	95	/* Now include the board configuration specific associations.
	96	*/
97	#include <asm/mpc8xx.h>
98
99	/* The MPC8xx cores have 16 possible interrupts. There are eight
100	* possible level sensitive interrupts assigned and generated internally
101	* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
102	* There are eight external interrupts (IRQs) that can be configured
103	* as either level or edge sensitive.
104	*
105	* On some implementations, there is also the possibility of an 8259
106	* through the PCI and PCI-ISA bridges.
107	*
108	* We are "flattening" the interrupt vectors of the cascaded CPM
109	* and 8259 interrupt controllers so that we can uniquely identify
110	* any interrupt source with a single integer.
111	*/
112	#define NR_SIU_INTS 16
113	#define NR_CPM_INTS 32
114	#ifndef NR_8259_INTS
115	#define NR_8259_INTS 0
116	#endif
117
118	#define SIU_IRQ_OFFSET 0
119	#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
120	#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
121
122	#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
123
124	/* These values must be zero-based and map 1:1 with the SIU configuration.
125	* They are used throughout the 8xx I/O subsystem to generate
126	* interrupt masks, flags, and other control patterns. This is why the
127	* current kernel assumption of the 8259 as the base controller is such
128	* a pain in the butt.
129	*/
130	#define SIU_IRQ0 (0) /* Highest priority */
131	#define SIU_LEVEL0 (1)
132	#define SIU_IRQ1 (2)
133	#define SIU_LEVEL1 (3)
134	#define SIU_IRQ2 (4)
135	#define SIU_LEVEL2 (5)
136	#define SIU_IRQ3 (6)
137	#define SIU_LEVEL3 (7)
138	#define SIU_IRQ4 (8)
139	#define SIU_LEVEL4 (9)
140	#define SIU_IRQ5 (10)
141	#define SIU_LEVEL5 (11)
142	#define SIU_IRQ6 (12)
143	#define SIU_LEVEL6 (13)
144	#define SIU_IRQ7 (14)
145	#define SIU_LEVEL7 (15)
146
514ccd4e VB	147	#define MPC8xx_INT_FEC1 SIU_LEVEL1
	148	#define MPC8xx_INT_FEC2 SIU_LEVEL3
	149
	150	#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
	151	#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
	152	#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
	153	#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
	154	#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
	155	#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
	156
1da177e4 LT	157	/* The internal interrupts we can configure as we see fit.
	158	* My personal preference is CPM at level 2, which puts it above the
	159	* MBX PCI/ISA/IDE interrupts.
	160	*/
	161	#ifndef PIT_INTERRUPT
	162	#define PIT_INTERRUPT SIU_LEVEL0
	163	#endif
	164	#ifndef CPM_INTERRUPT
	165	#define CPM_INTERRUPT SIU_LEVEL2
	166	#endif
	167	#ifndef PCMCIA_INTERRUPT
	168	#define PCMCIA_INTERRUPT SIU_LEVEL6
	169	#endif
	170	#ifndef DEC_INTERRUPT
	171	#define DEC_INTERRUPT SIU_LEVEL7
	172	#endif
	173
	174	/* Some internal interrupt registers use an 8-bit mask for the interrupt
	175	* level instead of a number.
	176	*/
	177	#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
	178
	179	/* always the same on 8xx -- Cort */
	180	static __inline__ int irq_canonicalize(int irq)
	181	{
	182	return irq;
	183	}
	184
	185	#elif defined(CONFIG_83xx)
	186	#include <asm/mpc83xx.h>
	187
	188	static __inline__ int irq_canonicalize(int irq)
	189	{
	190	return irq;
	191	}
	192
	193	#define NR_IRQS (NR_IPIC_INTS)
	194
	195	#elif defined(CONFIG_85xx)
	196	/* Now include the board configuration specific associations.
	197	*/
	198	#include <asm/mpc85xx.h>
	199
65145e06	200	/* The MPC8548 openpic has 48 internal interrupts and 12 external
1da177e4 LT	201	* interrupts.
	202	*
	203	* We are "flattening" the interrupt vectors of the cascaded CPM
	204	* so that we can uniquely identify any interrupt source with a
	205	* single integer.
	206	*/
	207	#define NR_CPM_INTS 64
65145e06	208	#define NR_EPIC_INTS 60
1da177e4 LT	209	#ifndef NR_8259_INTS
	210	#define NR_8259_INTS 0
	211	#endif
	212	#define NUM_8259_INTERRUPTS NR_8259_INTS
	213
	214	#ifndef CPM_IRQ_OFFSET
	215	#define CPM_IRQ_OFFSET 0
	216	#endif
	217
	218	#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
	219
	220	/* Internal IRQs on MPC85xx OpenPIC */
	221
	222	#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
	223	#ifdef CONFIG_CPM2
	224	#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
	225	#else
	226	#define MPC85xx_OPENPIC_IRQ_OFFSET 0
	227	#endif
	228	#endif
	229
	230	/* Not all of these exist on all MPC85xx implementations */
	231	#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
	232	#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
	233	#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
	234	#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
	235	#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
	236	#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
	237	#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
	238	#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
	239	#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
	240	#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
	241	#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
	242	#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
	243	#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
	244	#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
	245	#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
	246	#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
5b37b700 KG	247	#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
	248	#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
	249	#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4 LT	250	#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
	251	#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
	252	#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
5b37b700 KG	253	#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
	254	#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
	255	#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4 LT	256	#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
	257	#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
	258	#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
	259	#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
	260	#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
	261	#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
	262	#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
	263
	264	/* The 12 external interrupt lines */
65145e06 KG	265	#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
	266	#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
	267	#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
	268	#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
	269	#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
	270	#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
	271	#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
	272	#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
	273	#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
	274	#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
	275	#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
	276	#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
1da177e4 LT	277
	278	/* CPM related interrupts */
	279	#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
	280	#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
	281	#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
	282	#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
	283	#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
	284	#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
	285	#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
	286	#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
	287	#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
	288	#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
	289	#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
	290	#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
	291	#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
	292	#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
	293	#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
	294	#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
	295	#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
	296	#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
	297	#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
	298	#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
	299	#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
	300	#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
	301	#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
	302	#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
	303	#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
	304	#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
	305	#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
	306	#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
	307	#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
	308	#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
	309	#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
	310	#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
	311	#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
	312	#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
	313	#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
	314	#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
	315
	316	static __inline__ int irq_canonicalize(int irq)
	317	{
	318	return irq;
	319	}
	320
	321	#else /* CONFIG_40x + CONFIG_8xx */
	322	/*
	323	* this is the # irq's for all ppc arch's (pmac/chrp/prep)
	324	* so it is the max of them all
	325	*/
	326	#define NR_IRQS 256
	327
	328	#ifndef CONFIG_8260
	329
	330	#define NUM_8259_INTERRUPTS 16
	331
	332	#else /* CONFIG_8260 */
	333
	334	/* The 8260 has an internal interrupt controller with a maximum of
	335	* 64 IRQs. We will use NR_IRQs from above since it is large enough.
	336	* Don't be confused by the 8260 documentation where they list an
	337	* "interrupt number" and "interrupt vector". We are only interested
	338	* in the interrupt vector. There are "reserved" holes where the
	339	* vector number increases, but the interrupt number in the table does not.
	340	* (Document errata updates have fixed this...make sure you have up to
341	* date processor documentation -- Dan).
342	*/
343
344	#ifndef CPM_IRQ_OFFSET
345	#define CPM_IRQ_OFFSET 0
346	#endif
347
348	#define NR_CPM_INTS 64
349
350	#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
351	#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
352	#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
353	#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
354	#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
355	#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
356	#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
357	#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
358	#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
359	#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
360	#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
8e8fff09	361	#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
1da177e4 LT	362	#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
	363	#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
	364	#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
	365	#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
	366	#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
	367	#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
	368	#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
	369	#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
	370	#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
	371	#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
	372	#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
	373	#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
	374	#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
	375	#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
	376	#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
	377	#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
	378	#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
	379	#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
	380	#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
	381	#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
	382	#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
	383	#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
	384	#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
	385	#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
	386	#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
	387	#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
	388	#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
	389	#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
	390	#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
	391	#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
	392	#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
	393	#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
	394	#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
	395	#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
	396	#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
	397	#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
	398	#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
	399	#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
	400
	401	#endif /* CONFIG_8260 */
	402
	403	/*
	404	* This gets called from serial.c, which is now used on
	405	* powermacs as well as prep/chrp boxes.
	406	* Prep and chrp both have cascaded 8259 PICs.
	407	*/
	408	static __inline__ int irq_canonicalize(int irq)
	409	{
	410	if (ppc_md.irq_canonicalize)
	411	return ppc_md.irq_canonicalize(irq);
	412	return irq;
	413	}
	414
	415	#endif
	416
	417	#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
	418	/* pedantic: these are long because they are used with set_bit --RR */
	419	extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
	420	extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
	421	extern atomic_t ppc_n_lost_interrupts;
	422
1da177e4 LT	423	#endif /* _ASM_IRQ_H */
1da177e4 LT	424	#endif /* __KERNEL__ */