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1da177e4 LT |
1 | /* |
2 | * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling | |
3 | * | |
4 | * Copyright (C) 1997 Geert Uytterhoeven | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | */ | |
11 | ||
12 | #ifndef _PPC_KERNEL_OPEN_PIC_H | |
13 | #define _PPC_KERNEL_OPEN_PIC_H | |
14 | ||
1da177e4 LT |
15 | #include <linux/irq.h> |
16 | ||
17 | #define OPENPIC_SIZE 0x40000 | |
18 | ||
19 | /* | |
20 | * Non-offset'ed vector numbers | |
21 | */ | |
22 | ||
23 | #define OPENPIC_VEC_TIMER 110 /* and up */ | |
24 | #define OPENPIC_VEC_IPI 118 /* and up */ | |
25 | #define OPENPIC_VEC_SPURIOUS 255 | |
26 | ||
e4ee69c8 BH |
27 | /* Priorities */ |
28 | #define OPENPIC_PRIORITY_IPI_BASE 10 | |
29 | #define OPENPIC_PRIORITY_DEFAULT 4 | |
30 | #define OPENPIC_PRIORITY_NMI 9 | |
31 | ||
1da177e4 LT |
32 | /* OpenPIC IRQ controller structure */ |
33 | extern struct hw_interrupt_type open_pic; | |
34 | ||
35 | /* OpenPIC IPI controller structure */ | |
36 | #ifdef CONFIG_SMP | |
37 | extern struct hw_interrupt_type open_pic_ipi; | |
38 | #endif /* CONFIG_SMP */ | |
39 | ||
40 | extern u_int OpenPIC_NumInitSenses; | |
41 | extern u_char *OpenPIC_InitSenses; | |
42 | extern void __iomem * OpenPIC_Addr; | |
43 | extern int epic_serial_mode; | |
44 | ||
45 | /* Exported functions */ | |
46 | extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr); | |
47 | extern void openpic_init(int linux_irq_offset); | |
48 | extern void openpic_init_nmi_irq(u_int irq); | |
e4ee69c8 | 49 | extern void openpic_set_irq_priority(u_int irq, u_int pri); |
1da177e4 | 50 | extern void openpic_hookup_cascade(u_int irq, char *name, |
40a5f7ca | 51 | int (*cascade_fn)(void)); |
1da177e4 LT |
52 | extern u_int openpic_irq(void); |
53 | extern void openpic_eoi(void); | |
54 | extern void openpic_request_IPIs(void); | |
55 | extern void do_openpic_setup_cpu(void); | |
40a5f7ca | 56 | extern int openpic_get_irq(void); |
1da177e4 LT |
57 | extern void openpic_reset_processor_phys(u_int cpumask); |
58 | extern void openpic_setup_ISU(int isu_num, unsigned long addr); | |
59 | extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); | |
17a6392d | 60 | extern void smp_openpic_message_pass(int target, int msg); |
1da177e4 LT |
61 | extern void openpic_set_k2_cascade(int irq); |
62 | extern void openpic_set_priority(u_int pri); | |
7a648b9e | 63 | extern u_int openpic_get_priority(void); |
1da177e4 LT |
64 | |
65 | extern inline int openpic_to_irq(int irq) | |
66 | { | |
67 | /* IRQ 0 usually means 'disabled'.. don't mess with it | |
68 | * exceptions to this (sandpoint maybe?) | |
69 | * shouldn't use openpic_to_irq | |
70 | */ | |
71 | if (irq != 0){ | |
72 | return irq += NUM_8259_INTERRUPTS; | |
73 | } else { | |
74 | return 0; | |
75 | } | |
76 | } | |
77 | /* Support for second openpic on G5 macs */ | |
78 | ||
79 | // FIXME: To be replaced by sane cascaded controller management */ | |
80 | ||
81 | #define PMAC_OPENPIC2_OFFSET 128 | |
82 | ||
83 | #define OPENPIC2_VEC_TIMER 110 /* and up */ | |
84 | #define OPENPIC2_VEC_IPI 118 /* and up */ | |
85 | #define OPENPIC2_VEC_SPURIOUS 127 | |
86 | ||
87 | ||
88 | extern void* OpenPIC2_Addr; | |
89 | ||
90 | /* Exported functions */ | |
91 | extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr); | |
92 | extern void openpic2_init(int linux_irq_offset); | |
93 | extern void openpic2_init_nmi_irq(u_int irq); | |
94 | extern u_int openpic2_irq(void); | |
95 | extern void openpic2_eoi(void); | |
40a5f7ca | 96 | extern int openpic2_get_irq(void); |
1da177e4 LT |
97 | extern void openpic2_setup_ISU(int isu_num, unsigned long addr); |
98 | #endif /* _PPC_KERNEL_OPEN_PIC_H */ |