[deliverable/linux.git] / include / asm-ppc / ppc_asm.h

/*
 * include/asm-ppc/ppc_asm.h
 *
 * Definitions used by various bits of low-level assembly code on PowerPC.
 *
 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/config.h>

/*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)

#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
				SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \
				REST_10GPRS(22, base)

#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*(n)(base)
#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)
#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*(n)(base)
#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)
#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)
#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)
#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)
#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)

#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,b,base
#define SAVE_2VR(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
#define SAVE_4VR(n,b,base)	SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
#define SAVE_8VR(n,b,base)	SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
#define SAVE_16VR(n,b,base)	SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
#define SAVE_32VR(n,b,base)	SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,b,base
#define REST_2VR(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)
#define REST_4VR(n,b,base)	REST_2VR(n,b,base); REST_2VR(n+2,b,base)
#define REST_8VR(n,b,base)	REST_4VR(n,b,base); REST_4VR(n+4,b,base)
#define REST_16VR(n,b,base)	REST_8VR(n,b,base); REST_8VR(n+8,b,base)
#define REST_32VR(n,b,base)	REST_16VR(n,b,base); REST_16VR(n+16,b,base)

#define SAVE_EVR(n,s,base)	evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
#define SAVE_2EVR(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
#define SAVE_4EVR(n,s,base)	SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
#define SAVE_8EVR(n,s,base)	SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
#define SAVE_16EVR(n,s,base)	SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
#define SAVE_32EVR(n,s,base)	SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)

#define REST_EVR(n,s,base)	lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
#define REST_2EVR(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)
#define REST_4EVR(n,s,base)	REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
#define REST_8EVR(n,s,base)	REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
#define REST_16EVR(n,s,base)	REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
#define REST_32EVR(n,s,base)	REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)

#ifdef CONFIG_PPC601_SYNC_FIX
#define SYNC				\
BEGIN_FTR_SECTION			\
	sync;				\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define SYNC_601			\
BEGIN_FTR_SECTION			\
	sync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601			\
BEGIN_FTR_SECTION			\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#else
#define	SYNC
#define SYNC_601
#define ISYNC_601
#endif

#ifndef CONFIG_SMP
#define TLBSYNC
#else /* CONFIG_SMP */
/* tlbsync is not implemented on 601 */
#define TLBSYNC				\
BEGIN_FTR_SECTION			\
	tlbsync;			\
	sync;				\
END_FTR_SECTION_IFCLR(CPU_FTR_601)
#endif

/*
 * This instruction is not implemented on the PPC 603 or 601; however, on
 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 * All of these instructions exist in the 8xx, they have magical powers,
 * and they must be used.
 */

#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
#define tlbia					\
	li	r4,1024;			\
	mtctr	r4;				\
	lis	r4,KERNELBASE@h;		\
0:	tlbie	r4;				\
	addi	r4,r4,0x1000;			\
	bdnz	0b
#endif

#ifdef CONFIG_BOOKE
#define tophys(rd,rs)				\
	addis	rd,rs,0

#define tovirt(rd,rs)				\
	addis	rd,rs,0

#else  /* CONFIG_BOOKE */
/*
 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 * physical base address of RAM at compile time.
 */
#define tophys(rd,rs)				\
0:	addis	rd,rs,-KERNELBASE@h;		\
	.section ".vtop_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous

#define tovirt(rd,rs)				\
0:	addis	rd,rs,KERNELBASE@h;		\
	.section ".ptov_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous
#endif  /* CONFIG_BOOKE */

/*
 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
 * we then have to make sure we preserve the top 32 bits except for
 * the 64-bit mode bit, which we clear.
 */
#ifdef CONFIG_PPC64BRIDGE
#define	FIX_SRR1(ra, rb)	\
	mr	rb,ra;		\
	mfmsr	ra;		\
	clrldi	ra,ra,1;		/* turn off 64-bit mode */ \
	rldimi	ra,rb,0,32
#define	RFI		.long	0x4c000024	/* rfid instruction */
#define MTMSRD(r)	.long	(0x7c000164 + ((r) << 21))	/* mtmsrd */
#define CLR_TOP32(r)	rlwinm	(r),(r),0,0,31	/* clear top 32 bits */

#else
#define FIX_SRR1(ra, rb)
#ifndef CONFIG_40x
#define	RFI		rfi
#else
#define RFI		rfi; b .	/* Prevent prefetch past rfi */
#endif
#define MTMSRD(r)	mtmsr	r
#define CLR_TOP32(r)
#endif /* CONFIG_PPC64BRIDGE */

#define RFCI		.long 0x4c000066	/* rfci instruction */
#define RFDI		.long 0x4c00004e	/* rfdi instruction */
#define RFMCI		.long 0x4c00004c	/* rfmci instruction */

#ifdef CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb)	dcbt	ra, rb;
#define	PPC405_ERR77_SYNC	sync;
#else
#define PPC405_ERR77(ra,rb)
#define PPC405_ERR77_SYNC
#endif

#ifdef CONFIG_IBM440EP_ERR42
#define PPC440EP_ERR42 isync
#else
#define PPC440EP_ERR42
#endif

/* The boring bits... */

/* Condition Register Bit Fields */

#define	cr0	0
#define	cr1	1
#define	cr2	2
#define	cr3	3
#define	cr4	4
#define	cr5	5
#define	cr6	6
#define	cr7	7


/* General Purpose Registers (GPRs) */

#define	r0	0
#define	r1	1
#define	r2	2
#define	r3	3
#define	r4	4
#define	r5	5
#define	r6	6
#define	r7	7
#define	r8	8
#define	r9	9
#define	r10	10
#define	r11	11
#define	r12	12
#define	r13	13
#define	r14	14
#define	r15	15
#define	r16	16
#define	r17	17
#define	r18	18
#define	r19	19
#define	r20	20
#define	r21	21
#define	r22	22
#define	r23	23
#define	r24	24
#define	r25	25
#define	r26	26
#define	r27	27
#define	r28	28
#define	r29	29
#define	r30	30
#define	r31	31


/* Floating Point Registers (FPRs) */

#define	fr0	0
#define	fr1	1
#define	fr2	2
#define	fr3	3
#define	fr4	4
#define	fr5	5
#define	fr6	6
#define	fr7	7
#define	fr8	8
#define	fr9	9
#define	fr10	10
#define	fr11	11
#define	fr12	12
#define	fr13	13
#define	fr14	14
#define	fr15	15
#define	fr16	16
#define	fr17	17
#define	fr18	18
#define	fr19	19
#define	fr20	20
#define	fr21	21
#define	fr22	22
#define	fr23	23
#define	fr24	24
#define	fr25	25
#define	fr26	26
#define	fr27	27
#define	fr28	28
#define	fr29	29
#define	fr30	30
#define	fr31	31

#define	vr0	0
#define	vr1	1
#define	vr2	2
#define	vr3	3
#define	vr4	4
#define	vr5	5
#define	vr6	6
#define	vr7	7
#define	vr8	8
#define	vr9	9
#define	vr10	10
#define	vr11	11
#define	vr12	12
#define	vr13	13
#define	vr14	14
#define	vr15	15
#define	vr16	16
#define	vr17	17
#define	vr18	18
#define	vr19	19
#define	vr20	20
#define	vr21	21
#define	vr22	22
#define	vr23	23
#define	vr24	24
#define	vr25	25
#define	vr26	26
#define	vr27	27
#define	vr28	28
#define	vr29	29
#define	vr30	30
#define	vr31	31

#define	evr0	0
#define	evr1	1
#define	evr2	2
#define	evr3	3
#define	evr4	4
#define	evr5	5
#define	evr6	6
#define	evr7	7
#define	evr8	8
#define	evr9	9
#define	evr10	10
#define	evr11	11
#define	evr12	12
#define	evr13	13
#define	evr14	14
#define	evr15	15
#define	evr16	16
#define	evr17	17
#define	evr18	18
#define	evr19	19
#define	evr20	20
#define	evr21	21
#define	evr22	22
#define	evr23	23
#define	evr24	24
#define	evr25	25
#define	evr26	26
#define	evr27	27
#define	evr28	28
#define	evr29	29
#define	evr30	30
#define	evr31	31

/* some stab codes */
#define N_FUN	36
#define N_RSYM	64
#define N_SLINE	68
#define N_SO	100
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-ppc/ppc_asm.h
	3	*
	4	* Definitions used by various bits of low-level assembly code on PowerPC.
	5	*
	6	* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#include <linux/config.h>
	15
	16	/*
	17	* Macros for storing registers into and loading registers from
	18	* exception frames.
	19	*/
	20	#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
	21	#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
	22	#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
	23	#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
	24	#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
	25	#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
	26	#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
	27	#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
	28	#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
	29	#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
	30
	31	#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
	32	SAVE_10GPRS(22, base)
	33	#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
	34	REST_10GPRS(22, base)
	35
	36	#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
	37	#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
	38	#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
	39	#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
	40	#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
	41	#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
	42	#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
	43	#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
	44	#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
	45	#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
	46	#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
	47	#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
	48
	49	#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
	50	#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
	51	#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
	52	#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
	53	#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
	54	#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
	55	#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
	56	#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
	57	#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
	58	#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
	59	#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
	60	#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
	61
	62	#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
	63	#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
	64	#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
65	#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
66	#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
67	#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
68
69	#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
70	#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
71	#define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
72	#define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
73	#define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
74	#define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
75
76	#ifdef CONFIG_PPC601_SYNC_FIX
77	#define SYNC \
78	BEGIN_FTR_SECTION \
79	sync; \
80	isync; \
81	END_FTR_SECTION_IFSET(CPU_FTR_601)
82	#define SYNC_601 \
83	BEGIN_FTR_SECTION \
84	sync; \
85	END_FTR_SECTION_IFSET(CPU_FTR_601)
86	#define ISYNC_601 \
87	BEGIN_FTR_SECTION \
88	isync; \
89	END_FTR_SECTION_IFSET(CPU_FTR_601)
90	#else
91	#define SYNC
92	#define SYNC_601
93	#define ISYNC_601
94	#endif
95
96	#ifndef CONFIG_SMP
97	#define TLBSYNC
98	#else /* CONFIG_SMP */
99	/* tlbsync is not implemented on 601 */
100	#define TLBSYNC \
101	BEGIN_FTR_SECTION \
102	tlbsync; \
103	sync; \
104	END_FTR_SECTION_IFCLR(CPU_FTR_601)
105	#endif
106
107	/*
108	* This instruction is not implemented on the PPC 603 or 601; however, on
109	* the 403GCX and 405GP tlbia IS defined and tlbie is not.
110	* All of these instructions exist in the 8xx, they have magical powers,
111	* and they must be used.
112	*/
113
114	#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
115	#define tlbia \
116	li r4,1024; \
117	mtctr r4; \
118	lis r4,KERNELBASE@h; \
119	0: tlbie r4; \
120	addi r4,r4,0x1000; \
121	bdnz 0b
122	#endif
123
124	#ifdef CONFIG_BOOKE
125	#define tophys(rd,rs) \
126	addis rd,rs,0
127
128	#define tovirt(rd,rs) \
129	addis rd,rs,0
130
131	#else /* CONFIG_BOOKE */
132	/*
133	* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
134	* physical base address of RAM at compile time.
135	*/
136	#define tophys(rd,rs) \
137	0: addis rd,rs,-KERNELBASE@h; \
138	.section ".vtop_fixup","aw"; \
139	.align 1; \
140	.long 0b; \
141	.previous
142
143	#define tovirt(rd,rs) \
144	0: addis rd,rs,KERNELBASE@h; \
145	.section ".ptov_fixup","aw"; \
146	.align 1; \
147	.long 0b; \
148	.previous
149	#endif /* CONFIG_BOOKE */
150
151	/*
152	* On 64-bit cpus, we use the rfid instruction instead of rfi, but
153	* we then have to make sure we preserve the top 32 bits except for
154	* the 64-bit mode bit, which we clear.
155	*/
156	#ifdef CONFIG_PPC64BRIDGE
157	#define FIX_SRR1(ra, rb) \
158	mr rb,ra; \
159	mfmsr ra; \
160	clrldi ra,ra,1; /* turn off 64-bit mode */ \
161	rldimi ra,rb,0,32
162	#define RFI .long 0x4c000024 /* rfid instruction */
163	#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
164	#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
165
166	#else
167	#define FIX_SRR1(ra, rb)
168	#ifndef CONFIG_40x
169	#define RFI rfi
170	#else
171	#define RFI rfi; b . /* Prevent prefetch past rfi */
172	#endif
173	#define MTMSRD(r) mtmsr r
174	#define CLR_TOP32(r)
175	#endif /* CONFIG_PPC64BRIDGE */
176
33d9e9b5 KG	177	#define RFCI .long 0x4c000066 /* rfci instruction */
33d9e9b5 KG	178	#define RFDI .long 0x4c00004e /* rfdi instruction */
1da177e4 LT	179	#define RFMCI .long 0x4c00004c /* rfmci instruction */
	180
	181	#ifdef CONFIG_IBM405_ERR77
	182	#define PPC405_ERR77(ra,rb) dcbt ra, rb;
	183	#define PPC405_ERR77_SYNC sync;
	184	#else
	185	#define PPC405_ERR77(ra,rb)
	186	#define PPC405_ERR77_SYNC
	187	#endif
	188
c9cf73ae MP	189	#ifdef CONFIG_IBM440EP_ERR42
	190	#define PPC440EP_ERR42 isync
	191	#else
	192	#define PPC440EP_ERR42
	193	#endif
	194
1da177e4 LT	195	/* The boring bits... */
	196
	197	/* Condition Register Bit Fields */
	198
	199	#define cr0 0
	200	#define cr1 1
	201	#define cr2 2
	202	#define cr3 3
	203	#define cr4 4
	204	#define cr5 5
	205	#define cr6 6
	206	#define cr7 7
	207
	208
	209	/* General Purpose Registers (GPRs) */
	210
	211	#define r0 0
	212	#define r1 1
	213	#define r2 2
	214	#define r3 3
	215	#define r4 4
	216	#define r5 5
	217	#define r6 6
	218	#define r7 7
	219	#define r8 8
	220	#define r9 9
	221	#define r10 10
	222	#define r11 11
	223	#define r12 12
	224	#define r13 13
	225	#define r14 14
	226	#define r15 15
	227	#define r16 16
	228	#define r17 17
	229	#define r18 18
	230	#define r19 19
	231	#define r20 20
	232	#define r21 21
	233	#define r22 22
	234	#define r23 23
	235	#define r24 24
	236	#define r25 25
	237	#define r26 26
	238	#define r27 27
	239	#define r28 28
	240	#define r29 29
	241	#define r30 30
	242	#define r31 31
	243
	244
	245	/* Floating Point Registers (FPRs) */
	246
	247	#define fr0 0
	248	#define fr1 1
	249	#define fr2 2
	250	#define fr3 3
	251	#define fr4 4
	252	#define fr5 5
	253	#define fr6 6
	254	#define fr7 7
	255	#define fr8 8
	256	#define fr9 9
	257	#define fr10 10
	258	#define fr11 11
259	#define fr12 12
260	#define fr13 13
261	#define fr14 14
262	#define fr15 15
263	#define fr16 16
264	#define fr17 17
265	#define fr18 18
266	#define fr19 19
267	#define fr20 20
268	#define fr21 21
269	#define fr22 22
270	#define fr23 23
271	#define fr24 24
272	#define fr25 25
273	#define fr26 26
274	#define fr27 27
275	#define fr28 28
276	#define fr29 29
277	#define fr30 30
278	#define fr31 31
279
280	#define vr0 0
281	#define vr1 1
282	#define vr2 2
283	#define vr3 3
284	#define vr4 4
285	#define vr5 5
286	#define vr6 6
287	#define vr7 7
288	#define vr8 8
289	#define vr9 9
290	#define vr10 10
291	#define vr11 11
292	#define vr12 12
293	#define vr13 13
294	#define vr14 14
295	#define vr15 15
296	#define vr16 16
297	#define vr17 17
298	#define vr18 18
299	#define vr19 19
300	#define vr20 20
301	#define vr21 21
302	#define vr22 22
303	#define vr23 23
304	#define vr24 24
305	#define vr25 25
306	#define vr26 26
307	#define vr27 27
308	#define vr28 28
309	#define vr29 29
310	#define vr30 30
311	#define vr31 31
312
313	#define evr0 0
314	#define evr1 1
315	#define evr2 2
316	#define evr3 3
317	#define evr4 4
318	#define evr5 5
319	#define evr6 6
320	#define evr7 7
321	#define evr8 8
322	#define evr9 9
323	#define evr10 10
324	#define evr11 11
325	#define evr12 12
326	#define evr13 13
327	#define evr14 14
328	#define evr15 15
329	#define evr16 16
330	#define evr17 17
331	#define evr18 18
332	#define evr19 19
333	#define evr20 20
334	#define evr21 21
335	#define evr22 22
336	#define evr23 23
337	#define evr24 24
338	#define evr25 25
339	#define evr26 26
340	#define evr27 27
341	#define evr28 28
342	#define evr29 29
343	#define evr30 30
344	#define evr31 31
345
346	/* some stab codes */
347	#define N_FUN 36
348	#define N_RSYM 64
349	#define N_SLINE 68
350	#define N_SO 100