[deliverable/linux.git] / include / asm-ppc64 / cputable.h

/*
 *  include/asm-ppc64/cputable.h
 *
 *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
 *
 *  Modifications for ppc64:
 *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
 * 
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#ifndef __ASM_PPC_CPUTABLE_H
#define __ASM_PPC_CPUTABLE_H

#include <linux/config.h>
#include <asm/page.h> /* for ASM_CONST */

/* Exposed to userland CPU features - Must match ppc32 definitions */
#define PPC_FEATURE_32			0x80000000
#define PPC_FEATURE_64			0x40000000
#define PPC_FEATURE_601_INSTR		0x20000000
#define PPC_FEATURE_HAS_ALTIVEC		0x10000000
#define PPC_FEATURE_HAS_FPU		0x08000000
#define PPC_FEATURE_HAS_MMU		0x04000000
#define PPC_FEATURE_HAS_4xxMAC		0x02000000
#define PPC_FEATURE_UNIFIED_CACHE	0x01000000

#ifdef __KERNEL__

#ifndef __ASSEMBLY__

/* This structure can grow, it's real size is used by head.S code
 * via the mkdefs mechanism.
 */
struct cpu_spec;

typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);

struct cpu_spec {
	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	unsigned int	pvr_mask;
	unsigned int	pvr_value;

	char		*cpu_name;
	unsigned long	cpu_features;		/* Kernel features */
	unsigned int	cpu_user_features;	/* Userland features */

	/* cache line sizes */
	unsigned int	icache_bsize;
	unsigned int	dcache_bsize;

	/* this is called to initialize various CPU bits like L1 cache,
	 * BHT, SPD, etc... from head.S before branching to identify_machine
	 */
	cpu_setup_t	cpu_setup;

	/* This is used to identify firmware features which are available
	 * to the kernel.
	 */
	unsigned long   firmware_features;
};

extern struct cpu_spec		cpu_specs[];
extern struct cpu_spec		*cur_cpu_spec;

static inline unsigned long cpu_has_feature(unsigned long feature)
{
	return cur_cpu_spec->cpu_features & feature;
}


/* firmware feature bitmask values */
#define FIRMWARE_MAX_FEATURES 63

#define FW_FEATURE_PFT		(1UL<<0)
#define FW_FEATURE_TCE		(1UL<<1)	
#define FW_FEATURE_SPRG0	(1UL<<2)	
#define FW_FEATURE_DABR		(1UL<<3)	
#define FW_FEATURE_COPY		(1UL<<4)	
#define FW_FEATURE_ASR		(1UL<<5)	
#define FW_FEATURE_DEBUG	(1UL<<6)	
#define FW_FEATURE_TERM		(1UL<<7)	
#define FW_FEATURE_PERF		(1UL<<8)	
#define FW_FEATURE_DUMP		(1UL<<9)	
#define FW_FEATURE_INTERRUPT	(1UL<<10)	
#define FW_FEATURE_MIGRATE	(1UL<<11)	
#define FW_FEATURE_PERFMON	(1UL<<12)	
#define FW_FEATURE_CRQ   	(1UL<<13)	
#define FW_FEATURE_VIO   	(1UL<<14)	
#define FW_FEATURE_RDMA   	(1UL<<15)	
#define FW_FEATURE_LLAN   	(1UL<<16)	
#define FW_FEATURE_BULK   	(1UL<<17)	
#define FW_FEATURE_XDABR   	(1UL<<18)	
#define FW_FEATURE_MULTITCE   	(1UL<<19)	
#define FW_FEATURE_SPLPAR   	(1UL<<20)	

typedef struct {
    unsigned long val;
    char * name;
} firmware_feature_t;

extern firmware_feature_t firmware_features_table[];

#endif /* __ASSEMBLY__ */

/* CPU kernel features */

/* Retain the 32b definitions for the time being - use bottom half of word */
#define CPU_FTR_SPLIT_ID_CACHE		ASM_CONST(0x0000000000000001)
#define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
#define CPU_FTR_TAU			ASM_CONST(0x0000000000000010)
#define CPU_FTR_CAN_DOZE		ASM_CONST(0x0000000000000020)
#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)
#define CPU_FTR_604_PERF_MON		ASM_CONST(0x0000000000000080)
#define CPU_FTR_601			ASM_CONST(0x0000000000000100)
#define CPU_FTR_HPTE_TABLE		ASM_CONST(0x0000000000000200)
#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)
#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)
#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)

/* Add the 64b processor unique features in the top half of the word */
#define CPU_FTR_SLB           		ASM_CONST(0x0000000100000000)
#define CPU_FTR_16M_PAGE      		ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL         		ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE     		ASM_CONST(0x0000000800000000)
#define CPU_FTR_NODSISRALIGN  		ASM_CONST(0x0000001000000000)
#define CPU_FTR_IABR  			ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA  			ASM_CONST(0x0000004000000000)
#define CPU_FTR_PMC8  			ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT  			ASM_CONST(0x0000010000000000)
#define CPU_FTR_COHERENT_ICACHE  	ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x0000040000000000)
#define CPU_FTR_MMCRA_SIHV		ASM_CONST(0x0000080000000000)

/* Platform firmware features */
#define FW_FTR_				ASM_CONST(0x0000000000000001)

#ifndef __ASSEMBLY__
#define COMMON_USER_PPC64	(PPC_FEATURE_32 | PPC_FEATURE_64 | \
			         PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)

#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
                                 CPU_FTR_NODSISRALIGN)

/* iSeries doesn't support large pages */
#ifdef CONFIG_PPC_ISERIES
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE)
#else
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
#endif

#define COMMON_PPC64_FW	(0)
#endif

#ifdef __ASSEMBLY__

#define BEGIN_FTR_SECTION		98:

#define END_FTR_SECTION(msk, val)		\
99:						\
	.section __ftr_fixup,"a";		\
	.align 3;				\
	.llong msk;			        \
	.llong val;			        \
	.llong 98b;			        \
	.llong 99b;	 		        \
	.previous

#else

#define BEGIN_FTR_SECTION		"98:\n"
#define END_FTR_SECTION(msk, val)		\
"99:\n"						\
"	.section __ftr_fixup,\"a\";\n"		\
"	.align 3;\n"				\
"	.llong "#msk";\n"			\
"	.llong "#val";\n"			\
"	.llong 98b;\n"			        \
"	.llong 99b;\n"	 		        \
"	.previous\n"

#endif /* __ASSEMBLY__ */

#define END_FTR_SECTION_IFSET(msk)	END_FTR_SECTION((msk), (msk))
#define END_FTR_SECTION_IFCLR(msk)	END_FTR_SECTION((msk), 0)

#endif /* __ASM_PPC_CPUTABLE_H */
#endif /* __KERNEL__ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-ppc64/cputable.h
	3	*
	4	* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
	5	*
	6	* Modifications for ppc64:
	7	* Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#ifndef __ASM_PPC_CPUTABLE_H
	16	#define __ASM_PPC_CPUTABLE_H
	17
	18	#include <linux/config.h>
	19	#include <asm/page.h> /* for ASM_CONST */
	20
	21	/* Exposed to userland CPU features - Must match ppc32 definitions */
	22	#define PPC_FEATURE_32 0x80000000
	23	#define PPC_FEATURE_64 0x40000000
	24	#define PPC_FEATURE_601_INSTR 0x20000000
	25	#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
	26	#define PPC_FEATURE_HAS_FPU 0x08000000
	27	#define PPC_FEATURE_HAS_MMU 0x04000000
	28	#define PPC_FEATURE_HAS_4xxMAC 0x02000000
	29	#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
	30
	31	#ifdef __KERNEL__
	32
	33	#ifndef __ASSEMBLY__
	34
	35	/* This structure can grow, it's real size is used by head.S code
	36	* via the mkdefs mechanism.
	37	*/
	38	struct cpu_spec;
	39
	40	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
	41
	42	struct cpu_spec {
	43	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	44	unsigned int pvr_mask;
	45	unsigned int pvr_value;
	46
	47	char *cpu_name;
	48	unsigned long cpu_features; /* Kernel features */
	49	unsigned int cpu_user_features; /* Userland features */
	50
	51	/* cache line sizes */
	52	unsigned int icache_bsize;
	53	unsigned int dcache_bsize;
	54
	55	/* this is called to initialize various CPU bits like L1 cache,
	56	* BHT, SPD, etc... from head.S before branching to identify_machine
	57	*/
	58	cpu_setup_t cpu_setup;
	59
	60	/* This is used to identify firmware features which are available
	61	* to the kernel.
	62	*/
	63	unsigned long firmware_features;
	64	};
65
66	extern struct cpu_spec cpu_specs[];
67	extern struct cpu_spec *cur_cpu_spec;
68
69	static inline unsigned long cpu_has_feature(unsigned long feature)
70	{
71	return cur_cpu_spec->cpu_features & feature;
72	}
73
74
75	/* firmware feature bitmask values */
76	#define FIRMWARE_MAX_FEATURES 63
77
78	#define FW_FEATURE_PFT (1UL<<0)
79	#define FW_FEATURE_TCE (1UL<<1)
80	#define FW_FEATURE_SPRG0 (1UL<<2)
81	#define FW_FEATURE_DABR (1UL<<3)
82	#define FW_FEATURE_COPY (1UL<<4)
83	#define FW_FEATURE_ASR (1UL<<5)
84	#define FW_FEATURE_DEBUG (1UL<<6)
85	#define FW_FEATURE_TERM (1UL<<7)
86	#define FW_FEATURE_PERF (1UL<<8)
87	#define FW_FEATURE_DUMP (1UL<<9)
88	#define FW_FEATURE_INTERRUPT (1UL<<10)
89	#define FW_FEATURE_MIGRATE (1UL<<11)
90	#define FW_FEATURE_PERFMON (1UL<<12)
91	#define FW_FEATURE_CRQ (1UL<<13)
92	#define FW_FEATURE_VIO (1UL<<14)
93	#define FW_FEATURE_RDMA (1UL<<15)
94	#define FW_FEATURE_LLAN (1UL<<16)
95	#define FW_FEATURE_BULK (1UL<<17)
96	#define FW_FEATURE_XDABR (1UL<<18)
97	#define FW_FEATURE_MULTITCE (1UL<<19)
98	#define FW_FEATURE_SPLPAR (1UL<<20)
99
100	typedef struct {
101	unsigned long val;
102	char * name;
103	} firmware_feature_t;
104
105	extern firmware_feature_t firmware_features_table[];
106
107	#endif /* __ASSEMBLY__ */
108
109	/* CPU kernel features */
110
111	/* Retain the 32b definitions for the time being - use bottom half of word */
112	#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
113	#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
114	#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
115	#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
116	#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
117	#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
118	#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
119	#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
120	#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
121	#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
122	#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
123	#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
124	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
125	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
126	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
127
128	/* Add the 64b processor unique features in the top half of the word */
129	#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
130	#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
131	#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
132	#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
133	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
134	#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
135	#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
136	#define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000)
137	#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
138	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
139	#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
140	#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
141
142	/* Platform firmware features */
143	#define FW_FTR_ ASM_CONST(0x0000000000000001)
144
145	#ifndef __ASSEMBLY__
146	#define COMMON_USER_PPC64 (PPC_FEATURE_32 \| PPC_FEATURE_64 \| \
147	PPC_FEATURE_HAS_FPU \| PPC_FEATURE_HAS_MMU)
148
149	#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB \| \
150	CPU_FTR_TLBIEL \| CPU_FTR_NOEXECUTE \| \
151	CPU_FTR_NODSISRALIGN)
152
153	/* iSeries doesn't support large pages */
154	#ifdef CONFIG_PPC_ISERIES
155	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
156	#else
157	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE \| CPU_FTR_16M_PAGE)
158	#endif
159
160	#define COMMON_PPC64_FW (0)
161	#endif
162
163	#ifdef __ASSEMBLY__
164
165	#define BEGIN_FTR_SECTION 98:
166
167	#define END_FTR_SECTION(msk, val) \
168	99: \
169	.section __ftr_fixup,"a"; \
170	.align 3; \
171	.llong msk; \
172	.llong val; \
173	.llong 98b; \
174	.llong 99b; \
175	.previous
176
177	#else
178
179	#define BEGIN_FTR_SECTION "98:\n"
180	#define END_FTR_SECTION(msk, val) \
181	"99:\n" \
182	" .section __ftr_fixup,\"a\";\n" \
183	" .align 3;\n" \
184	" .llong "#msk";\n" \
185	" .llong "#val";\n" \
186	" .llong 98b;\n" \
187	" .llong 99b;\n" \
188	" .previous\n"
189
190	#endif /* __ASSEMBLY__ */
191
192	#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
193	#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
194
195	#endif /* __ASM_PPC_CPUTABLE_H */
196	#endif /* __KERNEL__ */
197