Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | |
3 | * | |
4 | * Based on alpha version. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef OP_IMPL_H | |
13 | #define OP_IMPL_H 1 | |
14 | ||
15 | #define OP_MAX_COUNTER 8 | |
16 | ||
17 | /* Per-counter configuration as set via oprofilefs. */ | |
18 | struct op_counter_config { | |
19 | unsigned long valid; | |
20 | unsigned long enabled; | |
21 | unsigned long event; | |
22 | unsigned long count; | |
23 | unsigned long kernel; | |
24 | /* We dont support per counter user/kernel selection */ | |
25 | unsigned long user; | |
26 | unsigned long unit_mask; | |
27 | }; | |
28 | ||
29 | /* System-wide configuration as set via oprofilefs. */ | |
30 | struct op_system_config { | |
31 | unsigned long mmcr0; | |
32 | unsigned long mmcr1; | |
33 | unsigned long mmcra; | |
34 | unsigned long enable_kernel; | |
35 | unsigned long enable_user; | |
36 | unsigned long backtrace_spinlocks; | |
37 | }; | |
38 | ||
39 | /* Per-arch configuration */ | |
a3e48c10 | 40 | struct op_powerpc_model { |
1da177e4 LT |
41 | void (*reg_setup) (struct op_counter_config *, |
42 | struct op_system_config *, | |
43 | int num_counters); | |
44 | void (*cpu_setup) (void *); | |
45 | void (*start) (struct op_counter_config *); | |
46 | void (*stop) (void); | |
47 | void (*handle_interrupt) (struct pt_regs *, | |
48 | struct op_counter_config *); | |
49 | int num_counters; | |
50 | }; | |
51 | ||
a3e48c10 SR |
52 | extern struct op_powerpc_model op_model_rs64; |
53 | extern struct op_powerpc_model op_model_power4; | |
dca85932 | 54 | |
1da177e4 LT |
55 | static inline unsigned int ctr_read(unsigned int i) |
56 | { | |
57 | switch(i) { | |
58 | case 0: | |
59 | return mfspr(SPRN_PMC1); | |
60 | case 1: | |
61 | return mfspr(SPRN_PMC2); | |
62 | case 2: | |
63 | return mfspr(SPRN_PMC3); | |
64 | case 3: | |
65 | return mfspr(SPRN_PMC4); | |
66 | case 4: | |
67 | return mfspr(SPRN_PMC5); | |
68 | case 5: | |
69 | return mfspr(SPRN_PMC6); | |
70 | case 6: | |
71 | return mfspr(SPRN_PMC7); | |
72 | case 7: | |
73 | return mfspr(SPRN_PMC8); | |
74 | default: | |
75 | return 0; | |
76 | } | |
77 | } | |
78 | ||
79 | static inline void ctr_write(unsigned int i, unsigned int val) | |
80 | { | |
81 | switch(i) { | |
82 | case 0: | |
83 | mtspr(SPRN_PMC1, val); | |
84 | break; | |
85 | case 1: | |
86 | mtspr(SPRN_PMC2, val); | |
87 | break; | |
88 | case 2: | |
89 | mtspr(SPRN_PMC3, val); | |
90 | break; | |
91 | case 3: | |
92 | mtspr(SPRN_PMC4, val); | |
93 | break; | |
94 | case 4: | |
95 | mtspr(SPRN_PMC5, val); | |
96 | break; | |
97 | case 5: | |
98 | mtspr(SPRN_PMC6, val); | |
99 | break; | |
100 | case 6: | |
101 | mtspr(SPRN_PMC7, val); | |
102 | break; | |
103 | case 7: | |
104 | mtspr(SPRN_PMC8, val); | |
105 | break; | |
106 | default: | |
107 | break; | |
108 | } | |
109 | } | |
110 | ||
111 | #endif |