Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef _PPC64_PGTABLE_H |
2 | #define _PPC64_PGTABLE_H | |
3 | ||
1da177e4 LT |
4 | /* |
5 | * This file contains the functions and defines necessary to modify and use | |
6 | * the ppc64 hashed page table. | |
7 | */ | |
8 | ||
9 | #ifndef __ASSEMBLY__ | |
10 | #include <linux/config.h> | |
11 | #include <linux/stddef.h> | |
12 | #include <asm/processor.h> /* For TASK_SIZE */ | |
13 | #include <asm/mmu.h> | |
14 | #include <asm/page.h> | |
15 | #include <asm/tlbflush.h> | |
16 | #endif /* __ASSEMBLY__ */ | |
17 | ||
58366af5 BH |
18 | #include <asm-generic/pgtable-nopud.h> |
19 | ||
1da177e4 LT |
20 | /* |
21 | * Entries per page directory level. The PTE level must use a 64b record | |
22 | * for each page table entry. The PMD and PGD level use a 32b record for | |
23 | * each entry by assuming that each entry is page aligned. | |
24 | */ | |
25 | #define PTE_INDEX_SIZE 9 | |
26 | #define PMD_INDEX_SIZE 10 | |
27 | #define PGD_INDEX_SIZE 10 | |
28 | ||
29 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
30 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
31 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
32 | ||
1f8d419e DG |
33 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
34 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
35 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
36 | #define PMD_MASK (~(PMD_SIZE-1)) | |
1da177e4 | 37 | |
1f8d419e DG |
38 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ |
39 | #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
40 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
41 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
42 | ||
43 | #define FIRST_USER_ADDRESS 0 | |
1da177e4 LT |
44 | |
45 | /* | |
46 | * Size of EA range mapped by our pagetables. | |
47 | */ | |
1f8d419e DG |
48 | #define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ |
49 | PGD_INDEX_SIZE + PAGE_SHIFT) | |
50 | #define EADDR_MASK ((1UL << EADDR_SIZE) - 1) | |
1da177e4 LT |
51 | |
52 | /* | |
53 | * Define the address range of the vmalloc VM area. | |
54 | */ | |
55 | #define VMALLOC_START (0xD000000000000000ul) | |
1f8d419e | 56 | #define VMALLOC_END (VMALLOC_START + EADDR_MASK) |
1da177e4 LT |
57 | |
58 | /* | |
59 | * Bits in a linux-style PTE. These match the bits in the | |
60 | * (hardware-defined) PowerPC PTE as closely as possible. | |
61 | */ | |
62 | #define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */ | |
63 | #define _PAGE_USER 0x0002 /* matches one of the PP bits */ | |
64 | #define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */ | |
65 | #define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */ | |
66 | #define _PAGE_GUARDED 0x0008 | |
67 | #define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */ | |
68 | #define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */ | |
69 | #define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */ | |
70 | #define _PAGE_DIRTY 0x0080 /* C: page changed */ | |
71 | #define _PAGE_ACCESSED 0x0100 /* R: page referenced */ | |
72 | #define _PAGE_RW 0x0200 /* software: user write access allowed */ | |
73 | #define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */ | |
74 | #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ | |
75 | #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */ | |
76 | #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */ | |
77 | #define _PAGE_HUGE 0x10000 /* 16MB page */ | |
78 | /* Bits 0x7000 identify the index within an HPT Group */ | |
79 | #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_SECONDARY | _PAGE_GROUP_IX) | |
80 | /* PAGE_MASK gives the right answer below, but only by accident */ | |
81 | /* It should be preserving the high 48 bits and then specifically */ | |
82 | /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */ | |
83 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HPTEFLAGS) | |
84 | ||
85 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) | |
86 | ||
87 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY) | |
88 | ||
89 | /* __pgprot defined in asm-ppc64/page.h */ | |
90 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | |
91 | ||
92 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER) | |
93 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC) | |
94 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) | |
95 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | |
96 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) | |
97 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | |
98 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE) | |
99 | #define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | |
100 | _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED) | |
101 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC) | |
102 | ||
103 | #define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE) | |
104 | #define HAVE_PAGE_AGP | |
105 | ||
106 | /* | |
107 | * This bit in a hardware PTE indicates that the page is *not* executable. | |
108 | */ | |
109 | #define HW_NO_EXEC _PAGE_EXEC | |
110 | ||
111 | /* | |
112 | * POWER4 and newer have per page execute protection, older chips can only | |
113 | * do this on a segment (256MB) basis. | |
114 | * | |
115 | * Also, write permissions imply read permissions. | |
116 | * This is the closest we can get.. | |
117 | * | |
118 | * Note due to the way vm flags are laid out, the bits are XWR | |
119 | */ | |
120 | #define __P000 PAGE_NONE | |
121 | #define __P001 PAGE_READONLY | |
122 | #define __P010 PAGE_COPY | |
123 | #define __P011 PAGE_COPY | |
124 | #define __P100 PAGE_READONLY_X | |
125 | #define __P101 PAGE_READONLY_X | |
126 | #define __P110 PAGE_COPY_X | |
127 | #define __P111 PAGE_COPY_X | |
128 | ||
129 | #define __S000 PAGE_NONE | |
130 | #define __S001 PAGE_READONLY | |
131 | #define __S010 PAGE_SHARED | |
132 | #define __S011 PAGE_SHARED | |
133 | #define __S100 PAGE_READONLY_X | |
134 | #define __S101 PAGE_READONLY_X | |
135 | #define __S110 PAGE_SHARED_X | |
136 | #define __S111 PAGE_SHARED_X | |
137 | ||
138 | #ifndef __ASSEMBLY__ | |
139 | ||
140 | /* | |
141 | * ZERO_PAGE is a global shared page that is always zero: used | |
142 | * for zero-mapped memory areas etc.. | |
143 | */ | |
144 | extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; | |
145 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | |
146 | #endif /* __ASSEMBLY__ */ | |
147 | ||
148 | /* shift to put page number into pte */ | |
149 | #define PTE_SHIFT (17) | |
150 | ||
1da177e4 LT |
151 | #ifdef CONFIG_HUGETLB_PAGE |
152 | ||
153 | #ifndef __ASSEMBLY__ | |
154 | int hash_huge_page(struct mm_struct *mm, unsigned long access, | |
155 | unsigned long ea, unsigned long vsid, int local); | |
156 | ||
157 | void hugetlb_mm_free_pgd(struct mm_struct *mm); | |
158 | #endif /* __ASSEMBLY__ */ | |
159 | ||
160 | #define HAVE_ARCH_UNMAPPED_AREA | |
161 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
162 | #else | |
163 | ||
164 | #define hash_huge_page(mm,a,ea,vsid,local) -1 | |
165 | #define hugetlb_mm_free_pgd(mm) do {} while (0) | |
166 | ||
167 | #endif | |
168 | ||
169 | #ifndef __ASSEMBLY__ | |
170 | ||
171 | /* | |
172 | * Conversion functions: convert a page and protection to a page entry, | |
173 | * and a page entry and page directory to the page they refer to. | |
174 | * | |
175 | * mk_pte takes a (struct page *) as input | |
176 | */ | |
177 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
178 | ||
1f8d419e DG |
179 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) |
180 | { | |
181 | pte_t pte; | |
182 | ||
183 | ||
184 | pte_val(pte) = (pfn << PTE_SHIFT) | pgprot_val(pgprot); | |
185 | return pte; | |
186 | } | |
1da177e4 LT |
187 | |
188 | #define pte_modify(_pte, newprot) \ | |
189 | (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))) | |
190 | ||
191 | #define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0) | |
192 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) | |
193 | ||
194 | /* pte_clear moved to later in this file */ | |
195 | ||
196 | #define pte_pfn(x) ((unsigned long)((pte_val(x) >> PTE_SHIFT))) | |
197 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
198 | ||
199 | #define pmd_set(pmdp, ptep) \ | |
1f8d419e | 200 | (pmd_val(*(pmdp)) = __ba_to_bpn(ptep)) |
1da177e4 LT |
201 | #define pmd_none(pmd) (!pmd_val(pmd)) |
202 | #define pmd_bad(pmd) (pmd_val(pmd) == 0) | |
203 | #define pmd_present(pmd) (pmd_val(pmd) != 0) | |
204 | #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) | |
1f8d419e | 205 | #define pmd_page_kernel(pmd) (__bpn_to_ba(pmd_val(pmd))) |
1da177e4 | 206 | #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd)) |
58366af5 BH |
207 | |
208 | #define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (__ba_to_bpn(pmdp))) | |
209 | #define pud_none(pud) (!pud_val(pud)) | |
210 | #define pud_bad(pud) ((pud_val(pud)) == 0UL) | |
211 | #define pud_present(pud) (pud_val(pud) != 0UL) | |
212 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) | |
213 | #define pud_page(pud) (__bpn_to_ba(pud_val(pud))) | |
1da177e4 LT |
214 | |
215 | /* | |
216 | * Find an entry in a page-table-directory. We combine the address region | |
217 | * (the high order N bits) and the pgd portion of the address. | |
218 | */ | |
219 | /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */ | |
220 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x7ff) | |
221 | ||
222 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
223 | ||
224 | /* Find an entry in the second-level page table.. */ | |
58366af5 BH |
225 | #define pmd_offset(pudp,addr) \ |
226 | ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) | |
1da177e4 LT |
227 | |
228 | /* Find an entry in the third-level page table.. */ | |
229 | #define pte_offset_kernel(dir,addr) \ | |
58366af5 BH |
230 | ((pte_t *) pmd_page_kernel(*(dir)) \ |
231 | + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) | |
1da177e4 LT |
232 | |
233 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
234 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
235 | #define pte_unmap(pte) do { } while(0) | |
236 | #define pte_unmap_nested(pte) do { } while(0) | |
237 | ||
238 | /* to find an entry in a kernel page-table-directory */ | |
239 | /* This now only contains the vmalloc pages */ | |
240 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
241 | ||
242 | /* to find an entry in the ioremap page-table-directory */ | |
243 | #define pgd_offset_i(address) (ioremap_pgd + pgd_index(address)) | |
244 | ||
1da177e4 LT |
245 | /* |
246 | * The following only work if pte_present() is true. | |
247 | * Undefined behaviour if not.. | |
248 | */ | |
249 | static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;} | |
250 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;} | |
251 | static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;} | |
252 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;} | |
253 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;} | |
254 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;} | |
255 | static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE;} | |
256 | ||
257 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } | |
258 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } | |
259 | ||
260 | static inline pte_t pte_rdprotect(pte_t pte) { | |
261 | pte_val(pte) &= ~_PAGE_USER; return pte; } | |
262 | static inline pte_t pte_exprotect(pte_t pte) { | |
263 | pte_val(pte) &= ~_PAGE_EXEC; return pte; } | |
264 | static inline pte_t pte_wrprotect(pte_t pte) { | |
265 | pte_val(pte) &= ~(_PAGE_RW); return pte; } | |
266 | static inline pte_t pte_mkclean(pte_t pte) { | |
267 | pte_val(pte) &= ~(_PAGE_DIRTY); return pte; } | |
268 | static inline pte_t pte_mkold(pte_t pte) { | |
269 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | |
270 | ||
271 | static inline pte_t pte_mkread(pte_t pte) { | |
272 | pte_val(pte) |= _PAGE_USER; return pte; } | |
273 | static inline pte_t pte_mkexec(pte_t pte) { | |
274 | pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } | |
275 | static inline pte_t pte_mkwrite(pte_t pte) { | |
276 | pte_val(pte) |= _PAGE_RW; return pte; } | |
277 | static inline pte_t pte_mkdirty(pte_t pte) { | |
278 | pte_val(pte) |= _PAGE_DIRTY; return pte; } | |
279 | static inline pte_t pte_mkyoung(pte_t pte) { | |
280 | pte_val(pte) |= _PAGE_ACCESSED; return pte; } | |
281 | static inline pte_t pte_mkhuge(pte_t pte) { | |
282 | pte_val(pte) |= _PAGE_HUGE; return pte; } | |
283 | ||
284 | /* Atomic PTE updates */ | |
285 | static inline unsigned long pte_update(pte_t *p, unsigned long clr) | |
286 | { | |
287 | unsigned long old, tmp; | |
288 | ||
289 | __asm__ __volatile__( | |
290 | "1: ldarx %0,0,%3 # pte_update\n\ | |
291 | andi. %1,%0,%6\n\ | |
292 | bne- 1b \n\ | |
293 | andc %1,%0,%4 \n\ | |
294 | stdcx. %1,0,%3 \n\ | |
295 | bne- 1b" | |
296 | : "=&r" (old), "=&r" (tmp), "=m" (*p) | |
297 | : "r" (p), "r" (clr), "m" (*p), "i" (_PAGE_BUSY) | |
298 | : "cc" ); | |
299 | return old; | |
300 | } | |
301 | ||
302 | /* PTE updating functions, this function puts the PTE in the | |
303 | * batch, doesn't actually triggers the hash flush immediately, | |
304 | * you need to call flush_tlb_pending() to do that. | |
305 | */ | |
306 | extern void hpte_update(struct mm_struct *mm, unsigned long addr, unsigned long pte, | |
307 | int wrprot); | |
308 | ||
309 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
310 | { | |
311 | unsigned long old; | |
312 | ||
313 | if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) | |
314 | return 0; | |
315 | old = pte_update(ptep, _PAGE_ACCESSED); | |
316 | if (old & _PAGE_HASHPTE) { | |
317 | hpte_update(mm, addr, old, 0); | |
318 | flush_tlb_pending(); | |
319 | } | |
320 | return (old & _PAGE_ACCESSED) != 0; | |
321 | } | |
322 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
323 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
324 | ({ \ | |
325 | int __r; \ | |
326 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
327 | __r; \ | |
328 | }) | |
329 | ||
330 | /* | |
331 | * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the | |
332 | * moment we always flush but we need to fix hpte_update and test if the | |
333 | * optimisation is worth it. | |
334 | */ | |
335 | static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
336 | { | |
337 | unsigned long old; | |
338 | ||
339 | if ((pte_val(*ptep) & _PAGE_DIRTY) == 0) | |
340 | return 0; | |
341 | old = pte_update(ptep, _PAGE_DIRTY); | |
342 | if (old & _PAGE_HASHPTE) | |
343 | hpte_update(mm, addr, old, 0); | |
344 | return (old & _PAGE_DIRTY) != 0; | |
345 | } | |
346 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY | |
347 | #define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \ | |
348 | ({ \ | |
349 | int __r; \ | |
350 | __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \ | |
351 | __r; \ | |
352 | }) | |
353 | ||
354 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
355 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
356 | { | |
357 | unsigned long old; | |
358 | ||
359 | if ((pte_val(*ptep) & _PAGE_RW) == 0) | |
360 | return; | |
361 | old = pte_update(ptep, _PAGE_RW); | |
362 | if (old & _PAGE_HASHPTE) | |
363 | hpte_update(mm, addr, old, 0); | |
364 | } | |
365 | ||
366 | /* | |
367 | * We currently remove entries from the hashtable regardless of whether | |
368 | * the entry was young or dirty. The generic routines only flush if the | |
369 | * entry was young or dirty which is not good enough. | |
370 | * | |
371 | * We should be more intelligent about this but for the moment we override | |
372 | * these functions and force a tlb flush unconditionally | |
373 | */ | |
374 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
375 | #define ptep_clear_flush_young(__vma, __address, __ptep) \ | |
376 | ({ \ | |
377 | int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \ | |
378 | __ptep); \ | |
379 | __young; \ | |
380 | }) | |
381 | ||
382 | #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH | |
383 | #define ptep_clear_flush_dirty(__vma, __address, __ptep) \ | |
384 | ({ \ | |
385 | int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \ | |
386 | __ptep); \ | |
387 | flush_tlb_page(__vma, __address); \ | |
388 | __dirty; \ | |
389 | }) | |
390 | ||
391 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
392 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
393 | { | |
394 | unsigned long old = pte_update(ptep, ~0UL); | |
395 | ||
396 | if (old & _PAGE_HASHPTE) | |
397 | hpte_update(mm, addr, old, 0); | |
398 | return __pte(old); | |
399 | } | |
400 | ||
401 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t * ptep) | |
402 | { | |
403 | unsigned long old = pte_update(ptep, ~0UL); | |
404 | ||
405 | if (old & _PAGE_HASHPTE) | |
406 | hpte_update(mm, addr, old, 0); | |
407 | } | |
408 | ||
409 | /* | |
410 | * set_pte stores a linux PTE into the linux page table. | |
411 | */ | |
412 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
413 | pte_t *ptep, pte_t pte) | |
414 | { | |
415 | if (pte_present(*ptep)) { | |
416 | pte_clear(mm, addr, ptep); | |
417 | flush_tlb_pending(); | |
418 | } | |
1f8d419e | 419 | *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); |
1da177e4 LT |
420 | } |
421 | ||
422 | /* Set the dirty and/or accessed bits atomically in a linux PTE, this | |
423 | * function doesn't need to flush the hash entry | |
424 | */ | |
425 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
426 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) | |
427 | { | |
428 | unsigned long bits = pte_val(entry) & | |
429 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); | |
430 | unsigned long old, tmp; | |
431 | ||
432 | __asm__ __volatile__( | |
433 | "1: ldarx %0,0,%4\n\ | |
434 | andi. %1,%0,%6\n\ | |
435 | bne- 1b \n\ | |
436 | or %0,%3,%0\n\ | |
437 | stdcx. %0,0,%4\n\ | |
438 | bne- 1b" | |
439 | :"=&r" (old), "=&r" (tmp), "=m" (*ptep) | |
440 | :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) | |
441 | :"cc"); | |
442 | } | |
443 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ | |
444 | do { \ | |
445 | __ptep_set_access_flags(__ptep, __entry, __dirty); \ | |
446 | flush_tlb_page_nohash(__vma, __address); \ | |
447 | } while(0) | |
448 | ||
449 | /* | |
450 | * Macro to mark a page protection value as "uncacheable". | |
451 | */ | |
452 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
453 | ||
454 | struct file; | |
455 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, | |
456 | unsigned long size, pgprot_t vma_prot); | |
457 | #define __HAVE_PHYS_MEM_ACCESS_PROT | |
458 | ||
459 | #define __HAVE_ARCH_PTE_SAME | |
460 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) | |
461 | ||
462 | extern unsigned long ioremap_bot, ioremap_base; | |
463 | ||
1da177e4 LT |
464 | #define pmd_ERROR(e) \ |
465 | printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e)) | |
466 | #define pgd_ERROR(e) \ | |
467 | printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e)) | |
468 | ||
1f8d419e DG |
469 | extern pgd_t swapper_pg_dir[]; |
470 | extern pgd_t ioremap_dir[]; | |
1da177e4 LT |
471 | |
472 | extern void paging_init(void); | |
473 | ||
3bf5ee95 HD |
474 | /* |
475 | * Because the huge pgtables are only 2 level, they can take | |
476 | * at most around 4M, much less than one hugepage which the | |
477 | * process is presumably entitled to use. So we don't bother | |
478 | * freeing up the pagetables on unmap, and wait until | |
479 | * destroy_context() to clean up the lot. | |
480 | */ | |
481 | #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \ | |
482 | do { } while (0) | |
1da177e4 LT |
483 | |
484 | /* | |
485 | * This gets called at the end of handling a page fault, when | |
486 | * the kernel has put a new PTE into the page table for the process. | |
487 | * We use it to put a corresponding HPTE into the hash table | |
488 | * ahead of time, instead of waiting for the inevitable extra | |
489 | * hash-table miss exception. | |
490 | */ | |
491 | struct vm_area_struct; | |
492 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | |
493 | ||
494 | /* Encode and de-code a swap entry */ | |
495 | #define __swp_type(entry) (((entry).val >> 1) & 0x3f) | |
496 | #define __swp_offset(entry) ((entry).val >> 8) | |
497 | #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) | |
498 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> PTE_SHIFT }) | |
499 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_SHIFT }) | |
500 | #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT) | |
501 | #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_SHIFT)|_PAGE_FILE}) | |
502 | #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT) | |
503 | ||
504 | /* | |
505 | * kern_addr_valid is intended to indicate whether an address is a valid | |
506 | * kernel address. Most 32-bit archs define it as always true (like this) | |
507 | * but most 64-bit archs actually perform a test. What should we do here? | |
508 | * The only use is in fs/ncpfs/dir.c | |
509 | */ | |
510 | #define kern_addr_valid(addr) (1) | |
511 | ||
1da177e4 LT |
512 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ |
513 | remap_pfn_range(vma, vaddr, pfn, size, prot) | |
514 | ||
1da177e4 LT |
515 | void pgtable_cache_init(void); |
516 | ||
1da177e4 LT |
517 | /* |
518 | * find_linux_pte returns the address of a linux pte for a given | |
519 | * effective address and directory. If not found, it returns zero. | |
520 | */ | |
521 | static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) | |
522 | { | |
523 | pgd_t *pg; | |
58366af5 | 524 | pud_t *pu; |
1da177e4 LT |
525 | pmd_t *pm; |
526 | pte_t *pt = NULL; | |
527 | pte_t pte; | |
528 | ||
529 | pg = pgdir + pgd_index(ea); | |
530 | if (!pgd_none(*pg)) { | |
58366af5 BH |
531 | pu = pud_offset(pg, ea); |
532 | if (!pud_none(*pu)) { | |
533 | pm = pmd_offset(pu, ea); | |
534 | if (pmd_present(*pm)) { | |
535 | pt = pte_offset_kernel(pm, ea); | |
536 | pte = *pt; | |
537 | if (!pte_present(pte)) | |
538 | pt = NULL; | |
539 | } | |
1da177e4 LT |
540 | } |
541 | } | |
542 | ||
543 | return pt; | |
544 | } | |
545 | ||
546 | #include <asm-generic/pgtable.h> | |
547 | ||
548 | #endif /* __ASSEMBLY__ */ | |
549 | ||
550 | #endif /* _PPC64_PGTABLE_H */ |