[deliverable/linux.git] / include / asm-ppc64 / pgtable.h

#ifndef _PPC64_PGTABLE_H
#define _PPC64_PGTABLE_H

/*
 * This file contains the functions and defines necessary to modify and use
 * the ppc64 hashed page table.
 */

#ifndef __ASSEMBLY__
#include <linux/config.h>
#include <linux/stddef.h>
#include <asm/processor.h>		/* For TASK_SIZE */
#include <asm/mmu.h>
#include <asm/page.h>
#include <asm/tlbflush.h>
struct mm_struct;
#endif /* __ASSEMBLY__ */

#ifdef CONFIG_PPC_64K_PAGES
#include <asm/pgtable-64k.h>
#else
#include <asm/pgtable-4k.h>
#endif

#define FIRST_USER_ADDRESS	0

/*
 * Size of EA range mapped by our pagetables.
 */
#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
                	    PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)

#if TASK_SIZE_USER64 > PGTABLE_RANGE
#error TASK_SIZE_USER64 exceeds pagetable range
#endif

#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
#error TASK_SIZE_USER64 exceeds user VSID range
#endif

/*
 * Define the address range of the vmalloc VM area.
 */
#define VMALLOC_START (0xD000000000000000ul)
#define VMALLOC_SIZE  (0x80000000000UL)
#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)

/*
 * Define the address range of the imalloc VM area.
 */
#define PHBS_IO_BASE	VMALLOC_END
#define IMALLOC_BASE	(PHBS_IO_BASE + 0x80000000ul)	/* Reserve 2 gigs for PHBs */
#define IMALLOC_END	(VMALLOC_START + PGTABLE_RANGE)

/*
 * Common bits in a linux-style PTE.  These match the bits in the
 * (hardware-defined) PowerPC PTE as closely as possible. Additional
 * bits may be defined in pgtable-*.h
 */
#define _PAGE_PRESENT	0x0001 /* software: pte contains a translation */
#define _PAGE_USER	0x0002 /* matches one of the PP bits */
#define _PAGE_FILE	0x0002 /* (!present only) software: pte holds file offset */
#define _PAGE_EXEC	0x0004 /* No execute on POWER4 and newer (we invert) */
#define _PAGE_GUARDED	0x0008
#define _PAGE_COHERENT	0x0010 /* M: enforce memory coherence (SMP systems) */
#define _PAGE_NO_CACHE	0x0020 /* I: cache inhibit */
#define _PAGE_WRITETHRU	0x0040 /* W: cache write-through */
#define _PAGE_DIRTY	0x0080 /* C: page changed */
#define _PAGE_ACCESSED	0x0100 /* R: page referenced */
#define _PAGE_RW	0x0200 /* software: user write access allowed */
#define _PAGE_HASHPTE	0x0400 /* software: pte has an associated HPTE */
#define _PAGE_BUSY	0x0800 /* software: PTE & hash are busy */ 

#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)

#define _PAGE_WRENABLE	(_PAGE_RW | _PAGE_DIRTY)

/* __pgprot defined in asm-ppc64/page.h */
#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)

#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
#define PAGE_KERNEL	__pgprot(_PAGE_BASE | _PAGE_WRENABLE)
#define PAGE_KERNEL_CI	__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
			       _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)

#define PAGE_AGP	__pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
#define HAVE_PAGE_AGP

/* PTEIDX nibble */
#define _PTEIDX_SECONDARY	0x8
#define _PTEIDX_GROUP_IX	0x7


/*
 * POWER4 and newer have per page execute protection, older chips can only
 * do this on a segment (256MB) basis.
 *
 * Also, write permissions imply read permissions.
 * This is the closest we can get..
 *
 * Note due to the way vm flags are laid out, the bits are XWR
 */
#define __P000	PAGE_NONE
#define __P001	PAGE_READONLY
#define __P010	PAGE_COPY
#define __P011	PAGE_COPY
#define __P100	PAGE_READONLY_X
#define __P101	PAGE_READONLY_X
#define __P110	PAGE_COPY_X
#define __P111	PAGE_COPY_X

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY_X
#define __S101	PAGE_READONLY_X
#define __S110	PAGE_SHARED_X
#define __S111	PAGE_SHARED_X

#ifndef __ASSEMBLY__

/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
#endif /* __ASSEMBLY__ */

#ifdef CONFIG_HUGETLB_PAGE

#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN

#endif

#ifndef __ASSEMBLY__

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 *
 * mk_pte takes a (struct page *) as input
 */
#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))

static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
{
	pte_t pte;


	pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
	return pte;
}

#define pte_modify(_pte, newprot) \
  (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))

#define pte_none(pte)		((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
#define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)

/* pte_clear moved to later in this file */

#define pte_pfn(x)		((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
#define pte_page(x)		pfn_to_page(pte_pfn(x))

#define pmd_set(pmdp, pmdval) 	(pmd_val(*(pmdp)) = (pmdval))
#define pmd_none(pmd)		(!pmd_val(pmd))
#define	pmd_bad(pmd)		(pmd_val(pmd) == 0)
#define	pmd_present(pmd)	(pmd_val(pmd) != 0)
#define	pmd_clear(pmdp)		(pmd_val(*(pmdp)) = 0)
#define pmd_page_kernel(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
#define pmd_page(pmd)		virt_to_page(pmd_page_kernel(pmd))

#define pud_set(pudp, pudval)	(pud_val(*(pudp)) = (pudval))
#define pud_none(pud)		(!pud_val(pud))
#define pud_bad(pud)		((pud_val(pud)) == 0)
#define pud_present(pud)	(pud_val(pud) != 0)
#define pud_clear(pudp)		(pud_val(*(pudp)) = 0)
#define pud_page(pud)		(pud_val(pud) & ~PUD_MASKED_BITS)

#define pgd_set(pgdp, pudp)	({pgd_val(*(pgdp)) = (unsigned long)(pudp);})

/* 
 * Find an entry in a page-table-directory.  We combine the address region 
 * (the high order N bits) and the pgd portion of the address.
 */
/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)

#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))

#define pmd_offset(pudp,addr) \
  (((pmd_t *) pud_page(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))

#define pte_offset_kernel(dir,addr) \
  (((pte_t *) pmd_page_kernel(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))

#define pte_offset_map(dir,addr)	pte_offset_kernel((dir), (addr))
#define pte_offset_map_nested(dir,addr)	pte_offset_kernel((dir), (addr))
#define pte_unmap(pte)			do { } while(0)
#define pte_unmap_nested(pte)		do { } while(0)

/* to find an entry in a kernel page-table-directory */
/* This now only contains the vmalloc pages */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER;}
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC;}
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}

static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }

static inline pte_t pte_rdprotect(pte_t pte) {
	pte_val(pte) &= ~_PAGE_USER; return pte; }
static inline pte_t pte_exprotect(pte_t pte) {
	pte_val(pte) &= ~_PAGE_EXEC; return pte; }
static inline pte_t pte_wrprotect(pte_t pte) {
	pte_val(pte) &= ~(_PAGE_RW); return pte; }
static inline pte_t pte_mkclean(pte_t pte) {
	pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
static inline pte_t pte_mkold(pte_t pte) {
	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkread(pte_t pte) {
	pte_val(pte) |= _PAGE_USER; return pte; }
static inline pte_t pte_mkexec(pte_t pte) {
	pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
static inline pte_t pte_mkwrite(pte_t pte) {
	pte_val(pte) |= _PAGE_RW; return pte; }
static inline pte_t pte_mkdirty(pte_t pte) {
	pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte) {
	pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkhuge(pte_t pte) {
	return pte; }

/* Atomic PTE updates */
static inline unsigned long pte_update(pte_t *p, unsigned long clr)
{
	unsigned long old, tmp;

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%3		# pte_update\n\
	andi.	%1,%0,%6\n\
	bne-	1b \n\
	andc	%1,%0,%4 \n\
	stdcx.	%1,0,%3 \n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" (clr), "m" (*p), "i" (_PAGE_BUSY)
	: "cc" );
	return old;
}

/* PTE updating functions, this function puts the PTE in the
 * batch, doesn't actually triggers the hash flush immediately,
 * you need to call flush_tlb_pending() to do that.
 * Pass -1 for "normal" size (4K or 64K)
 */
extern void hpte_update(struct mm_struct *mm, unsigned long addr,
			pte_t *ptep, unsigned long pte, int huge);

static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
					      unsigned long addr, pte_t *ptep)
{
	unsigned long old;

       	if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
		return 0;
	old = pte_update(ptep, _PAGE_ACCESSED);
	if (old & _PAGE_HASHPTE) {
		hpte_update(mm, addr, ptep, old, 0);
		flush_tlb_pending();
	}
	return (old & _PAGE_ACCESSED) != 0;
}
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define ptep_test_and_clear_young(__vma, __addr, __ptep)		   \
({									   \
	int __r;							   \
	__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
	__r;								   \
})

/*
 * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
 * moment we always flush but we need to fix hpte_update and test if the
 * optimisation is worth it.
 */
static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
					      unsigned long addr, pte_t *ptep)
{
	unsigned long old;

       	if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
		return 0;
	old = pte_update(ptep, _PAGE_DIRTY);
	if (old & _PAGE_HASHPTE)
		hpte_update(mm, addr, ptep, old, 0);
	return (old & _PAGE_DIRTY) != 0;
}
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
#define ptep_test_and_clear_dirty(__vma, __addr, __ptep)		   \
({									   \
	int __r;							   \
	__r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
	__r;								   \
})

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
				      pte_t *ptep)
{
	unsigned long old;

       	if ((pte_val(*ptep) & _PAGE_RW) == 0)
       		return;
	old = pte_update(ptep, _PAGE_RW);
	if (old & _PAGE_HASHPTE)
		hpte_update(mm, addr, ptep, old, 0);
}

/*
 * We currently remove entries from the hashtable regardless of whether
 * the entry was young or dirty. The generic routines only flush if the
 * entry was young or dirty which is not good enough.
 *
 * We should be more intelligent about this but for the moment we override
 * these functions and force a tlb flush unconditionally
 */
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
#define ptep_clear_flush_young(__vma, __address, __ptep)		\
({									\
	int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
						  __ptep);		\
	__young;							\
})

#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
#define ptep_clear_flush_dirty(__vma, __address, __ptep)		\
({									\
	int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
						  __ptep); 		\
	flush_tlb_page(__vma, __address);				\
	__dirty;							\
})

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
				       unsigned long addr, pte_t *ptep)
{
	unsigned long old = pte_update(ptep, ~0UL);

	if (old & _PAGE_HASHPTE)
		hpte_update(mm, addr, ptep, old, 0);
	return __pte(old);
}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
			     pte_t * ptep)
{
	unsigned long old = pte_update(ptep, ~0UL);

	if (old & _PAGE_HASHPTE)
		hpte_update(mm, addr, ptep, old, 0);
}

/*
 * set_pte stores a linux PTE into the linux page table.
 */
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
			      pte_t *ptep, pte_t pte)
{
	if (pte_present(*ptep)) {
		pte_clear(mm, addr, ptep);
		flush_tlb_pending();
	}
	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);

#ifdef CONFIG_PPC_64K_PAGES
	if (mmu_virtual_psize != MMU_PAGE_64K)
		pte = __pte(pte_val(pte) | _PAGE_COMBO);
#endif /* CONFIG_PPC_64K_PAGES */

	*ptep = pte;
}

/* Set the dirty and/or accessed bits atomically in a linux PTE, this
 * function doesn't need to flush the hash entry
 */
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
{
	unsigned long bits = pte_val(entry) &
		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
	unsigned long old, tmp;

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%4\n\
		andi.	%1,%0,%6\n\
		bne-	1b \n\
		or	%0,%3,%0\n\
		stdcx.	%0,0,%4\n\
		bne-	1b"
	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
	:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
	:"cc");
}
#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
	do {								   \
		__ptep_set_access_flags(__ptep, __entry, __dirty);	   \
		flush_tlb_page_nohash(__vma, __address);	       	   \
	} while(0)

/*
 * Macro to mark a page protection value as "uncacheable".
 */
#define pgprot_noncached(prot)	(__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))

struct file;
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
				     unsigned long size, pgprot_t vma_prot);
#define __HAVE_PHYS_MEM_ACCESS_PROT

#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern pgd_t swapper_pg_dir[];

extern void paging_init(void);

#ifdef CONFIG_HUGETLB_PAGE
#define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
	free_pgd_range(tlb, addr, end, floor, ceiling)
#endif

/*
 * This gets called at the end of handling a page fault, when
 * the kernel has put a new PTE into the page table for the process.
 * We use it to put a corresponding HPTE into the hash table
 * ahead of time, instead of waiting for the inevitable extra
 * hash-table miss exception.
 */
struct vm_area_struct;
extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);

/* Encode and de-code a swap entry */
#define __swp_type(entry)	(((entry).val >> 1) & 0x3f)
#define __swp_offset(entry)	((entry).val >> 8)
#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })
#define pte_to_pgoff(pte)	(pte_val(pte) >> PTE_RPN_SHIFT)
#define pgoff_to_pte(off)	((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_RPN_SHIFT)

/*
 * kern_addr_valid is intended to indicate whether an address is a valid
 * kernel address.  Most 32-bit archs define it as always true (like this)
 * but most 64-bit archs actually perform a test.  What should we do here?
 * The only use is in fs/ncpfs/dir.c
 */
#define kern_addr_valid(addr)	(1)

#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
		remap_pfn_range(vma, vaddr, pfn, size, prot)

void pgtable_cache_init(void);

/*
 * find_linux_pte returns the address of a linux pte for a given 
 * effective address and directory.  If not found, it returns zero.
 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
{
	pgd_t *pg;
	pud_t *pu;
	pmd_t *pm;
	pte_t *pt = NULL;

	pg = pgdir + pgd_index(ea);
	if (!pgd_none(*pg)) {
		pu = pud_offset(pg, ea);
		if (!pud_none(*pu)) {
			pm = pmd_offset(pu, ea);
			if (pmd_present(*pm))
				pt = pte_offset_kernel(pm, ea);
		}
	}
	return pt;
}

#include <asm-generic/pgtable.h>

#endif /* __ASSEMBLY__ */

#endif /* _PPC64_PGTABLE_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _PPC64_PGTABLE_H
	2	#define _PPC64_PGTABLE_H
	3
1da177e4 LT	4	/*
	5	* This file contains the functions and defines necessary to modify and use
	6	* the ppc64 hashed page table.
	7	*/
	8
	9	#ifndef __ASSEMBLY__
	10	#include <linux/config.h>
	11	#include <linux/stddef.h>
	12	#include <asm/processor.h> /* For TASK_SIZE */
	13	#include <asm/mmu.h>
	14	#include <asm/page.h>
	15	#include <asm/tlbflush.h>
8c65b4a6	16	struct mm_struct;
1da177e4 LT	17	#endif /* __ASSEMBLY__ */
1da177e4 LT	18
3c726f8d BH	19	#ifdef CONFIG_PPC_64K_PAGES
	20	#include <asm/pgtable-64k.h>
	21	#else
	22	#include <asm/pgtable-4k.h>
	23	#endif
1f8d419e DG	24
1f8d419e DG	25	#define FIRST_USER_ADDRESS 0
1da177e4 LT	26
	27	/*
	28	* Size of EA range mapped by our pagetables.
	29	*/
e28f7faf DG	30	#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
	31	PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
	32	#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
	33
	34	#if TASK_SIZE_USER64 > PGTABLE_RANGE
	35	#error TASK_SIZE_USER64 exceeds pagetable range
	36	#endif
	37
	38	#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
	39	#error TASK_SIZE_USER64 exceeds user VSID range
	40	#endif
1da177e4 LT	41
	42	/*
	43	* Define the address range of the vmalloc VM area.
	44	*/
	45	#define VMALLOC_START (0xD000000000000000ul)
e28f7faf	46	#define VMALLOC_SIZE (0x80000000000UL)
20cee16c	47	#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
1da177e4	48
800fc3ee DG	49	/*
	50	* Define the address range of the imalloc VM area.
	51	*/
	52	#define PHBS_IO_BASE VMALLOC_END
	53	#define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
	54	#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE)
	55
1da177e4	56	/*
3c726f8d BH	57	* Common bits in a linux-style PTE. These match the bits in the
	58	* (hardware-defined) PowerPC PTE as closely as possible. Additional
	59	* bits may be defined in pgtable-*.h
1da177e4 LT	60	*/
	61	#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
	62	#define _PAGE_USER 0x0002 /* matches one of the PP bits */
	63	#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
	64	#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
	65	#define _PAGE_GUARDED 0x0008
	66	#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
	67	#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
	68	#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
	69	#define _PAGE_DIRTY 0x0080 /* C: page changed */
	70	#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
	71	#define _PAGE_RW 0x0200 /* software: user write access allowed */
	72	#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
	73	#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
1da177e4 LT	74
	75	#define _PAGE_BASE (_PAGE_PRESENT \| _PAGE_ACCESSED \| _PAGE_COHERENT)
	76
	77	#define _PAGE_WRENABLE (_PAGE_RW \| _PAGE_DIRTY)
	78
	79	/* __pgprot defined in asm-ppc64/page.h */
	80	#define PAGE_NONE __pgprot(_PAGE_PRESENT \| _PAGE_ACCESSED)
	81
	82	#define PAGE_SHARED __pgprot(_PAGE_BASE \| _PAGE_RW \| _PAGE_USER)
	83	#define PAGE_SHARED_X __pgprot(_PAGE_BASE \| _PAGE_RW \| _PAGE_USER \| _PAGE_EXEC)
	84	#define PAGE_COPY __pgprot(_PAGE_BASE \| _PAGE_USER)
	85	#define PAGE_COPY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
	86	#define PAGE_READONLY __pgprot(_PAGE_BASE \| _PAGE_USER)
	87	#define PAGE_READONLY_X __pgprot(_PAGE_BASE \| _PAGE_USER \| _PAGE_EXEC)
	88	#define PAGE_KERNEL __pgprot(_PAGE_BASE \| _PAGE_WRENABLE)
	89	#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT \| _PAGE_ACCESSED \| \
	90	_PAGE_WRENABLE \| _PAGE_NO_CACHE \| _PAGE_GUARDED)
	91	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE \| _PAGE_WRENABLE \| _PAGE_EXEC)
	92
	93	#define PAGE_AGP __pgprot(_PAGE_BASE \| _PAGE_WRENABLE \| _PAGE_NO_CACHE)
	94	#define HAVE_PAGE_AGP
	95
3c726f8d BH	96	/* PTEIDX nibble */
	97	#define _PTEIDX_SECONDARY 0x8
	98	#define _PTEIDX_GROUP_IX 0x7
	99
1da177e4 LT	100
	101	/*
	102	* POWER4 and newer have per page execute protection, older chips can only
	103	* do this on a segment (256MB) basis.
	104	*
	105	* Also, write permissions imply read permissions.
	106	* This is the closest we can get..
	107	*
	108	* Note due to the way vm flags are laid out, the bits are XWR
	109	*/
	110	#define __P000 PAGE_NONE
	111	#define __P001 PAGE_READONLY
	112	#define __P010 PAGE_COPY
	113	#define __P011 PAGE_COPY
	114	#define __P100 PAGE_READONLY_X
	115	#define __P101 PAGE_READONLY_X
	116	#define __P110 PAGE_COPY_X
	117	#define __P111 PAGE_COPY_X
	118
	119	#define __S000 PAGE_NONE
	120	#define __S001 PAGE_READONLY
	121	#define __S010 PAGE_SHARED
	122	#define __S011 PAGE_SHARED
	123	#define __S100 PAGE_READONLY_X
	124	#define __S101 PAGE_READONLY_X
	125	#define __S110 PAGE_SHARED_X
	126	#define __S111 PAGE_SHARED_X
	127
	128	#ifndef __ASSEMBLY__
	129
	130	/*
	131	* ZERO_PAGE is a global shared page that is always zero: used
	132	* for zero-mapped memory areas etc..
	133	*/
	134	extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
	135	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	136	#endif /* __ASSEMBLY__ */
	137
1da177e4 LT	138	#ifdef CONFIG_HUGETLB_PAGE
1da177e4 LT	139
1da177e4 LT	140	#define HAVE_ARCH_UNMAPPED_AREA
1da177e4 LT	141	#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1da177e4 LT	142
	143	#endif
	144
	145	#ifndef __ASSEMBLY__
	146
	147	/*
	148	* Conversion functions: convert a page and protection to a page entry,
	149	* and a page entry and page directory to the page they refer to.
	150	*
	151	* mk_pte takes a (struct page *) as input
	152	*/
	153	#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
	154
1f8d419e DG	155	static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
	156	{
	157	pte_t pte;
	158
	159
3c726f8d	160	pte_val(pte) = (pfn << PTE_RPN_SHIFT) \| pgprot_val(pgprot);
1f8d419e DG	161	return pte;
1f8d419e DG	162	}
1da177e4 LT	163
	164	#define pte_modify(_pte, newprot) \
	165	(__pte((pte_val(_pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot)))
	166
	167	#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
	168	#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
	169
	170	/* pte_clear moved to later in this file */
	171
3c726f8d	172	#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
1da177e4 LT	173	#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 LT	174
3c726f8d	175	#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
1da177e4 LT	176	#define pmd_none(pmd) (!pmd_val(pmd))
	177	#define pmd_bad(pmd) (pmd_val(pmd) == 0)
	178	#define pmd_present(pmd) (pmd_val(pmd) != 0)
	179	#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
3c726f8d	180	#define pmd_page_kernel(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
1da177e4	181	#define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd))
58366af5	182
3c726f8d	183	#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
58366af5	184	#define pud_none(pud) (!pud_val(pud))
e28f7faf DG	185	#define pud_bad(pud) ((pud_val(pud)) == 0)
	186	#define pud_present(pud) (pud_val(pud) != 0)
	187	#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
3c726f8d	188	#define pud_page(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
e28f7faf DG	189
e28f7faf DG	190	#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
1da177e4 LT	191
	192	/*
	193	* Find an entry in a page-table-directory. We combine the address region
	194	* (the high order N bits) and the pgd portion of the address.
	195	*/
	196	/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
e28f7faf	197	#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
1da177e4 LT	198
	199	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	200
58366af5	201	#define pmd_offset(pudp,addr) \
e28f7faf	202	(((pmd_t ) pud_page((pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
1da177e4	203
1da177e4	204	#define pte_offset_kernel(dir,addr) \
e28f7faf	205	(((pte_t ) pmd_page_kernel((dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
1da177e4 LT	206
	207	#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
	208	#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
	209	#define pte_unmap(pte) do { } while(0)
	210	#define pte_unmap_nested(pte) do { } while(0)
	211
	212	/* to find an entry in a kernel page-table-directory */
	213	/* This now only contains the vmalloc pages */
	214	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	215
1da177e4 LT	216	/*
	217	* The following only work if pte_present() is true.
	218	* Undefined behaviour if not..
	219	*/
	220	static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;}
	221	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
	222	static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;}
	223	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
	224	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
	225	static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
1da177e4 LT	226
	227	static inline void pte_uncache(pte_t pte) { pte_val(pte) \|= _PAGE_NO_CACHE; }
	228	static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
	229
	230	static inline pte_t pte_rdprotect(pte_t pte) {
	231	pte_val(pte) &= ~_PAGE_USER; return pte; }
	232	static inline pte_t pte_exprotect(pte_t pte) {
	233	pte_val(pte) &= ~_PAGE_EXEC; return pte; }
	234	static inline pte_t pte_wrprotect(pte_t pte) {
	235	pte_val(pte) &= ~(_PAGE_RW); return pte; }
	236	static inline pte_t pte_mkclean(pte_t pte) {
	237	pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
	238	static inline pte_t pte_mkold(pte_t pte) {
	239	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
1da177e4 LT	240	static inline pte_t pte_mkread(pte_t pte) {
	241	pte_val(pte) \|= _PAGE_USER; return pte; }
	242	static inline pte_t pte_mkexec(pte_t pte) {
	243	pte_val(pte) \|= _PAGE_USER \| _PAGE_EXEC; return pte; }
	244	static inline pte_t pte_mkwrite(pte_t pte) {
	245	pte_val(pte) \|= _PAGE_RW; return pte; }
	246	static inline pte_t pte_mkdirty(pte_t pte) {
	247	pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	248	static inline pte_t pte_mkyoung(pte_t pte) {
	249	pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
	250	static inline pte_t pte_mkhuge(pte_t pte) {
3c726f8d	251	return pte; }
1da177e4 LT	252
	253	/* Atomic PTE updates */
	254	static inline unsigned long pte_update(pte_t *p, unsigned long clr)
	255	{
	256	unsigned long old, tmp;
	257
	258	__asm__ __volatile__(
	259	"1: ldarx %0,0,%3 # pte_update\n\
	260	andi. %1,%0,%6\n\
	261	bne- 1b \n\
	262	andc %1,%0,%4 \n\
	263	stdcx. %1,0,%3 \n\
	264	bne- 1b"
	265	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	266	: "r" (p), "r" (clr), "m" (*p), "i" (_PAGE_BUSY)
	267	: "cc" );
	268	return old;
	269	}
	270
	271	/* PTE updating functions, this function puts the PTE in the
	272	* batch, doesn't actually triggers the hash flush immediately,
	273	* you need to call flush_tlb_pending() to do that.
3c726f8d	274	* Pass -1 for "normal" size (4K or 64K)
1da177e4	275	*/
3c726f8d BH	276	extern void hpte_update(struct mm_struct *mm, unsigned long addr,
3c726f8d BH	277	pte_t *ptep, unsigned long pte, int huge);
1da177e4	278
3c726f8d BH	279	static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
3c726f8d BH	280	unsigned long addr, pte_t *ptep)
1da177e4 LT	281	{
	282	unsigned long old;
	283
	284	if ((pte_val(*ptep) & (_PAGE_ACCESSED \| _PAGE_HASHPTE)) == 0)
	285	return 0;
	286	old = pte_update(ptep, _PAGE_ACCESSED);
	287	if (old & _PAGE_HASHPTE) {
3c726f8d	288	hpte_update(mm, addr, ptep, old, 0);
1da177e4 LT	289	flush_tlb_pending();
	290	}
	291	return (old & _PAGE_ACCESSED) != 0;
	292	}
	293	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	294	#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	295	({ \
	296	int __r; \
	297	__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
	298	__r; \
	299	})
	300
	301	/*
	302	* On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
	303	* moment we always flush but we need to fix hpte_update and test if the
	304	* optimisation is worth it.
	305	*/
3c726f8d BH	306	static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
3c726f8d BH	307	unsigned long addr, pte_t *ptep)
1da177e4 LT	308	{
	309	unsigned long old;
	310
	311	if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
	312	return 0;
	313	old = pte_update(ptep, _PAGE_DIRTY);
	314	if (old & _PAGE_HASHPTE)
3c726f8d	315	hpte_update(mm, addr, ptep, old, 0);
1da177e4 LT	316	return (old & _PAGE_DIRTY) != 0;
	317	}
	318	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
	319	#define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \
	320	({ \
	321	int __r; \
	322	__r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
	323	__r; \
	324	})
	325
	326	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
3c726f8d BH	327	static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
3c726f8d BH	328	pte_t *ptep)
1da177e4 LT	329	{
	330	unsigned long old;
	331
	332	if ((pte_val(*ptep) & _PAGE_RW) == 0)
	333	return;
	334	old = pte_update(ptep, _PAGE_RW);
	335	if (old & _PAGE_HASHPTE)
3c726f8d	336	hpte_update(mm, addr, ptep, old, 0);
1da177e4 LT	337	}
	338
	339	/*
	340	* We currently remove entries from the hashtable regardless of whether
	341	* the entry was young or dirty. The generic routines only flush if the
	342	* entry was young or dirty which is not good enough.
	343	*
	344	* We should be more intelligent about this but for the moment we override
	345	* these functions and force a tlb flush unconditionally
	346	*/
	347	#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
	348	#define ptep_clear_flush_young(__vma, __address, __ptep) \
	349	({ \
	350	int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
	351	__ptep); \
	352	__young; \
	353	})
	354
	355	#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
	356	#define ptep_clear_flush_dirty(__vma, __address, __ptep) \
	357	({ \
	358	int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
	359	__ptep); \
	360	flush_tlb_page(__vma, __address); \
	361	__dirty; \
	362	})
	363
	364	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
3c726f8d BH	365	static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
3c726f8d BH	366	unsigned long addr, pte_t *ptep)
1da177e4 LT	367	{
	368	unsigned long old = pte_update(ptep, ~0UL);
	369
	370	if (old & _PAGE_HASHPTE)
3c726f8d	371	hpte_update(mm, addr, ptep, old, 0);
1da177e4 LT	372	return __pte(old);
	373	}
	374
3c726f8d BH	375	static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
3c726f8d BH	376	pte_t * ptep)
1da177e4 LT	377	{
	378	unsigned long old = pte_update(ptep, ~0UL);
	379
	380	if (old & _PAGE_HASHPTE)
3c726f8d	381	hpte_update(mm, addr, ptep, old, 0);
1da177e4 LT	382	}
	383
	384	/*
	385	* set_pte stores a linux PTE into the linux page table.
	386	*/
	387	static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
	388	pte_t *ptep, pte_t pte)
	389	{
	390	if (pte_present(*ptep)) {
	391	pte_clear(mm, addr, ptep);
	392	flush_tlb_pending();
	393	}
3c726f8d BH	394	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
	395
	396	#ifdef CONFIG_PPC_64K_PAGES
	397	if (mmu_virtual_psize != MMU_PAGE_64K)
	398	pte = __pte(pte_val(pte) \| _PAGE_COMBO);
	399	#endif /* CONFIG_PPC_64K_PAGES */
	400
	401	*ptep = pte;
1da177e4 LT	402	}
	403
	404	/* Set the dirty and/or accessed bits atomically in a linux PTE, this
	405	* function doesn't need to flush the hash entry
	406	*/
	407	#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
	408	static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
	409	{
	410	unsigned long bits = pte_val(entry) &
	411	(_PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_RW \| _PAGE_EXEC);
	412	unsigned long old, tmp;
	413
	414	__asm__ __volatile__(
	415	"1: ldarx %0,0,%4\n\
	416	andi. %1,%0,%6\n\
	417	bne- 1b \n\
	418	or %0,%3,%0\n\
	419	stdcx. %0,0,%4\n\
	420	bne- 1b"
	421	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
	422	:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
	423	:"cc");
	424	}
	425	#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
	426	do { \
	427	__ptep_set_access_flags(__ptep, __entry, __dirty); \
	428	flush_tlb_page_nohash(__vma, __address); \
	429	} while(0)
	430
	431	/*
	432	* Macro to mark a page protection value as "uncacheable".
	433	*/
	434	#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) \| _PAGE_NO_CACHE \| _PAGE_GUARDED))
	435
	436	struct file;
8b150478	437	extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
1da177e4 LT	438	unsigned long size, pgprot_t vma_prot);
	439	#define __HAVE_PHYS_MEM_ACCESS_PROT
	440
	441	#define __HAVE_ARCH_PTE_SAME
	442	#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
	443
65500d23 HD	444	#define pte_ERROR(e) \
65500d23 HD	445	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
1da177e4	446	#define pmd_ERROR(e) \
e28f7faf	447	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
1da177e4	448	#define pgd_ERROR(e) \
e28f7faf	449	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1da177e4	450
1f8d419e	451	extern pgd_t swapper_pg_dir[];
1da177e4 LT	452
	453	extern void paging_init(void);
	454
b74d0bd5	455	#ifdef CONFIG_HUGETLB_PAGE
3bf5ee95	456	#define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
e28f7faf	457	free_pgd_range(tlb, addr, end, floor, ceiling)
b74d0bd5	458	#endif
1da177e4 LT	459
	460	/*
	461	* This gets called at the end of handling a page fault, when
	462	* the kernel has put a new PTE into the page table for the process.
	463	* We use it to put a corresponding HPTE into the hash table
	464	* ahead of time, instead of waiting for the inevitable extra
	465	* hash-table miss exception.
	466	*/
	467	struct vm_area_struct;
	468	extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
	469
	470	/* Encode and de-code a swap entry */
	471	#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
	472	#define __swp_offset(entry) ((entry).val >> 8)
3c726f8d BH	473	#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)\|((offset)<<8)})
	474	#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
	475	#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
	476	#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
	477	#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)\|_PAGE_FILE})
	478	#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
1da177e4 LT	479
	480	/*
	481	* kern_addr_valid is intended to indicate whether an address is a valid
	482	* kernel address. Most 32-bit archs define it as always true (like this)
	483	* but most 64-bit archs actually perform a test. What should we do here?
	484	* The only use is in fs/ncpfs/dir.c
	485	*/
	486	#define kern_addr_valid(addr) (1)
	487
1da177e4 LT	488	#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
	489	remap_pfn_range(vma, vaddr, pfn, size, prot)
	490
1da177e4 LT	491	void pgtable_cache_init(void);
1da177e4 LT	492
1da177e4 LT	493	/*
	494	* find_linux_pte returns the address of a linux pte for a given
	495	* effective address and directory. If not found, it returns zero.
3c726f8d	496	/static inline pte_t find_linux_pte(pgd_t *pgdir, unsigned long ea)
1da177e4 LT	497	{
1da177e4 LT	498	pgd_t *pg;
58366af5	499	pud_t *pu;
1da177e4 LT	500	pmd_t *pm;
1da177e4 LT	501	pte_t *pt = NULL;
1da177e4 LT	502
	503	pg = pgdir + pgd_index(ea);
	504	if (!pgd_none(*pg)) {
58366af5 BH	505	pu = pud_offset(pg, ea);
	506	if (!pud_none(*pu)) {
	507	pm = pmd_offset(pu, ea);
3c726f8d	508	if (pmd_present(*pm))
58366af5	509	pt = pte_offset_kernel(pm, ea);
1da177e4 LT	510	}
1da177e4 LT	511	}
1da177e4 LT	512	return pt;
	513	}
	514
	515	#include <asm-generic/pgtable.h>
	516
	517	#endif /* __ASSEMBLY__ */
	518
	519	#endif /* _PPC64_PGTABLE_H */