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1da177e4 LT |
1 | /* |
2 | * arch/ppc64/kernel/ppc_asm.h | |
3 | * | |
4 | * Definitions used by various bits of low-level assembly code on PowerPC. | |
5 | * | |
6 | * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #ifndef _PPC64_PPC_ASM_H | |
15 | #define _PPC64_PPC_ASM_H | |
16 | /* | |
17 | * Macros for storing registers into and loading registers from | |
18 | * exception frames. | |
19 | */ | |
20 | #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) | |
21 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) | |
22 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) | |
23 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) | |
24 | #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) | |
25 | #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) | |
26 | #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) | |
27 | #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) | |
28 | #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) | |
29 | #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) | |
30 | ||
31 | #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) | |
32 | #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) | |
33 | ||
34 | #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) | |
35 | #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) | |
36 | #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) | |
37 | #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) | |
38 | #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) | |
39 | #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) | |
40 | #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) | |
41 | #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) | |
42 | #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) | |
43 | #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) | |
44 | #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) | |
45 | #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) | |
46 | ||
47 | #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base | |
48 | #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) | |
49 | #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) | |
50 | #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) | |
51 | #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) | |
52 | #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) | |
53 | #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base | |
54 | #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) | |
55 | #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) | |
56 | #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) | |
57 | #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) | |
58 | #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) | |
59 | ||
60 | /* Macros to adjust thread priority for Iseries hardware multithreading */ | |
61 | #define HMT_LOW or 1,1,1 | |
62 | #define HMT_MEDIUM or 2,2,2 | |
63 | #define HMT_HIGH or 3,3,3 | |
64 | ||
65 | /* Insert the high 32 bits of the MSR into what will be the new | |
66 | MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF | |
67 | bits. */ | |
68 | ||
69 | #define FIX_SRR1(ra, rb) \ | |
70 | mr rb,ra; \ | |
71 | mfmsr ra; \ | |
72 | rldimi ra,rb,0,32 | |
73 | ||
74 | #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */ | |
75 | ||
76 | /* | |
77 | * LOADADDR( rn, name ) | |
78 | * loads the address of 'name' into 'rn' | |
79 | * | |
80 | * LOADBASE( rn, name ) | |
81 | * loads the address (less the low 16 bits) of 'name' into 'rn' | |
82 | * suitable for base+disp addressing | |
83 | */ | |
84 | #define LOADADDR(rn,name) \ | |
85 | lis rn,name##@highest; \ | |
86 | ori rn,rn,name##@higher; \ | |
87 | rldicr rn,rn,32,31; \ | |
88 | oris rn,rn,name##@h; \ | |
89 | ori rn,rn,name##@l | |
90 | ||
91 | #define LOADBASE(rn,name) \ | |
92 | lis rn,name@highest; \ | |
93 | ori rn,rn,name@higher; \ | |
94 | rldicr rn,rn,32,31; \ | |
95 | oris rn,rn,name@ha | |
96 | ||
97 | ||
98 | #define SET_REG_TO_CONST(reg, value) \ | |
99 | lis reg,(((value)>>48)&0xFFFF); \ | |
100 | ori reg,reg,(((value)>>32)&0xFFFF); \ | |
101 | rldicr reg,reg,32,31; \ | |
102 | oris reg,reg,(((value)>>16)&0xFFFF); \ | |
103 | ori reg,reg,((value)&0xFFFF); | |
104 | ||
105 | #define SET_REG_TO_LABEL(reg, label) \ | |
106 | lis reg,(label)@highest; \ | |
107 | ori reg,reg,(label)@higher; \ | |
108 | rldicr reg,reg,32,31; \ | |
109 | oris reg,reg,(label)@h; \ | |
110 | ori reg,reg,(label)@l; | |
111 | ||
112 | ||
113 | /* PPPBBB - DRENG If KERNELBASE is always 0xC0..., | |
114 | * Then we can easily do this with one asm insn. -Peter | |
115 | */ | |
116 | #define tophys(rd,rs) \ | |
117 | lis rd,((KERNELBASE>>48)&0xFFFF); \ | |
118 | rldicr rd,rd,32,31; \ | |
119 | sub rd,rs,rd | |
120 | ||
121 | #define tovirt(rd,rs) \ | |
122 | lis rd,((KERNELBASE>>48)&0xFFFF); \ | |
123 | rldicr rd,rd,32,31; \ | |
124 | add rd,rs,rd | |
125 | ||
126 | /* Condition Register Bit Fields */ | |
127 | ||
128 | #define cr0 0 | |
129 | #define cr1 1 | |
130 | #define cr2 2 | |
131 | #define cr3 3 | |
132 | #define cr4 4 | |
133 | #define cr5 5 | |
134 | #define cr6 6 | |
135 | #define cr7 7 | |
136 | ||
137 | ||
138 | /* General Purpose Registers (GPRs) */ | |
139 | ||
140 | #define r0 0 | |
141 | #define r1 1 | |
142 | #define r2 2 | |
143 | #define r3 3 | |
144 | #define r4 4 | |
145 | #define r5 5 | |
146 | #define r6 6 | |
147 | #define r7 7 | |
148 | #define r8 8 | |
149 | #define r9 9 | |
150 | #define r10 10 | |
151 | #define r11 11 | |
152 | #define r12 12 | |
153 | #define r13 13 | |
154 | #define r14 14 | |
155 | #define r15 15 | |
156 | #define r16 16 | |
157 | #define r17 17 | |
158 | #define r18 18 | |
159 | #define r19 19 | |
160 | #define r20 20 | |
161 | #define r21 21 | |
162 | #define r22 22 | |
163 | #define r23 23 | |
164 | #define r24 24 | |
165 | #define r25 25 | |
166 | #define r26 26 | |
167 | #define r27 27 | |
168 | #define r28 28 | |
169 | #define r29 29 | |
170 | #define r30 30 | |
171 | #define r31 31 | |
172 | ||
173 | ||
174 | /* Floating Point Registers (FPRs) */ | |
175 | ||
176 | #define fr0 0 | |
177 | #define fr1 1 | |
178 | #define fr2 2 | |
179 | #define fr3 3 | |
180 | #define fr4 4 | |
181 | #define fr5 5 | |
182 | #define fr6 6 | |
183 | #define fr7 7 | |
184 | #define fr8 8 | |
185 | #define fr9 9 | |
186 | #define fr10 10 | |
187 | #define fr11 11 | |
188 | #define fr12 12 | |
189 | #define fr13 13 | |
190 | #define fr14 14 | |
191 | #define fr15 15 | |
192 | #define fr16 16 | |
193 | #define fr17 17 | |
194 | #define fr18 18 | |
195 | #define fr19 19 | |
196 | #define fr20 20 | |
197 | #define fr21 21 | |
198 | #define fr22 22 | |
199 | #define fr23 23 | |
200 | #define fr24 24 | |
201 | #define fr25 25 | |
202 | #define fr26 26 | |
203 | #define fr27 27 | |
204 | #define fr28 28 | |
205 | #define fr29 29 | |
206 | #define fr30 30 | |
207 | #define fr31 31 | |
208 | ||
209 | #define vr0 0 | |
210 | #define vr1 1 | |
211 | #define vr2 2 | |
212 | #define vr3 3 | |
213 | #define vr4 4 | |
214 | #define vr5 5 | |
215 | #define vr6 6 | |
216 | #define vr7 7 | |
217 | #define vr8 8 | |
218 | #define vr9 9 | |
219 | #define vr10 10 | |
220 | #define vr11 11 | |
221 | #define vr12 12 | |
222 | #define vr13 13 | |
223 | #define vr14 14 | |
224 | #define vr15 15 | |
225 | #define vr16 16 | |
226 | #define vr17 17 | |
227 | #define vr18 18 | |
228 | #define vr19 19 | |
229 | #define vr20 20 | |
230 | #define vr21 21 | |
231 | #define vr22 22 | |
232 | #define vr23 23 | |
233 | #define vr24 24 | |
234 | #define vr25 25 | |
235 | #define vr26 26 | |
236 | #define vr27 27 | |
237 | #define vr28 28 | |
238 | #define vr29 29 | |
239 | #define vr30 30 | |
240 | #define vr31 31 | |
241 | ||
242 | #endif /* _PPC64_PPC_ASM_H */ |