[deliverable/linux.git] / include / asm-s390 / smp.h

/*
 *  include/asm-s390/smp.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *               Heiko Carstens (heiko.carstens@de.ibm.com)
 */
#ifndef __ASM_SMP_H
#define __ASM_SMP_H

#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/bitops.h>

#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)

#include <asm/lowcore.h>
#include <asm/sigp.h>
#include <asm/ptrace.h>

/*
  s390 specific smp.c headers
 */
typedef struct
{
	int        intresting;
	sigp_ccode ccode; 
	__u32      status;
	__u16      cpu;
} sigp_info;

extern void machine_restart_smp(char *);
extern void machine_halt_smp(void);
extern void machine_power_off_smp(void);

#define NO_PROC_ID		0xFF		/* No processor magic marker */

/*
 *	This magic constant controls our willingness to transfer
 *	a process across CPUs. Such a transfer incurs misses on the L1
 *	cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
 *	gut feeling is this will vary by board in value. For a board
 *	with separate L2 cache it probably depends also on the RSS, and
 *	for a board with shared L2 cache it ought to decay fast as other
 *	processes are run.
 */
 
#define PROC_CHANGE_PENALTY	20		/* Schedule penalty */

#define raw_smp_processor_id()	(S390_lowcore.cpu_data.cpu_nr)

static inline __u16 hard_smp_processor_id(void)
{
        __u16 cpu_address;
 
	asm volatile("stap %0" : "=m" (cpu_address));
        return cpu_address;
}

/*
 * returns 1 if cpu is in stopped/check stopped state or not operational
 * returns 0 otherwise
 */
static inline int
smp_cpu_not_running(int cpu)
{
	__u32 status;

	switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
	case sigp_order_code_accepted:
	case sigp_status_stored:
		/* Check for stopped and check stop state */
		if (status & 0x50)
			return 1;
		break;
	case sigp_not_operational:
		return 1;
	default:
		break;
	}
	return 0;
}

#define cpu_logical_map(cpu) (cpu)

extern int __cpu_disable (void);
extern void __cpu_die (unsigned int cpu);
extern void cpu_die (void) __attribute__ ((noreturn));
extern int __cpu_up (unsigned int cpu);

extern struct mutex smp_cpu_state_mutex;

extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
	void *info, int wait);
#endif

#ifndef CONFIG_SMP
static inline void smp_send_stop(void)
{
	/* Disable all interrupts/machine checks */
	__load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
}

#define hard_smp_processor_id()		0
#define smp_cpu_not_running(cpu)	1
#endif

extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-s390/smp.h
	3	*
	4	* S390 version
	5	* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
	6	* Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
	7	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	8	* Heiko Carstens (heiko.carstens@de.ibm.com)
	9	*/
	10	#ifndef __ASM_SMP_H
	11	#define __ASM_SMP_H
	12
1da177e4 LT	13	#include <linux/threads.h>
	14	#include <linux/cpumask.h>
	15	#include <linux/bitops.h>
	16
	17	#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
	18
	19	#include <asm/lowcore.h>
	20	#include <asm/sigp.h>
c6b5b847	21	#include <asm/ptrace.h>
1da177e4 LT	22
	23	/*
	24	s390 specific smp.c headers
	25	*/
	26	typedef struct
	27	{
	28	int intresting;
	29	sigp_ccode ccode;
	30	__u32 status;
	31	__u16 cpu;
	32	} sigp_info;
	33
2b67fc46 HC	34	extern void machine_restart_smp(char *);
	35	extern void machine_halt_smp(void);
	36	extern void machine_power_off_smp(void);
	37
1da177e4 LT	38	#define NO_PROC_ID 0xFF /* No processor magic marker */
	39
	40	/*
	41	* This magic constant controls our willingness to transfer
	42	* a process across CPUs. Such a transfer incurs misses on the L1
	43	* cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
	44	* gut feeling is this will vary by board in value. For a board
	45	* with separate L2 cache it probably depends also on the RSS, and
	46	* for a board with shared L2 cache it ought to decay fast as other
	47	* processes are run.
	48	*/
	49
	50	#define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
	51
39c715b7	52	#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
1da177e4	53
4448aaf0	54	static inline __u16 hard_smp_processor_id(void)
1da177e4 LT	55	{
	56	__u16 cpu_address;
	57
94c12cc7	58	asm volatile("stap %0" : "=m" (cpu_address));
1da177e4 LT	59	return cpu_address;
	60	}
	61
	62	/*
	63	* returns 1 if cpu is in stopped/check stopped state or not operational
	64	* returns 0 otherwise
	65	*/
	66	static inline int
	67	smp_cpu_not_running(int cpu)
	68	{
	69	__u32 status;
	70
	71	switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
	72	case sigp_order_code_accepted:
	73	case sigp_status_stored:
	74	/* Check for stopped and check stop state */
	75	if (status & 0x50)
	76	return 1;
	77	break;
	78	case sigp_not_operational:
	79	return 1;
	80	default:
	81	break;
	82	}
	83	return 0;
	84	}
	85
	86	#define cpu_logical_map(cpu) (cpu)
	87
	88	extern int __cpu_disable (void);
	89	extern void __cpu_die (unsigned int cpu);
	90	extern void cpu_die (void) __attribute__ ((noreturn));
	91	extern int __cpu_up (unsigned int cpu);
	92
dbd70fb4 HC	93	extern struct mutex smp_cpu_state_mutex;
dbd70fb4 HC	94
dab5209c CO	95	extern int smp_call_function_mask(cpumask_t mask, void (func)(void ),
dab5209c CO	96	void *info, int wait);
1da177e4 LT	97	#endif
	98
	99	#ifndef CONFIG_SMP
c6b5b847 HC	100	static inline void smp_send_stop(void)
	101	{
	102	/* Disable all interrupts/machine checks */
c1821c2e	103	__load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
c6b5b847 HC	104	}
c6b5b847 HC	105
2f4dfe20	106	#define hard_smp_processor_id() 0
a386fba2	107	#define smp_cpu_not_running(cpu) 1
1da177e4 LT	108	#endif
1da177e4 LT	109
411ed322	110	extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
1da177e4	111	#endif