projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | #ifndef __ASM_CPU_SH3_DMA_H |
| 2 | #define __ASM_CPU_SH3_DMA_H | |
| 3 | ||
| 3ea6bc3d | 4 | |
| 4f247e84 | 5 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 3ea6bc3d MB |
6 | #define SH_DMAC_BASE 0xa4010020 |
| 7 | ||
| 8 | #define DMTE0_IRQ 48 | |
| 9 | #define DMTE1_IRQ 49 | |
| 10 | #define DMTE2_IRQ 50 | |
| 11 | #define DMTE3_IRQ 51 | |
| 12 | #define DMTE4_IRQ 76 | |
| 13 | #define DMTE5_IRQ 77 | |
| 14 | ||
| 15 | #else | |
| 1da177e4 | 16 | #define SH_DMAC_BASE 0xa4000020 |
| 3ea6bc3d | 17 | #endif |
| 1da177e4 | 18 | |
| 0d831770 PM |
19 | /* Definitions for the SuperH DMAC */ |
| 20 | #define TM_BURST 0x00000020 | |
| 21 | #define TS_8 0x00000000 | |
| 22 | #define TS_16 0x00000008 | |
| 23 | #define TS_32 0x00000010 | |
| 24 | #define TS_128 0x00000018 | |
| 25 | ||
| 26 | #define CHCR_TS_MASK 0x18 | |
| 27 | #define CHCR_TS_SHIFT 3 | |
| 28 | ||
| 29 | #define DMAOR_INIT DMAOR_DME | |
| 1da177e4 | 30 | |
| 0d831770 PM |
31 | /* |
| 32 | * The SuperH DMAC supports a number of transmit sizes, we list them here, | |
| 33 | * with their respective values as they appear in the CHCR registers. | |
| 34 | */ | |
| 35 | enum { | |
| 36 | XMIT_SZ_8BIT, | |
| 37 | XMIT_SZ_16BIT, | |
| 38 | XMIT_SZ_32BIT, | |
| 39 | XMIT_SZ_128BIT, | |
| 40 | }; | |
| 41 | ||
| d16aaffa | 42 | static unsigned int ts_shift[] __maybe_unused = { |
| 0d831770 PM |
43 | [XMIT_SZ_8BIT] = 0, |
| 44 | [XMIT_SZ_16BIT] = 1, | |
| 45 | [XMIT_SZ_32BIT] = 2, | |
| 46 | [XMIT_SZ_128BIT] = 4, | |
| 47 | }; | |
| 48 | ||
| 49 | #endif /* __ASM_CPU_SH3_DMA_H */ |