projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a23ba435 PM |
1 | #ifndef __ASM_SH_CPU_SH5_IRQ_H |
| 2 | #define __ASM_SH_CPU_SH5_IRQ_H | |
| 1da177e4 LT |
3 | |
| 4 | /* | |
| a23ba435 | 5 | * include/asm-sh/cpu-sh5/irq.h |
| 1da177e4 LT |
6 | * |
| 7 | * Copyright (C) 2000, 2001 Paolo Alberelli | |
| 8 | * | |
| a23ba435 PM |
9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive | |
| 11 | * for more details. | |
| 1da177e4 LT |
12 | */ |
| 13 | ||
| 1da177e4 LT |
14 | |
| 15 | /* | |
| 16 | * Encoded IRQs are not considered worth to be supported. | |
| 17 | * Main reason is that there's no per-encoded-interrupt | |
| 18 | * enable/disable mechanism (as there was in SH3/4). | |
| 19 | * An all enabled/all disabled is worth only if there's | |
| 20 | * a cascaded IC to disable/enable/ack on. Until such | |
| 21 | * IC is available there's no such support. | |
| 22 | * | |
| 23 | * Presumably Encoded IRQs may use extra IRQs beyond 64, | |
| 24 | * below. Some logic must be added to cope with IRQ_IRL? | |
| 25 | * in an exclusive way. | |
| 26 | * | |
| 27 | * Priorities are set at Platform level, when IRQ_IRL0-3 | |
| 28 | * are set to 0 Encoding is allowed. Otherwise it's not | |
| 29 | * allowed. | |
| 30 | */ | |
| 31 | ||
| 32 | /* Independent IRQs */ | |
| 33 | #define IRQ_IRL0 0 | |
| 34 | #define IRQ_IRL1 1 | |
| 35 | #define IRQ_IRL2 2 | |
| 36 | #define IRQ_IRL3 3 | |
| 37 | ||
| 38 | #define IRQ_INTA 4 | |
| 39 | #define IRQ_INTB 5 | |
| 40 | #define IRQ_INTC 6 | |
| 41 | #define IRQ_INTD 7 | |
| 42 | ||
| 43 | #define IRQ_SERR 12 | |
| 44 | #define IRQ_ERR 13 | |
| 45 | #define IRQ_PWR3 14 | |
| 46 | #define IRQ_PWR2 15 | |
| 47 | #define IRQ_PWR1 16 | |
| 48 | #define IRQ_PWR0 17 | |
| 49 | ||
| 50 | #define IRQ_DMTE0 18 | |
| 51 | #define IRQ_DMTE1 19 | |
| 52 | #define IRQ_DMTE2 20 | |
| 53 | #define IRQ_DMTE3 21 | |
| 54 | #define IRQ_DAERR 22 | |
| 55 | ||
| 56 | #define IRQ_TUNI0 32 | |
| 57 | #define IRQ_TUNI1 33 | |
| 58 | #define IRQ_TUNI2 34 | |
| 59 | #define IRQ_TICPI2 35 | |
| 60 | ||
| 61 | #define IRQ_ATI 36 | |
| 62 | #define IRQ_PRI 37 | |
| 63 | #define IRQ_CUI 38 | |
| 64 | ||
| 65 | #define IRQ_ERI 39 | |
| 66 | #define IRQ_RXI 40 | |
| 67 | #define IRQ_BRI 41 | |
| 68 | #define IRQ_TXI 42 | |
| 69 | ||
| 70 | #define IRQ_ITI 63 | |
| 71 | ||
| 72 | #define NR_INTC_IRQS 64 | |
| 73 | ||
| 74 | #ifdef CONFIG_SH_CAYMAN | |
| 75 | #define NR_EXT_IRQS 32 | |
| 76 | #define START_EXT_IRQS 64 | |
| 77 | ||
| 78 | /* PCI bus 2 uses encoded external interrupts on the Cayman board */ | |
| 79 | #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0) | |
| 80 | #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1) | |
| 81 | #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2) | |
| 82 | #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3) | |
| 83 | ||
| 84 | #define I8042_KBD_IRQ (START_EXT_IRQS + 2) | |
| 85 | #define I8042_AUX_IRQ (START_EXT_IRQS + 6) | |
| 86 | ||
| 87 | #define IRQ_CFCARD (START_EXT_IRQS + 7) | |
| 88 | #define IRQ_PCMCIA (0) | |
| 89 | ||
| 90 | #else | |
| 91 | #define NR_EXT_IRQS 0 | |
| 92 | #endif | |
| 93 | ||
| 1da177e4 LT |
94 | /* Default IRQs, fixed */ |
| 95 | #define TIMER_IRQ IRQ_TUNI0 | |
| 96 | #define RTC_IRQ IRQ_CUI | |
| 97 | ||
| 98 | /* Default Priorities, Platform may choose differently */ | |
| 99 | #define NO_PRIORITY 0 /* Disabled */ | |
| 100 | #define TIMER_PRIORITY 2 | |
| 101 | #define RTC_PRIORITY TIMER_PRIORITY | |
| 102 | #define SCIF_PRIORITY 3 | |
| 103 | #define INTD_PRIORITY 3 | |
| 104 | #define IRL3_PRIORITY 4 | |
| 105 | #define INTC_PRIORITY 6 | |
| 106 | #define IRL2_PRIORITY 7 | |
| 107 | #define INTB_PRIORITY 9 | |
| 108 | #define IRL1_PRIORITY 10 | |
| 109 | #define INTA_PRIORITY 12 | |
| 110 | #define IRL0_PRIORITY 13 | |
| 111 | #define TOP_PRIORITY 15 | |
| 112 | ||
| 1da177e4 LT |
113 | extern int intc_evt_to_irq[(0xE20/0x20)+1]; |
| 114 | int intc_irq_describe(char* p, int irq); | |
| 18bc8131 | 115 | extern int platform_int_priority[NR_INTC_IRQS]; |
| 1da177e4 | 116 | |
| a23ba435 | 117 | #endif /* __ASM_SH_CPU_SH5_IRQ_H */ |