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1da177e4 LT |
1 | /* |
2 | * include/asm-sh/dma.h | |
3 | * | |
4 | * Copyright (C) 2003, 2004 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #ifndef __ASM_SH_DMA_H | |
11 | #define __ASM_SH_DMA_H | |
12 | #ifdef __KERNEL__ | |
13 | ||
1da177e4 LT |
14 | #include <linux/spinlock.h> |
15 | #include <linux/wait.h> | |
16 | #include <linux/sysdev.h> | |
17 | #include <asm/cpu/dma.h> | |
1da177e4 LT |
18 | |
19 | /* The maximum address that we can perform a DMA transfer to on this platform */ | |
20 | /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any | |
21 | occurrence should be flagged as an error. */ | |
22 | /* But... */ | |
23 | /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */ | |
24 | #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) | |
25 | ||
26 | #ifdef CONFIG_NR_DMA_CHANNELS | |
27 | # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) | |
28 | #else | |
29 | # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * Read and write modes can mean drastically different things depending on the | |
34 | * channel configuration. Consult your DMAC documentation and module | |
35 | * implementation for further clues. | |
36 | */ | |
37 | #define DMA_MODE_READ 0x00 | |
38 | #define DMA_MODE_WRITE 0x01 | |
39 | #define DMA_MODE_MASK 0x01 | |
40 | ||
41 | #define DMA_AUTOINIT 0x10 | |
42 | ||
43 | /* | |
44 | * DMAC (dma_info) flags | |
45 | */ | |
46 | enum { | |
db9b99d4 MG |
47 | DMAC_CHANNELS_CONFIGURED = 0x01, |
48 | DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */ | |
1da177e4 LT |
49 | }; |
50 | ||
51 | /* | |
52 | * DMA channel capabilities / flags | |
53 | */ | |
54 | enum { | |
db9b99d4 MG |
55 | DMA_CONFIGURED = 0x01, |
56 | ||
57 | /* | |
58 | * Transfer end interrupt, inherited from DMAC. | |
59 | * wait_queue used in dma_wait_for_completion. | |
60 | */ | |
61 | DMA_TEI_CAPABLE = 0x02, | |
1da177e4 LT |
62 | }; |
63 | ||
64 | extern spinlock_t dma_spin_lock; | |
65 | ||
66 | struct dma_channel; | |
67 | ||
68 | struct dma_ops { | |
69 | int (*request)(struct dma_channel *chan); | |
70 | void (*free)(struct dma_channel *chan); | |
71 | ||
72 | int (*get_residue)(struct dma_channel *chan); | |
73 | int (*xfer)(struct dma_channel *chan); | |
db9b99d4 MG |
74 | int (*configure)(struct dma_channel *chan, unsigned long flags); |
75 | int (*extend)(struct dma_channel *chan, unsigned long op, void *param); | |
1da177e4 LT |
76 | }; |
77 | ||
78 | struct dma_channel { | |
db9b99d4 | 79 | char dev_id[16]; /* unique name per DMAC of channel */ |
1da177e4 | 80 | |
db9b99d4 | 81 | unsigned int chan; /* DMAC channel number */ |
0d831770 | 82 | unsigned int vchan; /* Virtual channel number */ |
db9b99d4 | 83 | |
1da177e4 LT |
84 | unsigned int mode; |
85 | unsigned int count; | |
86 | ||
87 | unsigned long sar; | |
88 | unsigned long dar; | |
89 | ||
db9b99d4 MG |
90 | const char **caps; |
91 | ||
1da177e4 LT |
92 | unsigned long flags; |
93 | atomic_t busy; | |
94 | ||
1da177e4 LT |
95 | wait_queue_head_t wait_queue; |
96 | ||
97 | struct sys_device dev; | |
db9b99d4 | 98 | void *priv_data; |
1da177e4 LT |
99 | }; |
100 | ||
101 | struct dma_info { | |
0d831770 PM |
102 | struct platform_device *pdev; |
103 | ||
1da177e4 LT |
104 | const char *name; |
105 | unsigned int nr_channels; | |
106 | unsigned long flags; | |
107 | ||
108 | struct dma_ops *ops; | |
109 | struct dma_channel *channels; | |
110 | ||
111 | struct list_head list; | |
db9b99d4 MG |
112 | int first_channel_nr; |
113 | }; | |
114 | ||
115 | struct dma_chan_caps { | |
116 | int ch_num; | |
117 | const char **caplist; | |
1da177e4 LT |
118 | }; |
119 | ||
120 | #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev) | |
121 | ||
122 | /* arch/sh/drivers/dma/dma-api.c */ | |
123 | extern int dma_xfer(unsigned int chan, unsigned long from, | |
124 | unsigned long to, size_t size, unsigned int mode); | |
125 | ||
126 | #define dma_write(chan, from, to, size) \ | |
127 | dma_xfer(chan, from, to, size, DMA_MODE_WRITE) | |
128 | #define dma_write_page(chan, from, to) \ | |
129 | dma_write(chan, from, to, PAGE_SIZE) | |
130 | ||
131 | #define dma_read(chan, from, to, size) \ | |
132 | dma_xfer(chan, from, to, size, DMA_MODE_READ) | |
133 | #define dma_read_page(chan, from, to) \ | |
134 | dma_read(chan, from, to, PAGE_SIZE) | |
135 | ||
db9b99d4 MG |
136 | extern int request_dma_bycap(const char **dmac, const char **caps, |
137 | const char *dev_id); | |
1da177e4 LT |
138 | extern int request_dma(unsigned int chan, const char *dev_id); |
139 | extern void free_dma(unsigned int chan); | |
140 | extern int get_dma_residue(unsigned int chan); | |
141 | extern struct dma_info *get_dma_info(unsigned int chan); | |
142 | extern struct dma_channel *get_dma_channel(unsigned int chan); | |
143 | extern void dma_wait_for_completion(unsigned int chan); | |
144 | extern void dma_configure_channel(unsigned int chan, unsigned long flags); | |
145 | ||
146 | extern int register_dmac(struct dma_info *info); | |
147 | extern void unregister_dmac(struct dma_info *info); | |
db9b99d4 MG |
148 | extern struct dma_info *get_dma_info_by_name(const char *dmac_name); |
149 | ||
150 | extern int dma_extend(unsigned int chan, unsigned long op, void *param); | |
151 | extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); | |
1da177e4 LT |
152 | |
153 | #ifdef CONFIG_SYSFS | |
154 | /* arch/sh/drivers/dma/dma-sysfs.c */ | |
0d831770 PM |
155 | extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); |
156 | extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); | |
157 | #else | |
158 | #define dma_create_sysfs_file(channel, info) do { } while (0) | |
159 | #define dma_remove_sysfs_file(channel, info) do { } while (0) | |
1da177e4 LT |
160 | #endif |
161 | ||
162 | #ifdef CONFIG_PCI | |
163 | extern int isa_dma_bridge_buggy; | |
164 | #else | |
165 | #define isa_dma_bridge_buggy (0) | |
166 | #endif | |
167 | ||
168 | #endif /* __KERNEL__ */ | |
169 | #endif /* __ASM_SH_DMA_H */ |