[deliverable/linux.git] / include / asm-sh / hw_irq.h

#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H

#include <linux/init.h>
#include <asm/atomic.h>

extern atomic_t irq_err_count;

struct ipr_data {
	unsigned char irq;
	unsigned char ipr_idx;		/* Index for the IPR registered */
	unsigned char shift;		/* Number of bits to shift the data */
	unsigned char priority;		/* The priority */
};

struct ipr_desc {
	unsigned long *ipr_offsets;
	unsigned int nr_offsets;
	struct ipr_data *ipr_data;
	unsigned int nr_irqs;
	struct irq_chip chip;
};

void register_ipr_controller(struct ipr_desc *);

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_group {
	intc_enum enum_id;
	intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_prio_reg {
	unsigned long set_reg, clr_reg, reg_width, field_width;
	intc_enum enum_ids[16];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

#ifdef CONFIG_SMP
#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif

struct intc_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	char *name;
#ifdef CONFIG_CPU_SH3
	struct intc_mask_reg *ack_regs;
	unsigned int nr_ack_regs;
#endif
};

#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	mask_regs, prio_regs, sense_regs)				\
struct intc_desc symbol __initdata = {					\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
	_INTC_ARRAY(sense_regs),					\
	chipname,							\
}

#ifdef CONFIG_CPU_SH3
#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
	mask_regs, prio_regs, sense_regs, ack_regs)			\
struct intc_desc symbol __initdata = {					\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
	_INTC_ARRAY(sense_regs),					\
	chipname,							\
	_INTC_ARRAY(ack_regs),						\
}
#endif

void __init register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);

void __init plat_irq_setup(void);
#ifdef CONFIG_CPU_SH3
void __init plat_irq_setup_sh3(void);
#endif

enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
void __init plat_irq_setup_pins(int mode);

#endif /* __ASM_SH_HW_IRQ_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_HW_IRQ_H
	2	#define __ASM_SH_HW_IRQ_H
	3
02ab3f70	4	#include <linux/init.h>
35f3c518 PM	5	#include <asm/atomic.h>
	6
	7	extern atomic_t irq_err_count;
	8
68abdbbb MD	9	struct ipr_data {
	10	unsigned char irq;
	11	unsigned char ipr_idx; /* Index for the IPR registered */
	12	unsigned char shift; /* Number of bits to shift the data */
	13	unsigned char priority; /* The priority */
	14	};
	15
	16	struct ipr_desc {
	17	unsigned long *ipr_offsets;
	18	unsigned int nr_offsets;
	19	struct ipr_data *ipr_data;
	20	unsigned int nr_irqs;
	21	struct irq_chip chip;
	22	};
	23
	24	void register_ipr_controller(struct ipr_desc *);
68abdbbb	25
02ab3f70 MD	26	typedef unsigned char intc_enum;
	27
	28	struct intc_vect {
	29	intc_enum enum_id;
	30	unsigned short vect;
	31	};
	32
	33	#define INTC_VECT(enum_id, vect) { enum_id, vect }
51da6426	34	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
02ab3f70	35
02ab3f70 MD	36	struct intc_group {
02ab3f70 MD	37	intc_enum enum_id;
5c37e025	38	intc_enum enum_ids[32];
02ab3f70 MD	39	};
02ab3f70 MD	40
5c37e025	41	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
02ab3f70 MD	42
	43	struct intc_mask_reg {
	44	unsigned long set_reg, clr_reg, reg_width;
	45	intc_enum enum_ids[32];
f18d533e MD	46	#ifdef CONFIG_SMP
	47	unsigned long smp;
	48	#endif
02ab3f70 MD	49	};
	50
	51	struct intc_prio_reg {
6ef5fb2c	52	unsigned long set_reg, clr_reg, reg_width, field_width;
02ab3f70	53	intc_enum enum_ids[16];
f18d533e MD	54	#ifdef CONFIG_SMP
	55	unsigned long smp;
	56	#endif
02ab3f70 MD	57	};
	58
	59	struct intc_sense_reg {
	60	unsigned long reg, reg_width, field_width;
	61	intc_enum enum_ids[16];
	62	};
	63
f18d533e MD	64	#ifdef CONFIG_SMP
	65	#define INTC_SMP(stride, nr) .smp = (stride) \| ((nr) << 8)
	66	#else
	67	#define INTC_SMP(stride, nr)
	68	#endif
	69
02ab3f70 MD	70	struct intc_desc {
	71	struct intc_vect *vectors;
	72	unsigned int nr_vectors;
	73	struct intc_group *groups;
	74	unsigned int nr_groups;
02ab3f70 MD	75	struct intc_mask_reg *mask_regs;
	76	unsigned int nr_mask_regs;
	77	struct intc_prio_reg *prio_regs;
	78	unsigned int nr_prio_regs;
	79	struct intc_sense_reg *sense_regs;
	80	unsigned int nr_sense_regs;
73505b44	81	char *name;
d58876e2 MD	82	#ifdef CONFIG_CPU_SH3
	83	struct intc_mask_reg *ack_regs;
	84	unsigned int nr_ack_regs;
	85	#endif
02ab3f70 MD	86	};
	87
	88	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
	89	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
7f3edee8	90	mask_regs, prio_regs, sense_regs) \
5c37e025	91	struct intc_desc symbol __initdata = { \
02ab3f70	92	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
02ab3f70 MD	93	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
02ab3f70 MD	94	_INTC_ARRAY(sense_regs), \
73505b44	95	chipname, \
02ab3f70 MD	96	}
02ab3f70 MD	97
d58876e2 MD	98	#ifdef CONFIG_CPU_SH3
	99	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
	100	mask_regs, prio_regs, sense_regs, ack_regs) \
	101	struct intc_desc symbol __initdata = { \
	102	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	103	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	104	_INTC_ARRAY(sense_regs), \
	105	chipname, \
	106	_INTC_ARRAY(ack_regs), \
	107	}
	108	#endif
	109
02ab3f70	110	void __init register_intc_controller(struct intc_desc *desc);
3d37d94e	111	int intc_set_priority(unsigned int irq, unsigned int prio);
02ab3f70	112
90015c89	113	void __init plat_irq_setup(void);
a276e588 MD	114	#ifdef CONFIG_CPU_SH3
	115	void __init plat_irq_setup_sh3(void);
	116	#endif
90015c89	117
a0e23267	118	enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
953c8ef2	119	IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
a0e23267	120	IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
39c7aa9e MD	121	void __init plat_irq_setup_pins(int mode);
39c7aa9e MD	122
1da177e4	123	#endif /* __ASM_SH_HW_IRQ_H */