Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
26ff6c11 PM |
2 | * This file contains the functions and defines necessary to modify and |
3 | * use the SuperH page table tree. | |
4 | * | |
1da177e4 | 5 | * Copyright (C) 1999 Niibe Yutaka |
249cfea9 | 6 | * Copyright (C) 2002 - 2007 Paul Mundt |
26ff6c11 PM |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General | |
9 | * Public License. See the file "COPYING" in the main directory of this | |
10 | * archive for more details. | |
1da177e4 | 11 | */ |
26ff6c11 PM |
12 | #ifndef __ASM_SH_PGTABLE_H |
13 | #define __ASM_SH_PGTABLE_H | |
1da177e4 | 14 | |
26ff6c11 PM |
15 | #include <asm-generic/pgtable-nopmd.h> |
16 | #include <asm/page.h> | |
17 | ||
1da177e4 | 18 | #ifndef __ASSEMBLY__ |
1da177e4 LT |
19 | #include <asm/addrspace.h> |
20 | #include <asm/fixmap.h> | |
1da177e4 | 21 | |
1da177e4 LT |
22 | /* |
23 | * ZERO_PAGE is a global shared page that is always zero: used | |
24 | * for zero-mapped memory areas etc.. | |
25 | */ | |
26ff6c11 | 26 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
1da177e4 LT |
27 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) |
28 | ||
29 | #endif /* !__ASSEMBLY__ */ | |
30 | ||
36bcd39d PM |
31 | /* |
32 | * Effective and physical address definitions, to aid with sign | |
33 | * extension. | |
34 | */ | |
35 | #define NEFF 32 | |
36 | #define NEFF_SIGN (1LL << (NEFF - 1)) | |
37 | #define NEFF_MASK (-1LL << NEFF) | |
38 | ||
39 | #ifdef CONFIG_29BIT | |
40 | #define NPHYS 29 | |
41 | #else | |
42 | #define NPHYS 32 | |
43 | #endif | |
44 | ||
45 | #define NPHYS_SIGN (1LL << (NPHYS - 1)) | |
46 | #define NPHYS_MASK (-1LL << NPHYS) | |
47 | ||
21440cf0 PM |
48 | /* |
49 | * traditional two-level paging structure | |
50 | */ | |
51 | /* PTE bits */ | |
55183e9b | 52 | #if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64) |
21440cf0 PM |
53 | # define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */ |
54 | #else | |
55 | # define PTE_MAGNITUDE 2 /* 32-bit PTEs */ | |
56 | #endif | |
57 | #define PTE_SHIFT PAGE_SHIFT | |
58 | #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE) | |
59 | ||
60 | /* PGD bits */ | |
61 | #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) | |
db2e1fa3 | 62 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
1da177e4 LT |
63 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
64 | ||
21440cf0 | 65 | /* Entries per level */ |
7a847f81 | 66 | #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) |
d04a0f79 | 67 | #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) |
21440cf0 | 68 | |
1da177e4 | 69 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) |
d455a369 | 70 | #define FIRST_USER_ADDRESS 0 |
1da177e4 | 71 | |
d02b08f6 SM |
72 | #ifdef CONFIG_32BIT |
73 | #define PHYS_ADDR_MASK 0xffffffff | |
74 | #else | |
75 | #define PHYS_ADDR_MASK 0x1fffffff | |
76 | #endif | |
77 | ||
78 | #define PTE_PHYS_MASK (PHYS_ADDR_MASK & PAGE_MASK) | |
1da177e4 | 79 | |
0468b4bb | 80 | #ifdef CONFIG_SUPERH32 |
f0b859e3 | 81 | #define VMALLOC_START (P3SEG) |
0468b4bb PM |
82 | #else |
83 | #define VMALLOC_START (0xf0000000) | |
84 | #endif | |
1da177e4 LT |
85 | #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) |
86 | ||
249cfea9 PM |
87 | #if defined(CONFIG_SUPERH32) |
88 | #include <asm/pgtable_32.h> | |
21440cf0 | 89 | #else |
249cfea9 | 90 | #include <asm/pgtable_64.h> |
1da177e4 LT |
91 | #endif |
92 | ||
93 | /* | |
21440cf0 PM |
94 | * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page |
95 | * protection for execute, and considers it the same as a read. Also, write | |
96 | * permission implies read permission. This is the closest we can get.. | |
97 | * | |
98 | * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme, | |
99 | * not only supporting separate execute, read, and write bits, but having | |
100 | * completely separate permission bits for user and kernel space. | |
1da177e4 | 101 | */ |
21440cf0 | 102 | /*xwr*/ |
1da177e4 LT |
103 | #define __P000 PAGE_NONE |
104 | #define __P001 PAGE_READONLY | |
105 | #define __P010 PAGE_COPY | |
106 | #define __P011 PAGE_COPY | |
21440cf0 PM |
107 | #define __P100 PAGE_EXECREAD |
108 | #define __P101 PAGE_EXECREAD | |
1da177e4 LT |
109 | #define __P110 PAGE_COPY |
110 | #define __P111 PAGE_COPY | |
111 | ||
112 | #define __S000 PAGE_NONE | |
113 | #define __S001 PAGE_READONLY | |
21440cf0 | 114 | #define __S010 PAGE_WRITEONLY |
1da177e4 | 115 | #define __S011 PAGE_SHARED |
21440cf0 PM |
116 | #define __S100 PAGE_EXECREAD |
117 | #define __S101 PAGE_EXECREAD | |
118 | #define __S110 PAGE_RWX | |
119 | #define __S111 PAGE_RWX | |
1da177e4 | 120 | |
1da177e4 LT |
121 | typedef pte_t *pte_addr_t; |
122 | ||
1da177e4 LT |
123 | #define kern_addr_valid(addr) (1) |
124 | ||
1da177e4 LT |
125 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ |
126 | remap_pfn_range(vma, vaddr, pfn, size, prot) | |
127 | ||
249cfea9 | 128 | #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) |
8c65b4a6 | 129 | |
1da177e4 LT |
130 | /* |
131 | * No page table caches to initialise | |
132 | */ | |
133 | #define pgtable_cache_init() do { } while (0) | |
134 | ||
e7bd34a1 PM |
135 | #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ |
136 | defined(CONFIG_SH7705_CACHE_32KB)) | |
249cfea9 | 137 | struct mm_struct; |
39e688a9 | 138 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
249cfea9 | 139 | pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
39e688a9 PM |
140 | #endif |
141 | ||
249cfea9 PM |
142 | struct vm_area_struct; |
143 | extern void update_mmu_cache(struct vm_area_struct * vma, | |
144 | unsigned long address, pte_t pte); | |
21440cf0 PM |
145 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
146 | extern void paging_init(void); | |
9acb98fb PM |
147 | extern void page_table_range_init(unsigned long start, unsigned long end, |
148 | pgd_t *pgd); | |
21440cf0 | 149 | |
1da177e4 LT |
150 | #include <asm-generic/pgtable.h> |
151 | ||
249cfea9 | 152 | #endif /* __ASM_SH_PGTABLE_H */ |