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1da177e4 LT |
1 | /* |
2 | * include/asm-sh/processor.h | |
3 | * | |
4 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
5 | * Copyright (C) 2002, 2003 Paul Mundt | |
6 | */ | |
7 | ||
8 | #ifndef __ASM_SH_PROCESSOR_H | |
9 | #define __ASM_SH_PROCESSOR_H | |
10 | #ifdef __KERNEL__ | |
11 | ||
f6dc8c5b | 12 | #include <linux/compiler.h> |
1da177e4 LT |
13 | #include <asm/page.h> |
14 | #include <asm/types.h> | |
15 | #include <asm/cache.h> | |
1da177e4 | 16 | #include <asm/ptrace.h> |
315bb968 | 17 | #include <asm/cpu-features.h> |
1da177e4 LT |
18 | |
19 | /* | |
20 | * Default implementation of macro that returns current | |
21 | * instruction pointer ("program counter"). | |
22 | */ | |
23 | #define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n1:":"=z" (pc)); pc; }) | |
24 | ||
25 | /* Core Processor Version Register */ | |
26 | #define CCN_PVR 0xff000030 | |
27 | #define CCN_CVR 0xff000040 | |
28 | #define CCN_PRR 0xff000044 | |
29 | ||
30 | /* | |
31 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
32 | * | |
33 | * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry | |
de02797a | 34 | * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c |
1da177e4 LT |
35 | * for parsing the subtype in get_cpu_subtype(). |
36 | */ | |
37 | enum cpu_type { | |
38 | /* SH-2 types */ | |
b229632a YS |
39 | CPU_SH7604, CPU_SH7619, |
40 | ||
41 | /* SH-2A types */ | |
42 | CPU_SH7206, | |
1da177e4 LT |
43 | |
44 | /* SH-3 types */ | |
e5723e0e PM |
45 | CPU_SH7705, CPU_SH7706, CPU_SH7707, |
46 | CPU_SH7708, CPU_SH7708S, CPU_SH7708R, | |
47 | CPU_SH7709, CPU_SH7709A, CPU_SH7710, | |
48 | CPU_SH7729, CPU_SH7300, | |
1da177e4 LT |
49 | |
50 | /* SH-4 types */ | |
51 | CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, | |
52 | CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, | |
b552c7e8 PM |
53 | |
54 | /* SH-4A types */ | |
e5723e0e | 55 | CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781, |
b552c7e8 | 56 | CPU_SH7785, |
1da177e4 LT |
57 | |
58 | /* Unknown subtype */ | |
59 | CPU_SH_NONE | |
60 | }; | |
61 | ||
62 | struct sh_cpuinfo { | |
72c35543 | 63 | unsigned int type; |
1da177e4 LT |
64 | unsigned long loops_per_jiffy; |
65 | ||
72c35543 PM |
66 | struct cache_info icache; /* Primary I-cache */ |
67 | struct cache_info dcache; /* Primary D-cache */ | |
68 | struct cache_info scache; /* Secondary cache */ | |
1da177e4 LT |
69 | |
70 | unsigned long flags; | |
72c35543 | 71 | } __attribute__ ((aligned(SMP_CACHE_BYTES))); |
1da177e4 LT |
72 | |
73 | extern struct sh_cpuinfo boot_cpu_data; | |
74 | ||
75 | #ifdef CONFIG_SMP | |
76 | extern struct sh_cpuinfo cpu_data[]; | |
77 | #define current_cpu_data cpu_data[smp_processor_id()] | |
78 | #else | |
79 | #define cpu_data (&boot_cpu_data) | |
80 | #define current_cpu_data boot_cpu_data | |
81 | #endif | |
82 | ||
83 | /* | |
84 | * User space process size: 2GB. | |
85 | * | |
86 | * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff | |
87 | */ | |
88 | #define TASK_SIZE 0x7c000000UL | |
89 | ||
90 | /* This decides where the kernel will search for a free chunk of vm | |
91 | * space during mmap's. | |
92 | */ | |
93 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 3) | |
94 | ||
95 | /* | |
96 | * Bit of SR register | |
97 | * | |
98 | * FD-bit: | |
99 | * When it's set, it means the processor doesn't have right to use FPU, | |
100 | * and it results exception when the floating operation is executed. | |
101 | * | |
102 | * IMASK-bit: | |
103 | * Interrupt level mask | |
104 | */ | |
105 | #define SR_FD 0x00008000 | |
106 | #define SR_DSP 0x00001000 | |
107 | #define SR_IMASK 0x000000f0 | |
108 | ||
109 | /* | |
110 | * FPU structure and data | |
111 | */ | |
112 | ||
113 | struct sh_fpu_hard_struct { | |
114 | unsigned long fp_regs[16]; | |
115 | unsigned long xfp_regs[16]; | |
116 | unsigned long fpscr; | |
117 | unsigned long fpul; | |
118 | ||
119 | long status; /* software status information */ | |
120 | }; | |
121 | ||
122 | /* Dummy fpu emulator */ | |
123 | struct sh_fpu_soft_struct { | |
124 | unsigned long fp_regs[16]; | |
125 | unsigned long xfp_regs[16]; | |
126 | unsigned long fpscr; | |
127 | unsigned long fpul; | |
128 | ||
129 | unsigned char lookahead; | |
130 | unsigned long entry_pc; | |
131 | }; | |
132 | ||
133 | union sh_fpu_union { | |
134 | struct sh_fpu_hard_struct hard; | |
135 | struct sh_fpu_soft_struct soft; | |
136 | }; | |
137 | ||
1da177e4 LT |
138 | struct thread_struct { |
139 | unsigned long sp; | |
140 | unsigned long pc; | |
141 | ||
142 | unsigned long trap_no, error_code; | |
143 | unsigned long address; | |
144 | /* Hardware debugging registers may come here */ | |
145 | unsigned long ubc_pc; | |
146 | ||
147 | /* floating point info */ | |
148 | union sh_fpu_union fpu; | |
149 | }; | |
150 | ||
2991be72 PM |
151 | typedef struct { |
152 | unsigned long seg; | |
153 | } mm_segment_t; | |
154 | ||
1da177e4 LT |
155 | /* Count of active tasks with UBC settings */ |
156 | extern int ubc_usercnt; | |
157 | ||
158 | #define INIT_THREAD { \ | |
159 | sizeof(init_stack) + (long) &init_stack, /* sp */ \ | |
160 | 0, /* pc */ \ | |
de02797a PM |
161 | 0, 0, \ |
162 | 0, \ | |
163 | 0, \ | |
164 | {{{0,}},} /* fpu state */ \ | |
1da177e4 LT |
165 | } |
166 | ||
167 | /* | |
168 | * Do necessary setup to start up a newly executed thread. | |
169 | */ | |
170 | #define start_thread(regs, new_pc, new_sp) \ | |
171 | set_fs(USER_DS); \ | |
de02797a | 172 | regs->pr = 0; \ |
1da177e4 LT |
173 | regs->sr = SR_FD; /* User mode. */ \ |
174 | regs->pc = new_pc; \ | |
175 | regs->regs[15] = new_sp | |
176 | ||
177 | /* Forward declaration, a strange C thing */ | |
178 | struct task_struct; | |
179 | struct mm_struct; | |
180 | ||
181 | /* Free all resources held by a thread. */ | |
182 | extern void release_thread(struct task_struct *); | |
183 | ||
184 | /* Prepare to copy thread state - unlazy all lazy status */ | |
185 | #define prepare_to_copy(tsk) do { } while (0) | |
186 | ||
187 | /* | |
188 | * create a kernel thread without removing it from tasklists | |
189 | */ | |
190 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | |
191 | ||
192 | /* Copy and release all segment info associated with a VM */ | |
193 | #define copy_segments(p, mm) do { } while(0) | |
194 | #define release_segments(mm) do { } while(0) | |
195 | ||
196 | /* | |
197 | * FPU lazy state save handling. | |
198 | */ | |
199 | ||
200 | static __inline__ void disable_fpu(void) | |
201 | { | |
202 | unsigned long __dummy; | |
203 | ||
204 | /* Set FD flag in SR */ | |
205 | __asm__ __volatile__("stc sr, %0\n\t" | |
206 | "or %1, %0\n\t" | |
207 | "ldc %0, sr" | |
208 | : "=&r" (__dummy) | |
209 | : "r" (SR_FD)); | |
210 | } | |
211 | ||
212 | static __inline__ void enable_fpu(void) | |
213 | { | |
214 | unsigned long __dummy; | |
215 | ||
216 | /* Clear out FD flag in SR */ | |
217 | __asm__ __volatile__("stc sr, %0\n\t" | |
218 | "and %1, %0\n\t" | |
219 | "ldc %0, sr" | |
220 | : "=&r" (__dummy) | |
221 | : "r" (~SR_FD)); | |
222 | } | |
223 | ||
224 | static __inline__ void release_fpu(struct pt_regs *regs) | |
225 | { | |
226 | regs->sr |= SR_FD; | |
227 | } | |
228 | ||
229 | static __inline__ void grab_fpu(struct pt_regs *regs) | |
230 | { | |
231 | regs->sr &= ~SR_FD; | |
232 | } | |
233 | ||
234 | #ifdef CONFIG_CPU_SH4 | |
235 | extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); | |
236 | #else | |
237 | #define save_fpu(tsk) do { } while (0) | |
238 | #endif | |
239 | ||
de02797a | 240 | #define unlazy_fpu(tsk, regs) do { \ |
1da177e4 | 241 | if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ |
de02797a | 242 | save_fpu(tsk, regs); \ |
1da177e4 LT |
243 | } \ |
244 | } while (0) | |
245 | ||
de02797a PM |
246 | #define clear_fpu(tsk, regs) do { \ |
247 | if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ | |
248 | clear_tsk_thread_flag(tsk, TIF_USEDFPU); \ | |
249 | release_fpu(regs); \ | |
1da177e4 LT |
250 | } \ |
251 | } while (0) | |
252 | ||
253 | /* Double presision, NANS as NANS, rounding to nearest, no exceptions */ | |
254 | #define FPSCR_INIT 0x00080000 | |
255 | ||
256 | #define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */ | |
257 | #define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */ | |
258 | ||
259 | /* | |
260 | * Return saved PC of a blocked thread. | |
261 | */ | |
262 | #define thread_saved_pc(tsk) (tsk->thread.pc) | |
263 | ||
6b002230 PM |
264 | void show_trace(struct task_struct *tsk, unsigned long *sp, |
265 | struct pt_regs *regs); | |
1da177e4 LT |
266 | extern unsigned long get_wchan(struct task_struct *p); |
267 | ||
268 | #define KSTK_EIP(tsk) ((tsk)->thread.pc) | |
269 | #define KSTK_ESP(tsk) ((tsk)->thread.sp) | |
270 | ||
271 | #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") | |
f6dc8c5b | 272 | #define cpu_relax() barrier() |
1da177e4 | 273 | |
e86d6b66 PM |
274 | #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \ |
275 | defined(CONFIG_CPU_SH4) | |
276 | #define PREFETCH_STRIDE L1_CACHE_BYTES | |
277 | #define ARCH_HAS_PREFETCH | |
278 | #define ARCH_HAS_PREFETCHW | |
279 | static inline void prefetch(void *x) | |
280 | { | |
281 | __asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory"); | |
282 | } | |
283 | ||
284 | #define prefetchw(x) prefetch(x) | |
285 | #endif | |
286 | ||
19f9a34f PM |
287 | #ifdef CONFIG_VSYSCALL |
288 | extern int vsyscall_init(void); | |
289 | #else | |
290 | #define vsyscall_init() do { } while (0) | |
291 | #endif | |
292 | ||
1da177e4 LT |
293 | #endif /* __KERNEL__ */ |
294 | #endif /* __ASM_SH_PROCESSOR_H */ |