Commit | Line | Data |
---|---|---|
af3c7dfe PM |
1 | #ifndef __ASM_SH_PROCESSOR_64_H |
2 | #define __ASM_SH_PROCESSOR_64_H | |
1da177e4 LT |
3 | |
4 | /* | |
af3c7dfe | 5 | * include/asm-sh/processor_64.h |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 2000, 2001 Paolo Alberelli | |
8 | * Copyright (C) 2003 Paul Mundt | |
9 | * Copyright (C) 2004 Richard Curnow | |
10 | * | |
af3c7dfe PM |
11 | * This file is subject to the terms and conditions of the GNU General Public |
12 | * License. See the file "COPYING" in the main directory of this archive | |
13 | * for more details. | |
1da177e4 | 14 | */ |
1da177e4 LT |
15 | #ifndef __ASSEMBLY__ |
16 | ||
af3c7dfe PM |
17 | #include <linux/compiler.h> |
18 | #include <asm/page.h> | |
1da177e4 LT |
19 | #include <asm/types.h> |
20 | #include <asm/cache.h> | |
256b22ca | 21 | #include <asm/ptrace.h> |
af3c7dfe | 22 | #include <asm/cpu/registers.h> |
1da177e4 LT |
23 | |
24 | /* | |
25 | * Default implementation of macro that returns current | |
26 | * instruction pointer ("program counter"). | |
27 | */ | |
28 | #define current_text_addr() ({ \ | |
29 | void *pc; \ | |
30 | unsigned long long __dummy = 0; \ | |
31 | __asm__("gettr tr0, %1\n\t" \ | |
32 | "pta 4, tr0\n\t" \ | |
33 | "gettr tr0, %0\n\t" \ | |
34 | "ptabs %1, tr0\n\t" \ | |
35 | :"=r" (pc), "=r" (__dummy) \ | |
36 | : "1" (__dummy)); \ | |
37 | pc; }) | |
38 | ||
1da177e4 LT |
39 | /* |
40 | * TLB information structure | |
41 | * | |
42 | * Defined for both I and D tlb, per-processor. | |
43 | */ | |
44 | struct tlb_info { | |
45 | unsigned long long next; | |
46 | unsigned long long first; | |
47 | unsigned long long last; | |
48 | ||
49 | unsigned int entries; | |
50 | unsigned int step; | |
51 | ||
52 | unsigned long flags; | |
53 | }; | |
54 | ||
55 | struct sh_cpuinfo { | |
56 | enum cpu_type type; | |
57 | unsigned long loops_per_jiffy; | |
c0acca67 | 58 | unsigned long asid_cache; |
1da177e4 | 59 | |
1da177e4 LT |
60 | unsigned int cpu_clock, master_clock, bus_clock, module_clock; |
61 | ||
62 | /* Cache info */ | |
63 | struct cache_info icache; | |
64 | struct cache_info dcache; | |
c0acca67 | 65 | struct cache_info scache; |
1da177e4 LT |
66 | |
67 | /* TLB info */ | |
68 | struct tlb_info itlb; | |
69 | struct tlb_info dtlb; | |
1da177e4 | 70 | |
76168c21 PM |
71 | unsigned long flags; |
72 | }; | |
1da177e4 | 73 | |
76168c21 PM |
74 | extern struct sh_cpuinfo cpu_data[]; |
75 | #define boot_cpu_data cpu_data[0] | |
76 | #define current_cpu_data cpu_data[smp_processor_id()] | |
77 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] | |
1da177e4 LT |
78 | |
79 | #endif | |
80 | ||
81 | /* | |
82 | * User space process size: 2GB - 4k. | |
83 | */ | |
84 | #define TASK_SIZE 0x7ffff000UL | |
85 | ||
922a70d3 DH |
86 | #define STACK_TOP TASK_SIZE |
87 | #define STACK_TOP_MAX STACK_TOP | |
88 | ||
1da177e4 LT |
89 | /* This decides where the kernel will search for a free chunk of vm |
90 | * space during mmap's. | |
91 | */ | |
92 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 3) | |
93 | ||
94 | /* | |
95 | * Bit of SR register | |
96 | * | |
97 | * FD-bit: | |
98 | * When it's set, it means the processor doesn't have right to use FPU, | |
99 | * and it results exception when the floating operation is executed. | |
100 | * | |
101 | * IMASK-bit: | |
102 | * Interrupt level mask | |
103 | * | |
104 | * STEP-bit: | |
105 | * Single step bit | |
106 | * | |
107 | */ | |
1da177e4 LT |
108 | #if defined(CONFIG_SH64_SR_WATCH) |
109 | #define SR_MMU 0x84000000 | |
110 | #else | |
111 | #define SR_MMU 0x80000000 | |
112 | #endif | |
113 | ||
114 | #define SR_IMASK 0x000000f0 | |
9bbafce2 | 115 | #define SR_FD 0x00008000 |
1da177e4 LT |
116 | #define SR_SSTEP 0x08000000 |
117 | ||
118 | #ifndef __ASSEMBLY__ | |
119 | ||
120 | /* | |
121 | * FPU structure and data : require 8-byte alignment as we need to access it | |
122 | with fld.p, fst.p | |
123 | */ | |
124 | ||
125 | struct sh_fpu_hard_struct { | |
126 | unsigned long fp_regs[64]; | |
127 | unsigned int fpscr; | |
128 | /* long status; * software status information */ | |
129 | }; | |
130 | ||
131 | #if 0 | |
132 | /* Dummy fpu emulator */ | |
133 | struct sh_fpu_soft_struct { | |
134 | unsigned long long fp_regs[32]; | |
135 | unsigned int fpscr; | |
136 | unsigned char lookahead; | |
137 | unsigned long entry_pc; | |
138 | }; | |
139 | #endif | |
140 | ||
141 | union sh_fpu_union { | |
142 | struct sh_fpu_hard_struct hard; | |
143 | /* 'hard' itself only produces 32 bit alignment, yet we need | |
144 | to access it using 64 bit load/store as well. */ | |
145 | unsigned long long alignment_dummy; | |
146 | }; | |
147 | ||
148 | struct thread_struct { | |
149 | unsigned long sp; | |
150 | unsigned long pc; | |
151 | /* This stores the address of the pt_regs built during a context | |
152 | switch, or of the register save area built for a kernel mode | |
153 | exception. It is used for backtracing the stack of a sleeping task | |
154 | or one that traps in kernel mode. */ | |
155 | struct pt_regs *kregs; | |
156 | /* This stores the address of the pt_regs constructed on entry from | |
157 | user mode. It is a fixed value over the lifetime of a process, or | |
158 | NULL for a kernel thread. */ | |
159 | struct pt_regs *uregs; | |
160 | ||
161 | unsigned long trap_no, error_code; | |
162 | unsigned long address; | |
163 | /* Hardware debugging registers may come here */ | |
164 | ||
165 | /* floating point info */ | |
166 | union sh_fpu_union fpu; | |
167 | }; | |
168 | ||
af3c7dfe PM |
169 | typedef struct { |
170 | unsigned long seg; | |
171 | } mm_segment_t; | |
172 | ||
1da177e4 LT |
173 | #define INIT_MMAP \ |
174 | { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } | |
175 | ||
176 | extern struct pt_regs fake_swapper_regs; | |
177 | ||
178 | #define INIT_THREAD { \ | |
179 | .sp = sizeof(init_stack) + \ | |
180 | (long) &init_stack, \ | |
181 | .pc = 0, \ | |
182 | .kregs = &fake_swapper_regs, \ | |
183 | .uregs = NULL, \ | |
184 | .trap_no = 0, \ | |
185 | .error_code = 0, \ | |
186 | .address = 0, \ | |
187 | .fpu = { { { 0, } }, } \ | |
188 | } | |
189 | ||
190 | /* | |
191 | * Do necessary setup to start up a newly executed thread. | |
192 | */ | |
193 | #define SR_USER (SR_MMU | SR_FD) | |
194 | ||
af3c7dfe PM |
195 | #define start_thread(regs, new_pc, new_sp) \ |
196 | set_fs(USER_DS); \ | |
197 | regs->sr = SR_USER; /* User mode. */ \ | |
1da177e4 LT |
198 | regs->pc = new_pc - 4; /* Compensate syscall exit */ \ |
199 | regs->pc |= 1; /* Set SHmedia ! */ \ | |
af3c7dfe | 200 | regs->regs[18] = 0; \ |
1da177e4 LT |
201 | regs->regs[15] = new_sp |
202 | ||
203 | /* Forward declaration, a strange C thing */ | |
204 | struct task_struct; | |
205 | struct mm_struct; | |
206 | ||
207 | /* Free all resources held by a thread. */ | |
208 | extern void release_thread(struct task_struct *); | |
209 | /* | |
210 | * create a kernel thread without removing it from tasklists | |
211 | */ | |
212 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | |
213 | ||
214 | ||
215 | /* Copy and release all segment info associated with a VM */ | |
216 | #define copy_segments(p, mm) do { } while (0) | |
217 | #define release_segments(mm) do { } while (0) | |
218 | #define forget_segments() do { } while (0) | |
219 | #define prepare_to_copy(tsk) do { } while (0) | |
220 | /* | |
221 | * FPU lazy state save handling. | |
222 | */ | |
223 | ||
256b22ca | 224 | static inline void disable_fpu(void) |
1da177e4 LT |
225 | { |
226 | unsigned long long __dummy; | |
227 | ||
228 | /* Set FD flag in SR */ | |
229 | __asm__ __volatile__("getcon " __SR ", %0\n\t" | |
230 | "or %0, %1, %0\n\t" | |
231 | "putcon %0, " __SR "\n\t" | |
232 | : "=&r" (__dummy) | |
233 | : "r" (SR_FD)); | |
234 | } | |
235 | ||
256b22ca | 236 | static inline void enable_fpu(void) |
1da177e4 LT |
237 | { |
238 | unsigned long long __dummy; | |
239 | ||
240 | /* Clear out FD flag in SR */ | |
241 | __asm__ __volatile__("getcon " __SR ", %0\n\t" | |
242 | "and %0, %1, %0\n\t" | |
243 | "putcon %0, " __SR "\n\t" | |
244 | : "=&r" (__dummy) | |
245 | : "r" (~SR_FD)); | |
246 | } | |
247 | ||
248 | /* Round to nearest, no exceptions on inexact, overflow, underflow, | |
249 | zero-divide, invalid. Configure option for whether to flush denorms to | |
250 | zero, or except if a denorm is encountered. */ | |
251 | #if defined(CONFIG_SH64_FPU_DENORM_FLUSH) | |
252 | #define FPSCR_INIT 0x00040000 | |
253 | #else | |
254 | #define FPSCR_INIT 0x00000000 | |
255 | #endif | |
256 | ||
ffd25eb6 | 257 | #ifdef CONFIG_SH_FPU |
1da177e4 LT |
258 | /* Initialise the FP state of a task */ |
259 | void fpinit(struct sh_fpu_hard_struct *fpregs); | |
ffd25eb6 | 260 | #else |
ffd25eb6 PM |
261 | #define fpinit(fpregs) do { } while (0) |
262 | #endif | |
1da177e4 LT |
263 | |
264 | extern struct task_struct *last_task_used_math; | |
265 | ||
266 | /* | |
267 | * Return saved PC of a blocked thread. | |
268 | */ | |
269 | #define thread_saved_pc(tsk) (tsk->thread.pc) | |
270 | ||
271 | extern unsigned long get_wchan(struct task_struct *p); | |
272 | ||
273 | #define KSTK_EIP(tsk) ((tsk)->thread.pc) | |
274 | #define KSTK_ESP(tsk) ((tsk)->thread.sp) | |
275 | ||
f6dc8c5b | 276 | #define cpu_relax() barrier() |
1da177e4 LT |
277 | |
278 | #endif /* __ASSEMBLY__ */ | |
af3c7dfe | 279 | #endif /* __ASM_SH_PROCESSOR_64_H */ |