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1da177e4 LT |
1 | #ifndef __ASM_SH_SYSTEM_H |
2 | #define __ASM_SH_SYSTEM_H | |
3 | ||
4 | /* | |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
6 | * Copyright (C) 2002 Paul Mundt | |
7 | */ | |
8 | ||
afbfb52e | 9 | #include <linux/irqflags.h> |
310f7963 | 10 | #include <linux/compiler.h> |
e08f457c | 11 | #include <linux/linkage.h> |
e4e3b5cc | 12 | #include <asm/types.h> |
3a2e117e | 13 | #include <asm/ptrace.h> |
1da177e4 | 14 | |
4f9a58d7 | 15 | #define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */ |
1da177e4 | 16 | |
a62a3861 | 17 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) |
29847622 PM |
18 | #define __icbi() \ |
19 | { \ | |
20 | unsigned long __addr; \ | |
21 | __addr = 0xa8000000; \ | |
22 | __asm__ __volatile__( \ | |
23 | "icbi %0\n\t" \ | |
24 | : /* no output */ \ | |
25 | : "m" (__m(__addr))); \ | |
26 | } | |
27 | #endif | |
1da177e4 | 28 | |
29847622 PM |
29 | /* |
30 | * A brief note on ctrl_barrier(), the control register write barrier. | |
31 | * | |
32 | * Legacy SH cores typically require a sequence of 8 nops after | |
33 | * modification of a control register in order for the changes to take | |
34 | * effect. On newer cores (like the sh4a and sh5) this is accomplished | |
35 | * with icbi. | |
36 | * | |
37 | * Also note that on sh4a in the icbi case we can forego a synco for the | |
38 | * write barrier, as it's not necessary for control registers. | |
39 | * | |
40 | * Historically we have only done this type of barrier for the MMUCR, but | |
41 | * it's also necessary for the CCR, so we make it generic here instead. | |
42 | */ | |
a62a3861 | 43 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) |
29847622 PM |
44 | #define mb() __asm__ __volatile__ ("synco": : :"memory") |
45 | #define rmb() mb() | |
46 | #define wmb() __asm__ __volatile__ ("synco": : :"memory") | |
47 | #define ctrl_barrier() __icbi() | |
fdfc74f9 PM |
48 | #define read_barrier_depends() do { } while(0) |
49 | #else | |
29847622 PM |
50 | #define mb() __asm__ __volatile__ ("": : :"memory") |
51 | #define rmb() mb() | |
52 | #define wmb() __asm__ __volatile__ ("": : :"memory") | |
53 | #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") | |
1da177e4 | 54 | #define read_barrier_depends() do { } while(0) |
fdfc74f9 | 55 | #endif |
1da177e4 LT |
56 | |
57 | #ifdef CONFIG_SMP | |
58 | #define smp_mb() mb() | |
59 | #define smp_rmb() rmb() | |
60 | #define smp_wmb() wmb() | |
61 | #define smp_read_barrier_depends() read_barrier_depends() | |
62 | #else | |
63 | #define smp_mb() barrier() | |
64 | #define smp_rmb() barrier() | |
65 | #define smp_wmb() barrier() | |
66 | #define smp_read_barrier_depends() do { } while(0) | |
67 | #endif | |
68 | ||
357d5946 | 69 | #define set_mb(var, value) do { (void)xchg(&var, value); } while (0) |
1da177e4 | 70 | |
00b3aa3f | 71 | static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) |
1da177e4 LT |
72 | { |
73 | unsigned long flags, retval; | |
74 | ||
75 | local_irq_save(flags); | |
76 | retval = *m; | |
77 | *m = val; | |
78 | local_irq_restore(flags); | |
79 | return retval; | |
80 | } | |
81 | ||
00b3aa3f | 82 | static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) |
1da177e4 LT |
83 | { |
84 | unsigned long flags, retval; | |
85 | ||
86 | local_irq_save(flags); | |
87 | retval = *m; | |
88 | *m = val & 0xff; | |
89 | local_irq_restore(flags); | |
90 | return retval; | |
91 | } | |
92 | ||
00b3aa3f PM |
93 | extern void __xchg_called_with_bad_pointer(void); |
94 | ||
95 | #define __xchg(ptr, x, size) \ | |
96 | ({ \ | |
97 | unsigned long __xchg__res; \ | |
98 | volatile void *__xchg_ptr = (ptr); \ | |
99 | switch (size) { \ | |
100 | case 4: \ | |
101 | __xchg__res = xchg_u32(__xchg_ptr, x); \ | |
102 | break; \ | |
103 | case 1: \ | |
104 | __xchg__res = xchg_u8(__xchg_ptr, x); \ | |
105 | break; \ | |
106 | default: \ | |
107 | __xchg_called_with_bad_pointer(); \ | |
108 | __xchg__res = x; \ | |
109 | break; \ | |
110 | } \ | |
111 | \ | |
112 | __xchg__res; \ | |
113 | }) | |
114 | ||
115 | #define xchg(ptr,x) \ | |
116 | ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) | |
1da177e4 | 117 | |
e4e3b5cc TR |
118 | static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, |
119 | unsigned long new) | |
120 | { | |
121 | __u32 retval; | |
122 | unsigned long flags; | |
123 | ||
124 | local_irq_save(flags); | |
125 | retval = *m; | |
126 | if (retval == old) | |
127 | *m = new; | |
128 | local_irq_restore(flags); /* implies memory barrier */ | |
129 | return retval; | |
130 | } | |
131 | ||
132 | /* This function doesn't exist, so you'll get a linker error | |
133 | * if something tries to do an invalid cmpxchg(). */ | |
134 | extern void __cmpxchg_called_with_bad_pointer(void); | |
135 | ||
136 | #define __HAVE_ARCH_CMPXCHG 1 | |
137 | ||
138 | static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, | |
139 | unsigned long new, int size) | |
140 | { | |
141 | switch (size) { | |
142 | case 4: | |
143 | return __cmpxchg_u32(ptr, old, new); | |
144 | } | |
145 | __cmpxchg_called_with_bad_pointer(); | |
146 | return old; | |
147 | } | |
148 | ||
149 | #define cmpxchg(ptr,o,n) \ | |
150 | ({ \ | |
151 | __typeof__(*(ptr)) _o_ = (o); \ | |
152 | __typeof__(*(ptr)) _n_ = (n); \ | |
153 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
154 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
155 | }) | |
156 | ||
3a2e117e PM |
157 | extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn)); |
158 | ||
1f666587 PM |
159 | extern void *set_exception_table_vec(unsigned int vec, void *handler); |
160 | ||
161 | static inline void *set_exception_table_evt(unsigned int evt, void *handler) | |
162 | { | |
163 | return set_exception_table_vec(evt >> 5, handler); | |
164 | } | |
165 | ||
bd079997 PM |
166 | /* |
167 | * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. | |
168 | */ | |
169 | #ifdef CONFIG_CPU_SH2A | |
170 | extern unsigned int instruction_size(unsigned int insn); | |
0fa70efb | 171 | #elif defined(CONFIG_SUPERH32) |
bd079997 | 172 | #define instruction_size(insn) (2) |
0fa70efb PM |
173 | #else |
174 | #define instruction_size(insn) (4) | |
bd079997 PM |
175 | #endif |
176 | ||
1da177e4 LT |
177 | /* XXX |
178 | * disable hlt during certain critical i/o operations | |
179 | */ | |
180 | #define HAVE_DISABLE_HLT | |
181 | void disable_hlt(void); | |
182 | void enable_hlt(void); | |
183 | ||
e08f457c | 184 | void default_idle(void); |
aba1030a | 185 | void per_cpu_trap_init(void); |
e08f457c PM |
186 | |
187 | asmlinkage void break_point_trap(void); | |
5a4f7c66 PM |
188 | |
189 | #ifdef CONFIG_SUPERH32 | |
190 | #define BUILD_TRAP_HANDLER(name) \ | |
191 | asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \ | |
192 | unsigned long r6, unsigned long r7, \ | |
193 | struct pt_regs __regs) | |
194 | ||
195 | #define TRAP_HANDLER_DECL \ | |
196 | struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \ | |
b000659b PM |
197 | unsigned int vec = regs->tra; \ |
198 | (void)vec; | |
5a4f7c66 PM |
199 | #else |
200 | #define BUILD_TRAP_HANDLER(name) \ | |
201 | asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs) | |
202 | #define TRAP_HANDLER_DECL | |
203 | #endif | |
204 | ||
205 | BUILD_TRAP_HANDLER(address_error); | |
206 | BUILD_TRAP_HANDLER(debug); | |
207 | BUILD_TRAP_HANDLER(bug); | |
74d99a5e PM |
208 | BUILD_TRAP_HANDLER(fpu_error); |
209 | BUILD_TRAP_HANDLER(fpu_state_restore); | |
e08f457c | 210 | |
1da177e4 LT |
211 | #define arch_align_stack(x) (x) |
212 | ||
a62a3861 PM |
213 | #ifdef CONFIG_SUPERH32 |
214 | # include "system_32.h" | |
215 | #else | |
216 | # include "system_64.h" | |
217 | #endif | |
218 | ||
1da177e4 | 219 | #endif |