projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a62a3861 PM |
1 | #ifndef __ASM_SH_SYSTEM_32_H |
| 2 | #define __ASM_SH_SYSTEM_32_H | |
| 3 | ||
| 4 | #include <linux/types.h> | |
| 5 | ||
| 6 | struct task_struct *__switch_to(struct task_struct *prev, | |
| 7 | struct task_struct *next); | |
| 8 | ||
| 9 | /* | |
| 10 | * switch_to() should switch tasks to task nr n, first | |
| 11 | */ | |
| 830626ca PM |
12 | #define switch_to(prev, next, last) \ |
| 13 | do { \ | |
| 14 | register u32 *__ts1 __asm__ ("r1") = (u32 *)&prev->thread.sp; \ | |
| 15 | register u32 *__ts2 __asm__ ("r2") = (u32 *)&prev->thread.pc; \ | |
| 16 | register u32 *__ts4 __asm__ ("r4") = (u32 *)prev; \ | |
| 17 | register u32 *__ts5 __asm__ ("r5") = (u32 *)next; \ | |
| 18 | register u32 *__ts6 __asm__ ("r6") = (u32 *)&next->thread.sp; \ | |
| 19 | register u32 __ts7 __asm__ ("r7") = next->thread.pc; \ | |
| 20 | struct task_struct *__last; \ | |
| 21 | \ | |
| 22 | __asm__ __volatile__ ( \ | |
| 23 | ".balign 4\n\t" \ | |
| 24 | "stc.l gbr, @-r15\n\t" \ | |
| 25 | "sts.l pr, @-r15\n\t" \ | |
| 26 | "mov.l r8, @-r15\n\t" \ | |
| 27 | "mov.l r9, @-r15\n\t" \ | |
| 28 | "mov.l r10, @-r15\n\t" \ | |
| 29 | "mov.l r11, @-r15\n\t" \ | |
| 30 | "mov.l r12, @-r15\n\t" \ | |
| 31 | "mov.l r13, @-r15\n\t" \ | |
| 32 | "mov.l r14, @-r15\n\t" \ | |
| 33 | "mov.l r15, @r1\t! save SP\n\t" \ | |
| 34 | "mov.l @r6, r15\t! change to new stack\n\t" \ | |
| 35 | "mova 1f, %0\n\t" \ | |
| 36 | "mov.l %0, @r2\t! save PC\n\t" \ | |
| 37 | "mov.l 2f, %0\n\t" \ | |
| 38 | "jmp @%0\t! call __switch_to\n\t" \ | |
| 39 | " lds r7, pr\t! with return to new PC\n\t" \ | |
| 40 | ".balign 4\n" \ | |
| 41 | "2:\n\t" \ | |
| 42 | ".long __switch_to\n" \ | |
| 43 | "1:\n\t" \ | |
| 44 | "mov.l @r15+, r14\n\t" \ | |
| 45 | "mov.l @r15+, r13\n\t" \ | |
| 46 | "mov.l @r15+, r12\n\t" \ | |
| 47 | "mov.l @r15+, r11\n\t" \ | |
| 48 | "mov.l @r15+, r10\n\t" \ | |
| 49 | "mov.l @r15+, r9\n\t" \ | |
| 50 | "mov.l @r15+, r8\n\t" \ | |
| 51 | "lds.l @r15+, pr\n\t" \ | |
| 52 | "ldc.l @r15+, gbr\n\t" \ | |
| 53 | : "=z" (__last) \ | |
| 54 | : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ | |
| 55 | "r" (__ts5), "r" (__ts6), "r" (__ts7) \ | |
| 56 | : "r3", "t"); \ | |
| 57 | \ | |
| 58 | last = __last; \ | |
| a62a3861 PM |
59 | } while (0) |
| 60 | ||
| cbaa118e SM |
61 | #define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text"))) |
| 62 | ||
| a62a3861 | 63 | /* |
| cbaa118e SM |
64 | * Jump to uncached area. |
| 65 | * When handling TLB or caches, we need to do it from an uncached area. | |
| a62a3861 | 66 | */ |
| cbaa118e SM |
67 | #define jump_to_uncached() \ |
| 68 | do { \ | |
| 69 | unsigned long __dummy; \ | |
| 70 | \ | |
| 71 | __asm__ __volatile__( \ | |
| 72 | "mova 1f, %0\n\t" \ | |
| 73 | "add %1, %0\n\t" \ | |
| 74 | "jmp @%0\n\t" \ | |
| 75 | " nop\n\t" \ | |
| 76 | ".balign 4\n" \ | |
| 77 | "1:" \ | |
| 78 | : "=&z" (__dummy) \ | |
| 79 | : "r" (cached_to_uncached)); \ | |
| a62a3861 PM |
80 | } while (0) |
| 81 | ||
| 82 | /* | |
| cbaa118e | 83 | * Back to cached area. |
| a62a3861 | 84 | */ |
| cbaa118e | 85 | #define back_to_cached() \ |
| a62a3861 PM |
86 | do { \ |
| 87 | unsigned long __dummy; \ | |
| 88 | ctrl_barrier(); \ | |
| 89 | __asm__ __volatile__( \ | |
| 90 | "mov.l 1f, %0\n\t" \ | |
| 91 | "jmp @%0\n\t" \ | |
| 92 | " nop\n\t" \ | |
| 93 | ".balign 4\n" \ | |
| 94 | "1: .long 2f\n" \ | |
| 95 | "2:" \ | |
| 96 | : "=&r" (__dummy)); \ | |
| 97 | } while (0) | |
| 98 | ||
| e7cc9a73 MD |
99 | int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, |
| 100 | struct mem_access *ma); | |
| 101 | ||
| a62a3861 | 102 | #endif /* __ASM_SH_SYSTEM_32_H */ |