[deliverable/linux.git] / include / asm-sparc / cpudata_64.h

/* cpudata.h: Per-cpu parameters.
 *
 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC64_CPUDATA_H
#define _SPARC64_CPUDATA_H

#include <asm/hypervisor.h>
#include <asm/asi.h>

#ifndef __ASSEMBLY__

#include <linux/percpu.h>
#include <linux/threads.h>

typedef struct {
	/* Dcache line 1 */
	unsigned int	__softirq_pending; /* must be 1st, see rtrap.S */
	unsigned int	__pad0;
	unsigned long	clock_tick;	/* %tick's per second */
	unsigned long	__pad;
	unsigned int	__pad1;
	unsigned int	__pad2;

	/* Dcache line 2, rarely used */
	unsigned int	dcache_size;
	unsigned int	dcache_line_size;
	unsigned int	icache_size;
	unsigned int	icache_line_size;
	unsigned int	ecache_size;
	unsigned int	ecache_line_size;
	int		core_id;
	int		proc_id;
} cpuinfo_sparc;

DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
#define cpu_data(__cpu)		per_cpu(__cpu_data, (__cpu))
#define local_cpu_data()	__get_cpu_var(__cpu_data)

/* Trap handling code needs to get at a few critical values upon
 * trap entry and to process TSB misses.  These cannot be in the
 * per_cpu() area as we really need to lock them into the TLB and
 * thus make them part of the main kernel image.  As a result we
 * try to make this as small as possible.
 *
 * This is padded out and aligned to 64-bytes to avoid false sharing
 * on SMP.
 */

/* If you modify the size of this structure, please update
 * TRAP_BLOCK_SZ_SHIFT below.
 */
struct thread_info;
struct trap_per_cpu {
/* D-cache line 1: Basic thread information, cpu and device mondo queues */
	struct thread_info	*thread;
	unsigned long		pgd_paddr;
	unsigned long		cpu_mondo_pa;
	unsigned long		dev_mondo_pa;

/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
	unsigned long		resum_mondo_pa;
	unsigned long		resum_kernel_buf_pa;
	unsigned long		nonresum_mondo_pa;
	unsigned long		nonresum_kernel_buf_pa;

/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
	struct hv_fault_status	fault_info;

/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
	unsigned long		cpu_mondo_block_pa;
	unsigned long		cpu_list_pa;
	unsigned long		tsb_huge;
	unsigned long		tsb_huge_temp;

/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
	unsigned long		irq_worklist_pa;
	unsigned int		cpu_mondo_qmask;
	unsigned int		dev_mondo_qmask;
	unsigned int		resum_qmask;
	unsigned int		nonresum_qmask;
	void			*hdesc;
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
extern void init_cur_cpu_trap(struct thread_info *);
extern void setup_tba(void);
extern int ncpus_probed;
extern void __init cpu_probe(void);
extern const struct seq_operations cpuinfo_op;

extern unsigned long real_hard_smp_processor_id(void);

struct cpuid_patch_entry {
	unsigned int	addr;
	unsigned int	cheetah_safari[4];
	unsigned int	cheetah_jbus[4];
	unsigned int	starfire[4];
	unsigned int	sun4v[4];
};
extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;

struct sun4v_1insn_patch_entry {
	unsigned int	addr;
	unsigned int	insn;
};
extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
	__sun4v_1insn_patch_end;

struct sun4v_2insn_patch_entry {
	unsigned int	addr;
	unsigned int	insns[2];
};
extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
	__sun4v_2insn_patch_end;

#endif /* !(__ASSEMBLY__) */

#define TRAP_PER_CPU_THREAD		0x00
#define TRAP_PER_CPU_PGD_PADDR		0x08
#define TRAP_PER_CPU_CPU_MONDO_PA	0x10
#define TRAP_PER_CPU_DEV_MONDO_PA	0x18
#define TRAP_PER_CPU_RESUM_MONDO_PA	0x20
#define TRAP_PER_CPU_RESUM_KBUF_PA	0x28
#define TRAP_PER_CPU_NONRESUM_MONDO_PA	0x30
#define TRAP_PER_CPU_NONRESUM_KBUF_PA	0x38
#define TRAP_PER_CPU_FAULT_INFO		0x40
#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA	0xc0
#define TRAP_PER_CPU_CPU_LIST_PA	0xc8
#define TRAP_PER_CPU_TSB_HUGE		0xd0
#define TRAP_PER_CPU_TSB_HUGE_TEMP	0xd8
#define TRAP_PER_CPU_IRQ_WORKLIST_PA	0xe0
#define TRAP_PER_CPU_CPU_MONDO_QMASK	0xe8
#define TRAP_PER_CPU_DEV_MONDO_QMASK	0xec
#define TRAP_PER_CPU_RESUM_QMASK	0xf0
#define TRAP_PER_CPU_NONRESUM_QMASK	0xf4

#define TRAP_BLOCK_SZ_SHIFT		8

#include <asm/scratchpad.h>

#define __GET_CPUID(REG)				\
	/* Spitfire implementation (default). */	\
661:	ldxa		[%g0] ASI_UPA_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	 and		REG, 0x1f, REG;			\
	nop;						\
	.section	.cpuid_patch, "ax";		\
	/* Instruction location. */			\
	.word		661b;				\
	/* Cheetah Safari implementation. */		\
	ldxa		[%g0] ASI_SAFARI_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x3ff, REG;		\
	nop;						\
	/* Cheetah JBUS implementation. */		\
	ldxa		[%g0] ASI_JBUS_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x1f, REG;			\
	nop;						\
	/* Starfire implementation. */			\
	sethi		%hi(0x1fff40000d0 >> 9), REG;	\
	sllx		REG, 9, REG;			\
	or		REG, 0xd0, REG;			\
	lduwa		[REG] ASI_PHYS_BYPASS_EC_E, REG;\
	/* sun4v implementation. */			\
	mov		SCRATCHPAD_CPUID, REG;		\
	ldxa		[REG] ASI_SCRATCHPAD, REG;	\
	nop;						\
	nop;						\
	.previous;

#ifdef CONFIG_SMP

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	__GET_CPUID(TMP)			\
	sethi	%hi(trap_block), DEST;		\
	sllx	TMP, TRAP_BLOCK_SZ_SHIFT, TMP;	\
	or	DEST, %lo(trap_block), DEST;	\
	add	DEST, TMP, DEST;		\

/* Clobbers TMP, current address space PGD phys address into DEST.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;

/* Clobbers TMP, loads DEST with current thread info pointer.  */
#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* Given the current thread info pointer in THR, load the per-cpu
 * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 * clobbered.
 *
 * You absolutely cannot use DEST as a temporary in this code.  The
 * reason is that traps can happen during execution, and return from
 * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 * the calculations done by the macro mid-stream.
 */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)	\
	lduh	[THR + TI_CPU], REG1;			\
	sethi	%hi(__per_cpu_shift), REG3;		\
	sethi	%hi(__per_cpu_base), REG2;		\
	ldx	[REG3 + %lo(__per_cpu_shift)], REG3;	\
	ldx	[REG2 + %lo(__per_cpu_base)], REG2;	\
	sllx	REG1, REG3, REG3;			\
	add	REG3, REG2, DEST;

#else

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	sethi	%hi(trap_block), DEST;		\
	or	DEST, %lo(trap_block), DEST;	\

/* Uniprocessor versions, we know the cpuid is zero.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;

#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)

#endif /* !(CONFIG_SMP) */

#endif /* _SPARC64_CPUDATA_H */
Commit	Line	Data
f5e706ad SR	1	/* cpudata.h: Per-cpu parameters.
	2	*
	3	* Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
	4	*/
	5
	6	#ifndef _SPARC64_CPUDATA_H
	7	#define _SPARC64_CPUDATA_H
	8
	9	#include <asm/hypervisor.h>
	10	#include <asm/asi.h>
	11
	12	#ifndef __ASSEMBLY__
	13
	14	#include <linux/percpu.h>
	15	#include <linux/threads.h>
	16
	17	typedef struct {
	18	/* Dcache line 1 */
	19	unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
	20	unsigned int __pad0;
	21	unsigned long clock_tick; /* %tick's per second */
	22	unsigned long __pad;
	23	unsigned int __pad1;
	24	unsigned int __pad2;
	25
	26	/* Dcache line 2, rarely used */
	27	unsigned int dcache_size;
	28	unsigned int dcache_line_size;
	29	unsigned int icache_size;
	30	unsigned int icache_line_size;
	31	unsigned int ecache_size;
	32	unsigned int ecache_line_size;
	33	int core_id;
	34	int proc_id;
	35	} cpuinfo_sparc;
	36
	37	DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
	38	#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
	39	#define local_cpu_data() __get_cpu_var(__cpu_data)
	40
	41	/* Trap handling code needs to get at a few critical values upon
	42	* trap entry and to process TSB misses. These cannot be in the
	43	* per_cpu() area as we really need to lock them into the TLB and
	44	* thus make them part of the main kernel image. As a result we
	45	* try to make this as small as possible.
	46	*
	47	* This is padded out and aligned to 64-bytes to avoid false sharing
	48	* on SMP.
	49	*/
	50
	51	/* If you modify the size of this structure, please update
	52	* TRAP_BLOCK_SZ_SHIFT below.
	53	*/
	54	struct thread_info;
	55	struct trap_per_cpu {
	56	/* D-cache line 1: Basic thread information, cpu and device mondo queues */
	57	struct thread_info *thread;
	58	unsigned long pgd_paddr;
	59	unsigned long cpu_mondo_pa;
	60	unsigned long dev_mondo_pa;
	61
	62	/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
	63	unsigned long resum_mondo_pa;
	64	unsigned long resum_kernel_buf_pa;
65	unsigned long nonresum_mondo_pa;
66	unsigned long nonresum_kernel_buf_pa;
67
68	/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
69	struct hv_fault_status fault_info;
70
71	/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
72	unsigned long cpu_mondo_block_pa;
73	unsigned long cpu_list_pa;
74	unsigned long tsb_huge;
75	unsigned long tsb_huge_temp;
76
77	/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
78	unsigned long irq_worklist_pa;
79	unsigned int cpu_mondo_qmask;
80	unsigned int dev_mondo_qmask;
81	unsigned int resum_qmask;
82	unsigned int nonresum_qmask;
83	void *hdesc;
84	} __attribute__((aligned(64)));
85	extern struct trap_per_cpu trap_block[NR_CPUS];
86	extern void init_cur_cpu_trap(struct thread_info *);
87	extern void setup_tba(void);
88	extern int ncpus_probed;
89	extern void __init cpu_probe(void);
90	extern const struct seq_operations cpuinfo_op;
91
92	extern unsigned long real_hard_smp_processor_id(void);
93
94	struct cpuid_patch_entry {
95	unsigned int addr;
96	unsigned int cheetah_safari[4];
97	unsigned int cheetah_jbus[4];
98	unsigned int starfire[4];
99	unsigned int sun4v[4];
100	};
101	extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
102
103	struct sun4v_1insn_patch_entry {
104	unsigned int addr;
105	unsigned int insn;
106	};
107	extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
108	__sun4v_1insn_patch_end;
109
110	struct sun4v_2insn_patch_entry {
111	unsigned int addr;
112	unsigned int insns[2];
113	};
114	extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
115	__sun4v_2insn_patch_end;
116
117	#endif /* !(__ASSEMBLY__) */
118
119	#define TRAP_PER_CPU_THREAD 0x00
120	#define TRAP_PER_CPU_PGD_PADDR 0x08
121	#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
122	#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
123	#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
124	#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
125	#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
126	#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
127	#define TRAP_PER_CPU_FAULT_INFO 0x40
128	#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
129	#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
130	#define TRAP_PER_CPU_TSB_HUGE 0xd0
131	#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
132	#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0
133	#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8
134	#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec
135	#define TRAP_PER_CPU_RESUM_QMASK 0xf0
136	#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
137
138	#define TRAP_BLOCK_SZ_SHIFT 8
139
140	#include <asm/scratchpad.h>
141
142	#define __GET_CPUID(REG) \
143	/* Spitfire implementation (default). */ \
144	661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
145	srlx REG, 17, REG; \
146	and REG, 0x1f, REG; \
147	nop; \
148	.section .cpuid_patch, "ax"; \
149	/* Instruction location. */ \
150	.word 661b; \
151	/* Cheetah Safari implementation. */ \
152	ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
153	srlx REG, 17, REG; \
154	and REG, 0x3ff, REG; \
155	nop; \
156	/* Cheetah JBUS implementation. */ \
157	ldxa [%g0] ASI_JBUS_CONFIG, REG; \
158	srlx REG, 17, REG; \
159	and REG, 0x1f, REG; \
160	nop; \
161	/* Starfire implementation. */ \
162	sethi %hi(0x1fff40000d0 >> 9), REG; \
163	sllx REG, 9, REG; \
164	or REG, 0xd0, REG; \
165	lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
166	/* sun4v implementation. */ \
167	mov SCRATCHPAD_CPUID, REG; \
168	ldxa [REG] ASI_SCRATCHPAD, REG; \
169	nop; \
170	nop; \
171	.previous;
172
173	#ifdef CONFIG_SMP
174
175	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
176	__GET_CPUID(TMP) \
177	sethi %hi(trap_block), DEST; \
178	sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
179	or DEST, %lo(trap_block), DEST; \
180	add DEST, TMP, DEST; \
181
182	/* Clobbers TMP, current address space PGD phys address into DEST. */
183	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
184	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
185	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
186
187	/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
188	#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
189	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
190	add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
191
192	/* Clobbers TMP, loads DEST with current thread info pointer. */
193	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
194	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
195	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
196
197	/* Given the current thread info pointer in THR, load the per-cpu
198	* area base of the current processor into DEST. REG1, REG2, and REG3 are
199	* clobbered.
200	*
201	* You absolutely cannot use DEST as a temporary in this code. The
202	* reason is that traps can happen during execution, and return from
203	* trap will load the fully resolved DEST per-cpu base. This can corrupt
204	* the calculations done by the macro mid-stream.
205	*/
206	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
207	lduh [THR + TI_CPU], REG1; \
208	sethi %hi(__per_cpu_shift), REG3; \
209	sethi %hi(__per_cpu_base), REG2; \
210	ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
211	ldx [REG2 + %lo(__per_cpu_base)], REG2; \
212	sllx REG1, REG3, REG3; \
213	add REG3, REG2, DEST;
214
215	#else
216
217	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
218	sethi %hi(trap_block), DEST; \
219	or DEST, %lo(trap_block), DEST; \
220
221	/* Uniprocessor versions, we know the cpuid is zero. */
222	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
223	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
224	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
225
226	/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
227	#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
228	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
229	add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
230
231	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
232	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
233	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
234
235	/* No per-cpu areas on uniprocessor, so no need to load DEST. */
236	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
237
238	#endif /* !(CONFIG_SMP) */
239
240	#endif /* _SPARC64_CPUDATA_H */