Commit | Line | Data |
---|---|---|
f5e706ad SR |
1 | #ifndef __SPARC64_PCI_H |
2 | #define __SPARC64_PCI_H | |
3 | ||
4 | #ifdef __KERNEL__ | |
5 | ||
6 | #include <linux/dma-mapping.h> | |
7 | ||
8 | /* Can be used to override the logic in pci_scan_bus for skipping | |
9 | * already-configured bus numbers - to be used for buggy BIOSes | |
10 | * or architectures with incomplete PCI setup by the loader. | |
11 | */ | |
12 | #define pcibios_assign_all_busses() 0 | |
13 | #define pcibios_scan_all_fns(a, b) 0 | |
14 | ||
15 | #define PCIBIOS_MIN_IO 0UL | |
16 | #define PCIBIOS_MIN_MEM 0UL | |
17 | ||
18 | #define PCI_IRQ_NONE 0xffffffff | |
19 | ||
20 | #define PCI_CACHE_LINE_BYTES 64 | |
21 | ||
22 | static inline void pcibios_set_master(struct pci_dev *dev) | |
23 | { | |
24 | /* No special bus mastering setup handling */ | |
25 | } | |
26 | ||
27 | static inline void pcibios_penalize_isa_irq(int irq, int active) | |
28 | { | |
29 | /* We don't do dynamic PCI IRQ allocation */ | |
30 | } | |
31 | ||
32 | /* The PCI address space does not equal the physical memory | |
33 | * address space. The networking and block device layers use | |
34 | * this boolean for bounce buffer decisions. | |
35 | */ | |
36 | #define PCI_DMA_BUS_IS_PHYS (0) | |
37 | ||
38 | static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, | |
39 | dma_addr_t *dma_handle) | |
40 | { | |
41 | return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC); | |
42 | } | |
43 | ||
44 | static inline void pci_free_consistent(struct pci_dev *pdev, size_t size, | |
45 | void *vaddr, dma_addr_t dma_handle) | |
46 | { | |
47 | return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle); | |
48 | } | |
49 | ||
50 | static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, | |
51 | size_t size, int direction) | |
52 | { | |
53 | return dma_map_single(&pdev->dev, ptr, size, | |
54 | (enum dma_data_direction) direction); | |
55 | } | |
56 | ||
57 | static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr, | |
58 | size_t size, int direction) | |
59 | { | |
60 | dma_unmap_single(&pdev->dev, dma_addr, size, | |
61 | (enum dma_data_direction) direction); | |
62 | } | |
63 | ||
64 | #define pci_map_page(dev, page, off, size, dir) \ | |
65 | pci_map_single(dev, (page_address(page) + (off)), size, dir) | |
66 | #define pci_unmap_page(dev,addr,sz,dir) \ | |
67 | pci_unmap_single(dev,addr,sz,dir) | |
68 | ||
69 | /* pci_unmap_{single,page} is not a nop, thus... */ | |
70 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ | |
71 | dma_addr_t ADDR_NAME; | |
72 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | |
73 | __u32 LEN_NAME; | |
74 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | |
75 | ((PTR)->ADDR_NAME) | |
76 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | |
77 | (((PTR)->ADDR_NAME) = (VAL)) | |
78 | #define pci_unmap_len(PTR, LEN_NAME) \ | |
79 | ((PTR)->LEN_NAME) | |
80 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | |
81 | (((PTR)->LEN_NAME) = (VAL)) | |
82 | ||
83 | static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg, | |
84 | int nents, int direction) | |
85 | { | |
86 | return dma_map_sg(&pdev->dev, sg, nents, | |
87 | (enum dma_data_direction) direction); | |
88 | } | |
89 | ||
90 | static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg, | |
91 | int nents, int direction) | |
92 | { | |
93 | dma_unmap_sg(&pdev->dev, sg, nents, | |
94 | (enum dma_data_direction) direction); | |
95 | } | |
96 | ||
97 | static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, | |
98 | dma_addr_t dma_handle, | |
99 | size_t size, int direction) | |
100 | { | |
101 | dma_sync_single_for_cpu(&pdev->dev, dma_handle, size, | |
102 | (enum dma_data_direction) direction); | |
103 | } | |
104 | ||
105 | static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev, | |
106 | dma_addr_t dma_handle, | |
107 | size_t size, int direction) | |
108 | { | |
109 | /* No flushing needed to sync cpu writes to the device. */ | |
110 | } | |
111 | ||
112 | static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, | |
113 | struct scatterlist *sg, | |
114 | int nents, int direction) | |
115 | { | |
116 | dma_sync_sg_for_cpu(&pdev->dev, sg, nents, | |
117 | (enum dma_data_direction) direction); | |
118 | } | |
119 | ||
120 | static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev, | |
121 | struct scatterlist *sg, | |
122 | int nelems, int direction) | |
123 | { | |
124 | /* No flushing needed to sync cpu writes to the device. */ | |
125 | } | |
126 | ||
127 | /* Return whether the given PCI device DMA address mask can | |
128 | * be supported properly. For example, if your device can | |
129 | * only drive the low 24-bits during PCI bus mastering, then | |
130 | * you would pass 0x00ffffff as the mask to this function. | |
131 | */ | |
132 | extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); | |
133 | ||
134 | /* PCI IOMMU mapping bypass support. */ | |
135 | ||
136 | /* PCI 64-bit addressing works for all slots on all controller | |
137 | * types on sparc64. However, it requires that the device | |
138 | * can drive enough of the 64 bits. | |
139 | */ | |
140 | #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) | |
141 | #define PCI64_ADDR_BASE 0xfffc000000000000UL | |
142 | ||
8d8bb39b FT |
143 | static inline int pci_dma_mapping_error(struct pci_dev *pdev, |
144 | dma_addr_t dma_addr) | |
f5e706ad | 145 | { |
8d8bb39b | 146 | return dma_mapping_error(&pdev->dev, dma_addr); |
f5e706ad SR |
147 | } |
148 | ||
149 | #ifdef CONFIG_PCI | |
150 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | |
151 | enum pci_dma_burst_strategy *strat, | |
152 | unsigned long *strategy_parameter) | |
153 | { | |
154 | unsigned long cacheline_size; | |
155 | u8 byte; | |
156 | ||
157 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
158 | if (byte == 0) | |
159 | cacheline_size = 1024; | |
160 | else | |
161 | cacheline_size = (int) byte * 4; | |
162 | ||
163 | *strat = PCI_DMA_BURST_BOUNDARY; | |
164 | *strategy_parameter = cacheline_size; | |
165 | } | |
166 | #endif | |
167 | ||
168 | /* Return the index of the PCI controller for device PDEV. */ | |
169 | ||
170 | extern int pci_domain_nr(struct pci_bus *bus); | |
171 | static inline int pci_proc_domain(struct pci_bus *bus) | |
172 | { | |
173 | return 1; | |
174 | } | |
175 | ||
176 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
177 | ||
178 | #define HAVE_PCI_MMAP | |
179 | #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA | |
180 | #define get_pci_unmapped_area get_fb_unmapped_area | |
181 | ||
182 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
183 | enum pci_mmap_state mmap_state, | |
184 | int write_combine); | |
185 | ||
186 | extern void | |
187 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
188 | struct resource *res); | |
189 | ||
190 | extern void | |
191 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
192 | struct pci_bus_region *region); | |
193 | ||
194 | extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *); | |
195 | ||
196 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |
197 | { | |
198 | return PCI_IRQ_NONE; | |
199 | } | |
200 | ||
201 | struct device_node; | |
202 | extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev); | |
203 | ||
204 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER | |
205 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
206 | const struct resource *rsrc, | |
207 | resource_size_t *start, resource_size_t *end); | |
208 | #endif /* __KERNEL__ */ | |
209 | ||
210 | #endif /* __SPARC64_PCI_H */ |