[deliverable/linux.git] / include / asm-sparc64 / irq.h

/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
 * irq.h: IRQ registers on the 64-bit Sparc.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
 */

#ifndef _SPARC64_IRQ_H
#define _SPARC64_IRQ_H

#include <linux/config.h>
#include <linux/linkage.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <asm/pil.h>
#include <asm/ptrace.h>

struct ino_bucket;

#define MAX_IRQ_DESC_ACTION	4

struct irq_desc {
	void			(*pre_handler)(struct ino_bucket *, void *, void *);
	void			*pre_handler_arg1;
	void			*pre_handler_arg2;
	u32			action_active_mask;
	struct irqaction	action[MAX_IRQ_DESC_ACTION];
};

/* You should not mess with this directly. That's the job of irq.c.
 *
 * If you make changes here, please update hand coded assembler of
 * the vectored interrupt trap handler in entry.S -DaveM
 *
 * This is currently one DCACHE line, two buckets per L2 cache
 * line.  Keep this in mind please.
 */
struct ino_bucket {
	/* Next handler in per-CPU IRQ worklist.  We know that
	 * bucket pointers have the high 32-bits clear, so to
	 * save space we only store the bits we need.
	 */
/*0x00*/unsigned int irq_chain;

	/* Virtual interrupt number assigned to this INO.  */
/*0x04*/unsigned char virt_irq;

	/* If an IVEC arrives while irq_info is NULL, we
	 * set this to notify request_irq() about the event.
	 */
/*0x05*/unsigned char pending;

	/* Miscellaneous flags. */
/*0x06*/unsigned char flags;

	/* Currently unused.  */
/*0x07*/unsigned char __pad;

	/* Reference to IRQ descriptor for this bucket. */
/*0x08*/struct irq_desc *irq_info;

	/* Sun5 Interrupt Clear Register. */
/*0x10*/unsigned long iclr;

	/* Sun5 Interrupt Mapping Register. */
/*0x18*/unsigned long imap;

};

/* IMAP/ICLR register defines */
#define IMAP_VALID		0x80000000	/* IRQ Enabled		*/
#define IMAP_TID_UPA		0x7c000000	/* UPA TargetID		*/
#define IMAP_TID_JBUS		0x7c000000	/* JBUS TargetID	*/
#define IMAP_TID_SHIFT		26
#define IMAP_AID_SAFARI		0x7c000000	/* Safari AgentID	*/
#define IMAP_AID_SHIFT		26
#define IMAP_NID_SAFARI		0x03e00000	/* Safari NodeID	*/
#define IMAP_NID_SHIFT		21
#define IMAP_IGN		0x000007c0	/* IRQ Group Number	*/
#define IMAP_INO		0x0000003f	/* IRQ Number		*/
#define IMAP_INR		0x000007ff	/* Full interrupt number*/

#define ICLR_IDLE		0x00000000	/* Idle state		*/
#define ICLR_TRANSMIT		0x00000001	/* Transmit state	*/
#define ICLR_PENDING		0x00000003	/* Pending state	*/

/* Only 8-bits are available, be careful.  -DaveM */
#define IBF_PCI		0x02	/* PSYCHO/SABRE/SCHIZO PCI interrupt.	 */
#define IBF_ACTIVE	0x04	/* Interrupt is active and has a handler.*/
#define IBF_INPROGRESS	0x10	/* IRQ is being serviced.		 */

#define NUM_IVECS	(IMAP_INR + 1)
extern struct ino_bucket ivector_table[NUM_IVECS];

#define __irq_ino(irq) \
        (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))

#define NR_IRQS    16

#define irq_canonicalize(irq)	(irq)
extern void disable_irq(unsigned int);
#define disable_irq_nosync disable_irq
extern void enable_irq(unsigned int);
extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, unsigned char flags);
extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);

static __inline__ void set_softint(unsigned long bits)
{
	__asm__ __volatile__("wr	%0, 0x0, %%set_softint"
			     : /* No outputs */
			     : "r" (bits));
}

static __inline__ void clear_softint(unsigned long bits)
{
	__asm__ __volatile__("wr	%0, 0x0, %%clear_softint"
			     : /* No outputs */
			     : "r" (bits));
}

static __inline__ unsigned long get_softint(void)
{
	unsigned long retval;

	__asm__ __volatile__("rd	%%softint, %0"
			     : "=r" (retval));
	return retval;
}

struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);

#endif
Commit	Line	Data
1da177e4 LT	1	/* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
	2	* irq.h: IRQ registers on the 64-bit Sparc.
	3	*
	4	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
	6	*/
	7
	8	#ifndef _SPARC64_IRQ_H
	9	#define _SPARC64_IRQ_H
	10
	11	#include <linux/config.h>
	12	#include <linux/linkage.h>
	13	#include <linux/kernel.h>
	14	#include <linux/errno.h>
	15	#include <linux/interrupt.h>
	16	#include <asm/pil.h>
	17	#include <asm/ptrace.h>
	18
088dd1f8 DM	19	struct ino_bucket;
	20
	21	#define MAX_IRQ_DESC_ACTION 4
	22
	23	struct irq_desc {
	24	void (pre_handler)(struct ino_bucket , void , void );
	25	void *pre_handler_arg1;
	26	void *pre_handler_arg2;
	27	u32 action_active_mask;
	28	struct irqaction action[MAX_IRQ_DESC_ACTION];
	29	};
	30
1da177e4 LT	31	/* You should not mess with this directly. That's the job of irq.c.
	32	*
	33	* If you make changes here, please update hand coded assembler of
63b61452	34	* the vectored interrupt trap handler in entry.S -DaveM
1da177e4 LT	35	*
	36	* This is currently one DCACHE line, two buckets per L2 cache
	37	* line. Keep this in mind please.
	38	*/
	39	struct ino_bucket {
37cdcd9e	40	/* Next handler in per-CPU IRQ worklist. We know that
1da177e4 LT	41	* bucket pointers have the high 32-bits clear, so to
	42	* save space we only store the bits we need.
	43	*/
	44	/0x00/unsigned int irq_chain;
	45
37cdcd9e DM	46	/* Virtual interrupt number assigned to this INO. */
37cdcd9e DM	47	/0x04/unsigned char virt_irq;
1da177e4 LT	48
	49	/* If an IVEC arrives while irq_info is NULL, we
	50	* set this to notify request_irq() about the event.
	51	*/
	52	/0x05/unsigned char pending;
	53
	54	/* Miscellaneous flags. */
	55	/0x06/unsigned char flags;
	56
088dd1f8 DM	57	/* Currently unused. */
	58	/0x07/unsigned char __pad;
	59
	60	/* Reference to IRQ descriptor for this bucket. */
	61	/0x08/struct irq_desc *irq_info;
1da177e4 LT	62
	63	/* Sun5 Interrupt Clear Register. */
	64	/0x10/unsigned long iclr;
	65
	66	/* Sun5 Interrupt Mapping Register. */
	67	/0x18/unsigned long imap;
	68
	69	};
	70
1da177e4 LT	71	/* IMAP/ICLR register defines */
	72	#define IMAP_VALID 0x80000000 /* IRQ Enabled */
	73	#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
	74	#define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
ebd8c56c	75	#define IMAP_TID_SHIFT 26
1da177e4	76	#define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
ebd8c56c	77	#define IMAP_AID_SHIFT 26
1da177e4	78	#define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
ebd8c56c	79	#define IMAP_NID_SHIFT 21
1da177e4 LT	80	#define IMAP_IGN 0x000007c0 /* IRQ Group Number */
	81	#define IMAP_INO 0x0000003f /* IRQ Number */
	82	#define IMAP_INR 0x000007ff /* Full interrupt number*/
	83
	84	#define ICLR_IDLE 0x00000000 /* Idle state */
	85	#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
	86	#define ICLR_PENDING 0x00000003 /* Pending state */
	87
	88	/* Only 8-bits are available, be careful. -DaveM */
088dd1f8 DM	89	#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
	90	#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
	91	#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
1da177e4 LT	92
	93	#define NUM_IVECS (IMAP_INR + 1)
	94	extern struct ino_bucket ivector_table[NUM_IVECS];
	95
	96	#define __irq_ino(irq) \
	97	(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
1da177e4 LT	98	#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
	99	#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
	100
1da177e4 LT	101	#define NR_IRQS 16
	102
	103	#define irq_canonicalize(irq) (irq)
	104	extern void disable_irq(unsigned int);
	105	#define disable_irq_nosync disable_irq
	106	extern void enable_irq(unsigned int);
37cdcd9e DM	107	extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
37cdcd9e DM	108	extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, unsigned char flags);
1da177e4 LT	109	extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
1da177e4 LT	110
1da177e4 LT	111	static __inline__ void set_softint(unsigned long bits)
	112	{
	113	__asm__ __volatile__("wr %0, 0x0, %%set_softint"
	114	: /* No outputs */
	115	: "r" (bits));
	116	}
	117
	118	static __inline__ void clear_softint(unsigned long bits)
	119	{
	120	__asm__ __volatile__("wr %0, 0x0, %%clear_softint"
	121	: /* No outputs */
	122	: "r" (bits));
	123	}
	124
	125	static __inline__ unsigned long get_softint(void)
	126	{
	127	unsigned long retval;
	128
	129	__asm__ __volatile__("rd %%softint, %0"
	130	: "=r" (retval));
	131	return retval;
	132	}
	133
	134	struct irqaction;
	135	struct pt_regs;
	136	int handle_IRQ_event(unsigned int, struct pt_regs , struct irqaction );
	137
	138	#endif