[deliverable/linux.git] / include / asm-sparc64 / pbm.h

/* pbm.h: UltraSparc PCI controller software state.
 *
 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
 */

#ifndef __SPARC64_PBM_H
#define __SPARC64_PBM_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/msi.h>

#include <asm/io.h>
#include <asm/page.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/of_device.h>
#include <asm/iommu.h>

/* The abstraction used here is that there are PCI controllers,
 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
 * underneath.  Each PCI bus module uses an IOMMU (shared by both
 * PBMs of a controller, or per-PBM), and if a streaming buffer
 * is present, each PCI bus module has it's own. (ie. the IOMMU
 * might be shared between PBMs, the STC is never shared)
 * Furthermore, each PCI bus module controls it's own autonomous
 * PCI bus.
 */

extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);

#define PCI_STC_FLUSHFLAG_INIT(STC) \
	(*((STC)->strbuf_flushflag) = 0UL)
#define PCI_STC_FLUSHFLAG_SET(STC) \
	(*((STC)->strbuf_flushflag) != 0UL)

/* There can be quite a few ranges and interrupt maps on a PCI
 * segment.  Thus...
 */
#define PROM_PCIRNG_MAX		64
#define PROM_PCIIMAP_MAX	64

struct pci_controller_info;

struct pci_pbm_info {
	/* PCI controller we sit under. */
	struct pci_controller_info	*parent;

	/* Physical address base of controller registers. */
	unsigned long			controller_regs;

	/* Physical address base of PBM registers. */
	unsigned long			pbm_regs;

	/* Physical address of DMA sync register, if any.  */
	unsigned long			sync_reg;

	/* Opaque 32-bit system bus Port ID. */
	u32				portid;

	/* Opaque 32-bit handle used for hypervisor calls.  */
	u32				devhandle;

	/* Chipset version information. */
	int				chip_type;
#define PBM_CHIP_TYPE_SABRE		1
#define PBM_CHIP_TYPE_PSYCHO		2
#define PBM_CHIP_TYPE_SCHIZO		3
#define PBM_CHIP_TYPE_SCHIZO_PLUS	4
#define PBM_CHIP_TYPE_TOMATILLO		5
	int				chip_version;
	int				chip_revision;

	/* Name used for top-level resources. */
	char				*name;

	/* OBP specific information. */
	struct device_node		*prom_node;
	u64				ino_bitmap;

	/* PBM I/O and Memory space resources. */
	struct resource			io_space;
	struct resource			mem_space;

	/* Base of PCI Config space, can be per-PBM or shared. */
	unsigned long			config_space;

	/* State of 66MHz capabilities on this PBM. */
	int				is_66mhz_capable;
	int				all_devs_66mhz;

#ifdef CONFIG_PCI_MSI
	/* MSI info.  */
	u32				msiq_num;
	u32				msiq_ent_count;
	u32				msiq_first;
	u32				msiq_first_devino;
	u32				msi_num;
	u32				msi_first;
	u32				msi_data_mask;
	u32				msix_data_width;
	u64				msi32_start;
	u64				msi64_start;
	u32				msi32_len;
	u32				msi64_len;
	void				*msi_queues;
	unsigned long			*msi_bitmap;
#endif /* !(CONFIG_PCI_MSI) */

	/* This PBM's streaming buffer. */
	struct strbuf			stc;

	/* IOMMU state, potentially shared by both PBM segments. */
	struct iommu			*iommu;

	/* Now things for the actual PCI bus probes. */
	unsigned int			pci_first_busno;
	unsigned int			pci_last_busno;
	struct pci_bus			*pci_bus;
};

struct pci_controller_info {
	/* List of all PCI controllers. */
	struct pci_controller_info	*next;

	/* Each controller gets a unique index, used mostly for
	 * error logging purposes.
	 */
	int				index;

	/* The PCI bus modules controlled by us. */
	struct pci_pbm_info		pbm_A;
	struct pci_pbm_info		pbm_B;

	/* Operations which are controller specific. */
	void (*scan_bus)(struct pci_controller_info *);

#ifdef CONFIG_PCI_MSI
	int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
			     struct msi_desc *entry);
	void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
#endif

	/* Now things for the actual PCI bus probes. */
	struct pci_ops			*pci_ops;
};

#endif /* !(__SPARC64_PBM_H) */
Commit	Line	Data
16ce82d8	1	/* pbm.h: UltraSparc PCI controller software state.
1da177e4	2	*
16ce82d8	3	* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	*/
	5
	6	#ifndef __SPARC64_PBM_H
	7	#define __SPARC64_PBM_H
	8
	9	#include <linux/types.h>
	10	#include <linux/pci.h>
	11	#include <linux/ioport.h>
	12	#include <linux/spinlock.h>
35a17eb6	13	#include <linux/msi.h>
1da177e4 LT	14
	15	#include <asm/io.h>
	16	#include <asm/page.h>
	17	#include <asm/oplib.h>
e87dc350	18	#include <asm/prom.h>
2b1e5978	19	#include <asm/of_device.h>
7c963ad1	20	#include <asm/iommu.h>
1da177e4 LT	21
	22	/* The abstraction used here is that there are PCI controllers,
	23	* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
	24	* underneath. Each PCI bus module uses an IOMMU (shared by both
	25	* PBMs of a controller, or per-PBM), and if a streaming buffer
	26	* is present, each PCI bus module has it's own. (ie. the IOMMU
	27	* might be shared between PBMs, the STC is never shared)
	28	* Furthermore, each PCI bus module controls it's own autonomous
	29	* PCI bus.
	30	*/
	31
16ce82d8	32	extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
1da177e4 LT	33
	34	#define PCI_STC_FLUSHFLAG_INIT(STC) \
	35	(*((STC)->strbuf_flushflag) = 0UL)
	36	#define PCI_STC_FLUSHFLAG_SET(STC) \
	37	(*((STC)->strbuf_flushflag) != 0UL)
	38
	39	/* There can be quite a few ranges and interrupt maps on a PCI
	40	* segment. Thus...
	41	*/
	42	#define PROM_PCIRNG_MAX 64
	43	#define PROM_PCIIMAP_MAX 64
	44
16ce82d8 DM	45	struct pci_controller_info;
16ce82d8 DM	46
1da177e4 LT	47	struct pci_pbm_info {
	48	/* PCI controller we sit under. */
	49	struct pci_controller_info *parent;
	50
	51	/* Physical address base of controller registers. */
	52	unsigned long controller_regs;
	53
	54	/* Physical address base of PBM registers. */
	55	unsigned long pbm_regs;
	56
bb6743f4 DM	57	/* Physical address of DMA sync register, if any. */
	58	unsigned long sync_reg;
	59
1da177e4 LT	60	/* Opaque 32-bit system bus Port ID. */
	61	u32 portid;
	62
bade5622 DM	63	/* Opaque 32-bit handle used for hypervisor calls. */
	64	u32 devhandle;
	65
1da177e4 LT	66	/* Chipset version information. */
	67	int chip_type;
	68	#define PBM_CHIP_TYPE_SABRE 1
	69	#define PBM_CHIP_TYPE_PSYCHO 2
	70	#define PBM_CHIP_TYPE_SCHIZO 3
	71	#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
	72	#define PBM_CHIP_TYPE_TOMATILLO 5
	73	int chip_version;
	74	int chip_revision;
	75
	76	/* Name used for top-level resources. */
e87dc350	77	char *name;
1da177e4 LT	78
1da177e4 LT	79	/* OBP specific information. */
e87dc350	80	struct device_node *prom_node;
1da177e4 LT	81	u64 ino_bitmap;
	82
	83	/* PBM I/O and Memory space resources. */
	84	struct resource io_space;
	85	struct resource mem_space;
	86
	87	/* Base of PCI Config space, can be per-PBM or shared. */
	88	unsigned long config_space;
	89
	90	/* State of 66MHz capabilities on this PBM. */
	91	int is_66mhz_capable;
	92	int all_devs_66mhz;
	93
35a17eb6 DM	94	#ifdef CONFIG_PCI_MSI
	95	/* MSI info. */
	96	u32 msiq_num;
	97	u32 msiq_ent_count;
	98	u32 msiq_first;
	99	u32 msiq_first_devino;
	100	u32 msi_num;
	101	u32 msi_first;
	102	u32 msi_data_mask;
	103	u32 msix_data_width;
	104	u64 msi32_start;
	105	u64 msi64_start;
	106	u32 msi32_len;
	107	u32 msi64_len;
	108	void *msi_queues;
	109	unsigned long *msi_bitmap;
	110	#endif /* !(CONFIG_PCI_MSI) */
	111
1da177e4	112	/* This PBM's streaming buffer. */
16ce82d8	113	struct strbuf stc;
1da177e4 LT	114
1da177e4 LT	115	/* IOMMU state, potentially shared by both PBM segments. */
16ce82d8	116	struct iommu *iommu;
1da177e4	117
1da177e4 LT	118	/* Now things for the actual PCI bus probes. */
	119	unsigned int pci_first_busno;
	120	unsigned int pci_last_busno;
	121	struct pci_bus *pci_bus;
	122	};
	123
	124	struct pci_controller_info {
	125	/* List of all PCI controllers. */
	126	struct pci_controller_info *next;
	127
	128	/* Each controller gets a unique index, used mostly for
	129	* error logging purposes.
	130	*/
	131	int index;
	132
1da177e4 LT	133	/* The PCI bus modules controlled by us. */
	134	struct pci_pbm_info pbm_A;
	135	struct pci_pbm_info pbm_B;
	136
	137	/* Operations which are controller specific. */
	138	void (scan_bus)(struct pci_controller_info );
1da177e4	139
35a17eb6 DM	140	#ifdef CONFIG_PCI_MSI
	141	int (setup_msi_irq)(unsigned int virt_irq_p, struct pci_dev *pdev,
	142	struct msi_desc *entry);
	143	void (teardown_msi_irq)(unsigned int virt_irq, struct pci_dev pdev);
	144	#endif
	145
1da177e4 LT	146	/* Now things for the actual PCI bus probes. */
1da177e4 LT	147	struct pci_ops *pci_ops;
1da177e4 LT	148	};
1da177e4 LT	149
1da177e4	150	#endif /* !(__SPARC64_PBM_H) */