[deliverable/linux.git] / include / asm-sparc64 / pbm.h

/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
 * pbm.h: UltraSparc PCI controller software state.
 *
 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
 */

#ifndef __SPARC64_PBM_H
#define __SPARC64_PBM_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <asm/page.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/iommu.h>

/* The abstraction used here is that there are PCI controllers,
 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
 * underneath.  Each PCI bus module uses an IOMMU (shared by both
 * PBMs of a controller, or per-PBM), and if a streaming buffer
 * is present, each PCI bus module has it's own. (ie. the IOMMU
 * might be shared between PBMs, the STC is never shared)
 * Furthermore, each PCI bus module controls it's own autonomous
 * PCI bus.
 */

struct pci_controller_info;

/* This contains the software state necessary to drive a PCI
 * controller's IOMMU.
 */
struct pci_iommu_arena {
	unsigned long	*map;
	unsigned int	hint;
	unsigned int	limit;
};

struct pci_iommu {
	/* This protects the controller's IOMMU and all
	 * streaming buffers underneath.
	 */
	spinlock_t	lock;

	struct pci_iommu_arena arena;

	/* IOMMU page table, a linear array of ioptes. */
	iopte_t		*page_table;		/* The page table itself. */

	/* Base PCI memory space address where IOMMU mappings
	 * begin.
	 */
	u32		page_table_map_base;

	/* IOMMU Controller Registers */
	unsigned long	iommu_control;		/* IOMMU control register */
	unsigned long	iommu_tsbbase;		/* IOMMU page table base register */
	unsigned long	iommu_flush;		/* IOMMU page flush register */
	unsigned long	iommu_ctxflush;		/* IOMMU context flush register */

	/* This is a register in the PCI controller, which if
	 * read will have no side-effects but will guarantee
	 * completion of all previous writes into IOMMU/STC.
	 */
	unsigned long	write_complete_reg;

	/* In order to deal with some buggy third-party PCI bridges that
	 * do wrong prefetching, we never mark valid mappings as invalid.
	 * Instead we point them at this dummy page.
	 */
	unsigned long	dummy_page;
	unsigned long	dummy_page_pa;

	/* CTX allocation. */
	unsigned long ctx_lowest_free;
	unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];

	/* Here a PCI controller driver describes the areas of
	 * PCI memory space where DMA to/from physical memory
	 * are addressed.  Drivers interrogate the PCI layer
	 * if their device has addressing limitations.  They
	 * do so via pci_dma_supported, and pass in a mask of
	 * DMA address bits their device can actually drive.
	 *
	 * The test for being usable is:
	 * 	(device_mask & dma_addr_mask) == dma_addr_mask
	 */
	u32 dma_addr_mask;
};

extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);

/* This describes a PCI bus module's streaming buffer. */
struct pci_strbuf {
	int		strbuf_enabled;		/* Present and using it? */

	/* Streaming Buffer Control Registers */
	unsigned long	strbuf_control;		/* STC control register */
	unsigned long	strbuf_pflush;		/* STC page flush register */
	unsigned long	strbuf_fsync;		/* STC flush synchronization reg */
	unsigned long	strbuf_ctxflush;	/* STC context flush register */
	unsigned long	strbuf_ctxmatch_base;	/* STC context flush match reg */
	unsigned long	strbuf_flushflag_pa;	/* Physical address of flush flag */
	volatile unsigned long *strbuf_flushflag; /* The flush flag itself */

	/* And this is the actual flush flag area.
	 * We allocate extra because the chips require
	 * a 64-byte aligned area.
	 */
	volatile unsigned long	__flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
};

#define PCI_STC_FLUSHFLAG_INIT(STC) \
	(*((STC)->strbuf_flushflag) = 0UL)
#define PCI_STC_FLUSHFLAG_SET(STC) \
	(*((STC)->strbuf_flushflag) != 0UL)

/* There can be quite a few ranges and interrupt maps on a PCI
 * segment.  Thus...
 */
#define PROM_PCIRNG_MAX		64
#define PROM_PCIIMAP_MAX	64

struct pci_pbm_info {
	/* PCI controller we sit under. */
	struct pci_controller_info	*parent;

	/* Physical address base of controller registers. */
	unsigned long			controller_regs;

	/* Physical address base of PBM registers. */
	unsigned long			pbm_regs;

	/* Physical address of DMA sync register, if any.  */
	unsigned long			sync_reg;

	/* Opaque 32-bit system bus Port ID. */
	u32				portid;

	/* Opaque 32-bit handle used for hypervisor calls.  */
	u32				devhandle;

	/* Chipset version information. */
	int				chip_type;
#define PBM_CHIP_TYPE_SABRE		1
#define PBM_CHIP_TYPE_PSYCHO		2
#define PBM_CHIP_TYPE_SCHIZO		3
#define PBM_CHIP_TYPE_SCHIZO_PLUS	4
#define PBM_CHIP_TYPE_TOMATILLO		5
	int				chip_version;
	int				chip_revision;

	/* Name used for top-level resources. */
	char				*name;

	/* OBP specific information. */
	struct device_node		*prom_node;
	struct linux_prom_pci_ranges	*pbm_ranges;
	int				num_pbm_ranges;
	struct linux_prom_pci_intmap	*pbm_intmap;
	int				num_pbm_intmap;
	struct linux_prom_pci_intmask	*pbm_intmask;
	u64				ino_bitmap;

	/* PBM I/O and Memory space resources. */
	struct resource			io_space;
	struct resource			mem_space;

	/* Base of PCI Config space, can be per-PBM or shared. */
	unsigned long			config_space;

	/* State of 66MHz capabilities on this PBM. */
	int				is_66mhz_capable;
	int				all_devs_66mhz;

	/* This PBM's streaming buffer. */
	struct pci_strbuf		stc;

	/* IOMMU state, potentially shared by both PBM segments. */
	struct pci_iommu		*iommu;

	/* PCI slot mapping. */
	unsigned int			pci_first_slot;

	/* Now things for the actual PCI bus probes. */
	unsigned int			pci_first_busno;
	unsigned int			pci_last_busno;
	struct pci_bus			*pci_bus;
};

struct pci_controller_info {
	/* List of all PCI controllers. */
	struct pci_controller_info	*next;

	/* Each controller gets a unique index, used mostly for
	 * error logging purposes.
	 */
	int				index;

	/* Do the PBMs both exist in the same PCI domain? */
	int				pbms_same_domain;

	/* The PCI bus modules controlled by us. */
	struct pci_pbm_info		pbm_A;
	struct pci_pbm_info		pbm_B;

	/* Operations which are controller specific. */
	void (*scan_bus)(struct pci_controller_info *);
	unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
	void (*base_address_update)(struct pci_dev *, int);
	void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);

	/* Now things for the actual PCI bus probes. */
	struct pci_ops			*pci_ops;
	unsigned int			pci_first_busno;
	unsigned int			pci_last_busno;

	void				*starfire_cookie;
};

/* PCI devices which are not bridges have this placed in their pci_dev
 * sysdata member.  This makes OBP aware PCI device drivers easier to
 * code.
 */
struct pcidev_cookie {
	struct pci_pbm_info		*pbm;
	char				prom_name[64];
	int				prom_node;
	struct linux_prom_pci_registers	prom_regs[PROMREG_MAX];
	int num_prom_regs;
	struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
	int num_prom_assignments;
};

/* Currently these are the same across all PCI controllers
 * we support.  Someday they may not be...
 */
#define PCI_IRQ_IGN	0x000007c0	/* Interrupt Group Number */
#define PCI_IRQ_INO	0x0000003f	/* Interrupt Number */

#endif /* !(__SPARC64_PBM_H) */
Commit	Line	Data
1da177e4 LT	1	/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
	2	* pbm.h: UltraSparc PCI controller software state.
	3	*
	4	* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
	5	*/
	6
	7	#ifndef __SPARC64_PBM_H
	8	#define __SPARC64_PBM_H
	9
	10	#include <linux/types.h>
	11	#include <linux/pci.h>
	12	#include <linux/ioport.h>
	13	#include <linux/spinlock.h>
	14
	15	#include <asm/io.h>
	16	#include <asm/page.h>
	17	#include <asm/oplib.h>
e87dc350	18	#include <asm/prom.h>
7c963ad1	19	#include <asm/iommu.h>
1da177e4 LT	20
	21	/* The abstraction used here is that there are PCI controllers,
	22	* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
	23	* underneath. Each PCI bus module uses an IOMMU (shared by both
	24	* PBMs of a controller, or per-PBM), and if a streaming buffer
	25	* is present, each PCI bus module has it's own. (ie. the IOMMU
	26	* might be shared between PBMs, the STC is never shared)
	27	* Furthermore, each PCI bus module controls it's own autonomous
	28	* PCI bus.
	29	*/
	30
1da177e4 LT	31	struct pci_controller_info;
	32
	33	/* This contains the software state necessary to drive a PCI
	34	* controller's IOMMU.
	35	*/
688cb30b DM	36	struct pci_iommu_arena {
	37	unsigned long *map;
	38	unsigned int hint;
	39	unsigned int limit;
	40	};
	41
1da177e4 LT	42	struct pci_iommu {
	43	/* This protects the controller's IOMMU and all
	44	* streaming buffers underneath.
	45	*/
	46	spinlock_t lock;
	47
688cb30b DM	48	struct pci_iommu_arena arena;
688cb30b DM	49
1da177e4 LT	50	/* IOMMU page table, a linear array of ioptes. */
1da177e4 LT	51	iopte_t page_table; / The page table itself. */
1da177e4 LT	52
	53	/* Base PCI memory space address where IOMMU mappings
	54	* begin.
	55	*/
	56	u32 page_table_map_base;
	57
	58	/* IOMMU Controller Registers */
	59	unsigned long iommu_control; /* IOMMU control register */
	60	unsigned long iommu_tsbbase; /* IOMMU page table base register */
	61	unsigned long iommu_flush; /* IOMMU page flush register */
	62	unsigned long iommu_ctxflush; /* IOMMU context flush register */
	63
	64	/* This is a register in the PCI controller, which if
	65	* read will have no side-effects but will guarantee
	66	* completion of all previous writes into IOMMU/STC.
	67	*/
	68	unsigned long write_complete_reg;
	69
1da177e4 LT	70	/* In order to deal with some buggy third-party PCI bridges that
	71	* do wrong prefetching, we never mark valid mappings as invalid.
	72	* Instead we point them at this dummy page.
	73	*/
	74	unsigned long dummy_page;
	75	unsigned long dummy_page_pa;
	76
7c963ad1 DM	77	/* CTX allocation. */
	78	unsigned long ctx_lowest_free;
	79	unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
	80
1da177e4 LT	81	/* Here a PCI controller driver describes the areas of
	82	* PCI memory space where DMA to/from physical memory
	83	* are addressed. Drivers interrogate the PCI layer
	84	* if their device has addressing limitations. They
	85	* do so via pci_dma_supported, and pass in a mask of
	86	* DMA address bits their device can actually drive.
	87	*
	88	* The test for being usable is:
	89	* (device_mask & dma_addr_mask) == dma_addr_mask
	90	*/
	91	u32 dma_addr_mask;
	92	};
	93
51e85136	94	extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
1da177e4 LT	95
	96	/* This describes a PCI bus module's streaming buffer. */
	97	struct pci_strbuf {
	98	int strbuf_enabled; /* Present and using it? */
	99
	100	/* Streaming Buffer Control Registers */
	101	unsigned long strbuf_control; /* STC control register */
	102	unsigned long strbuf_pflush; /* STC page flush register */
	103	unsigned long strbuf_fsync; /* STC flush synchronization reg */
	104	unsigned long strbuf_ctxflush; /* STC context flush register */
	105	unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
	106	unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
	107	volatile unsigned long strbuf_flushflag; / The flush flag itself */
	108
	109	/* And this is the actual flush flag area.
	110	* We allocate extra because the chips require
	111	* a 64-byte aligned area.
	112	*/
	113	volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
	114	};
	115
	116	#define PCI_STC_FLUSHFLAG_INIT(STC) \
	117	(*((STC)->strbuf_flushflag) = 0UL)
	118	#define PCI_STC_FLUSHFLAG_SET(STC) \
	119	(*((STC)->strbuf_flushflag) != 0UL)
	120
	121	/* There can be quite a few ranges and interrupt maps on a PCI
	122	* segment. Thus...
	123	*/
	124	#define PROM_PCIRNG_MAX 64
	125	#define PROM_PCIIMAP_MAX 64
	126
	127	struct pci_pbm_info {
	128	/* PCI controller we sit under. */
	129	struct pci_controller_info *parent;
	130
	131	/* Physical address base of controller registers. */
	132	unsigned long controller_regs;
	133
	134	/* Physical address base of PBM registers. */
	135	unsigned long pbm_regs;
	136
bb6743f4 DM	137	/* Physical address of DMA sync register, if any. */
	138	unsigned long sync_reg;
	139
1da177e4 LT	140	/* Opaque 32-bit system bus Port ID. */
	141	u32 portid;
	142
bade5622 DM	143	/* Opaque 32-bit handle used for hypervisor calls. */
	144	u32 devhandle;
	145
1da177e4 LT	146	/* Chipset version information. */
	147	int chip_type;
	148	#define PBM_CHIP_TYPE_SABRE 1
	149	#define PBM_CHIP_TYPE_PSYCHO 2
	150	#define PBM_CHIP_TYPE_SCHIZO 3
	151	#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
	152	#define PBM_CHIP_TYPE_TOMATILLO 5
	153	int chip_version;
	154	int chip_revision;
	155
	156	/* Name used for top-level resources. */
e87dc350	157	char *name;
1da177e4 LT	158
1da177e4 LT	159	/* OBP specific information. */
e87dc350 DM	160	struct device_node *prom_node;
e87dc350 DM	161	struct linux_prom_pci_ranges *pbm_ranges;
1da177e4	162	int num_pbm_ranges;
e87dc350	163	struct linux_prom_pci_intmap *pbm_intmap;
1da177e4	164	int num_pbm_intmap;
e87dc350	165	struct linux_prom_pci_intmask *pbm_intmask;
1da177e4 LT	166	u64 ino_bitmap;
	167
	168	/* PBM I/O and Memory space resources. */
	169	struct resource io_space;
	170	struct resource mem_space;
	171
	172	/* Base of PCI Config space, can be per-PBM or shared. */
	173	unsigned long config_space;
	174
	175	/* State of 66MHz capabilities on this PBM. */
	176	int is_66mhz_capable;
	177	int all_devs_66mhz;
	178
	179	/* This PBM's streaming buffer. */
	180	struct pci_strbuf stc;
	181
	182	/* IOMMU state, potentially shared by both PBM segments. */
	183	struct pci_iommu *iommu;
	184
	185	/* PCI slot mapping. */
	186	unsigned int pci_first_slot;
	187
	188	/* Now things for the actual PCI bus probes. */
	189	unsigned int pci_first_busno;
	190	unsigned int pci_last_busno;
	191	struct pci_bus *pci_bus;
	192	};
	193
	194	struct pci_controller_info {
	195	/* List of all PCI controllers. */
	196	struct pci_controller_info *next;
	197
	198	/* Each controller gets a unique index, used mostly for
	199	* error logging purposes.
	200	*/
	201	int index;
	202
	203	/* Do the PBMs both exist in the same PCI domain? */
	204	int pbms_same_domain;
	205
	206	/* The PCI bus modules controlled by us. */
	207	struct pci_pbm_info pbm_A;
	208	struct pci_pbm_info pbm_B;
	209
	210	/* Operations which are controller specific. */
	211	void (scan_bus)(struct pci_controller_info );
	212	unsigned int (irq_build)(struct pci_pbm_info , struct pci_dev *, unsigned int);
	213	void (base_address_update)(struct pci_dev , int);
	214	void (resource_adjust)(struct pci_dev , struct resource , struct resource );
	215
	216	/* Now things for the actual PCI bus probes. */
	217	struct pci_ops *pci_ops;
	218	unsigned int pci_first_busno;
	219	unsigned int pci_last_busno;
	220
	221	void *starfire_cookie;
	222	};
	223
	224	/* PCI devices which are not bridges have this placed in their pci_dev
	225	* sysdata member. This makes OBP aware PCI device drivers easier to
	226	* code.
	227	*/
	228	struct pcidev_cookie {
	229	struct pci_pbm_info *pbm;
230	char prom_name[64];
231	int prom_node;
232	struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
233	int num_prom_regs;
234	struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
235	int num_prom_assignments;
236	};
237
238	/* Currently these are the same across all PCI controllers
239	* we support. Someday they may not be...
240	*/
241	#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
242	#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
243
244	#endif /* !(__SPARC64_PBM_H) */