projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge by hand from Linus' tree.
[deliverable/linux.git] / include / asm-sparc64 / pgtable.h
CommitLineData
1da177e4
LT		 1/* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef _SPARC64_PGTABLE_H
9#define _SPARC64_PGTABLE_H
10
11/* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15#include <asm-generic/pgtable-nopud.h>
16
17#include <linux/config.h>
18#include <linux/compiler.h>
19#include <asm/types.h>
20#include <asm/spitfire.h>
21#include <asm/asi.h>
22#include <asm/system.h>
23#include <asm/page.h>
24#include <asm/processor.h>
25#include <asm/const.h>
26
729b4f7d
DM		 27/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
28 * The page copy blockops can use 0x2000000 to 0x10000000.
1da177e4 29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
729b4f7d
DM		 30 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space,
32 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
1da177e4
LT		 33 * There is a single static kernel PMD which maps from 0x0 to address
34 * 0x400000000.
35 */
729b4f7d
DM		 36#define TLBTEMP_BASE _AC(0x0000000002000000,UL)
37#define MODULES_VADDR _AC(0x0000000010000000,UL)
38#define MODULES_LEN _AC(0x00000000e0000000,UL)
39#define MODULES_END _AC(0x00000000f0000000,UL)
1da177e4
LT		 40#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
41#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
729b4f7d
DM		 42#define VMALLOC_START _AC(0x0000000100000000,UL)
43#define VMALLOC_END _AC(0x0000000200000000,UL)
1da177e4
LT		 44
45/* XXX All of this needs to be rethought so we can take advantage
46 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
47 * XXX in the middle like on spitfire. -DaveM
48 */
49/*
50 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
51 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
52 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
53 * table is a single page long). The next higher PMD_BITS determine pmd#
54 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
55 * since the pmd entries are 4 bytes, and each pmd page is a single page
56 * long). Finally, the higher few bits determine pgde#.
57 */
58
59/* PMD_SHIFT determines the size of the area a second-level page
60 * table can map
61 */
62#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
56425306 63#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
1da177e4
LT		 64#define PMD_MASK (~(PMD_SIZE-1))
65#define PMD_BITS (PAGE_SHIFT - 2)
66
67/* PGDIR_SHIFT determines what a third-level page table entry can map */
68#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
56425306 69#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
1da177e4
LT		 70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71#define PGDIR_BITS (PAGE_SHIFT - 2)
72
73#ifndef __ASSEMBLY__
74
75#include <linux/sched.h>
76
77/* Entries per page directory level. */
78#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
79#define PTRS_PER_PMD (1UL << PMD_BITS)
80#define PTRS_PER_PGD (1UL << PGDIR_BITS)
81
82/* Kernel has a separate 44bit address space. */
d455a369 83#define FIRST_USER_ADDRESS 0
1da177e4
LT		 84
85#define pte_ERROR(e) __builtin_trap()
86#define pmd_ERROR(e) __builtin_trap()
87#define pgd_ERROR(e) __builtin_trap()
88
89#endif /* !(__ASSEMBLY__) */
90
91/* Spitfire/Cheetah TTE bits. */
92#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
93#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/
94#define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */
95#define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */
96#define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */
97#define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */
98#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
99#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
100#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
101#define _PAGE_RES1 _AC(0x0003000000000000,UL) /* Reserved */
102#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
103#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
104#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/
105#define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */
106#define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */
107#define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */
108#define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
109#define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
110#define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */
111#define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */
112#define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */
113#define _PAGE_G _AC(0x0000000000000001,UL) /* Global */
114
115/* Here are the SpitFire software bits we use in the TTE's.
116 *
117 * WARNING: If you are going to try and start using some
118 * of the soft2 bits, you will need to make
119 * modifications to the swap entry implementation.
120 * For example, one thing that could happen is that
121 * swp_entry_to_pte() would BUG_ON() if you tried
122 * to use one of the soft2 bits for _PAGE_FILE.
123 *
124 * Like other architectures, I have aliased _PAGE_FILE with
125 * _PAGE_MODIFIED. This works because _PAGE_FILE is never
126 * interpreted that way unless _PAGE_PRESENT is clear.
127 */
128#define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */
129#define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */
130#define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */
131#define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
132#define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */
133#define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */
134#define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */
135
136#if PAGE_SHIFT == 13
137#define _PAGE_SZBITS _PAGE_SZ8K
138#elif PAGE_SHIFT == 16
139#define _PAGE_SZBITS _PAGE_SZ64K
140#elif PAGE_SHIFT == 19
141#define _PAGE_SZBITS _PAGE_SZ512K
142#elif PAGE_SHIFT == 22
143#define _PAGE_SZBITS _PAGE_SZ4MB
144#else
145#error Wrong PAGE_SHIFT specified
146#endif
147
148#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
149#define _PAGE_SZHUGE _PAGE_SZ4MB
150#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
151#define _PAGE_SZHUGE _PAGE_SZ512K
152#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
153#define _PAGE_SZHUGE _PAGE_SZ64K
154#endif
155
156#define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
157
158#define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
159#define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
160#define __PRIV_BITS _PAGE_P
161
162#define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE)
163
164/* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
165#define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
166 __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC)
167
168#define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
169 __ACCESS_BITS | _PAGE_EXEC)
170
171#define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
172 __ACCESS_BITS | _PAGE_EXEC)
173
174#define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
175 __PRIV_BITS | \
176 __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC)
177
178#define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
179 _PAGE_CACHE | \
180 __ACCESS_BITS | _PAGE_WRITE)
181
182#define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
183 _PAGE_CACHE | __ACCESS_BITS)
184
185#define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
186 _PAGE_CACHE | __ACCESS_BITS)
187
188#define _PFN_MASK _PAGE_PADDR
189
190#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \
191 __ACCESS_BITS | _PAGE_E)
192
193#define __P000 PAGE_NONE
194#define __P001 PAGE_READONLY_NOEXEC
195#define __P010 PAGE_COPY_NOEXEC
196#define __P011 PAGE_COPY_NOEXEC
197#define __P100 PAGE_READONLY
198#define __P101 PAGE_READONLY
199#define __P110 PAGE_COPY
200#define __P111 PAGE_COPY
201
202#define __S000 PAGE_NONE
203#define __S001 PAGE_READONLY_NOEXEC
204#define __S010 PAGE_SHARED_NOEXEC
205#define __S011 PAGE_SHARED_NOEXEC
206#define __S100 PAGE_READONLY
207#define __S101 PAGE_READONLY
208#define __S110 PAGE_SHARED
209#define __S111 PAGE_SHARED
210
211#ifndef __ASSEMBLY__
212
213extern unsigned long phys_base;
214extern unsigned long pfn_base;
215
216extern struct page *mem_map_zero;
217#define ZERO_PAGE(vaddr) (mem_map_zero)
218
219/* PFNs are real physical page numbers. However, mem_map only begins to record
220 * per-page information starting at pfn_base. This is to handle systems where
221 * the first physical page in the machine is at some huge physical address,
222 * such as 4GB. This is common on a partitioned E10000, for example.
223 */
224
225#define pfn_pte(pfn, prot) \
226 __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS)
227#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
228
229#define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
230#define pte_page(x) pfn_to_page(pte_pfn(x))
231
232#define page_pte_prot(page, prot) mk_pte(page, prot)
233#define page_pte(page) page_pte_prot(page, __pgprot(0))
234
235static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
236{
237 pte_t __pte;
238 const unsigned long preserve_mask = (_PFN_MASK |
239 _PAGE_MODIFIED | _PAGE_ACCESSED |
240 _PAGE_CACHE | _PAGE_E |
241 _PAGE_PRESENT | _PAGE_SZBITS);
242
243 pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) |
244 (pgprot_val(new_prot) & ~preserve_mask);
245
246 return __pte;
247}
248#define pmd_set(pmdp, ptep) \
249 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
250#define pud_set(pudp, pmdp) \
251 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
252#define __pmd_page(pmd) \
253 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
254#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
255#define pud_page(pud) \
256 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
257#define pte_none(pte) (!pte_val(pte))
258#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
259#define pmd_none(pmd) (!pmd_val(pmd))
260#define pmd_bad(pmd) (0)
261#define pmd_present(pmd) (pmd_val(pmd) != 0U)
262#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
263#define pud_none(pud) (!pud_val(pud))
264#define pud_bad(pud) (0)
265#define pud_present(pud) (pud_val(pud) != 0U)
266#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
267
268/* The following only work if pte_present() is true.
269 * Undefined behaviour if not..
270 */
271#define pte_read(pte) (pte_val(pte) & _PAGE_READ)
272#define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC)
273#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
274#define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
275#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
276#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
277#define pte_rdprotect(pte) \
278 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
279#define pte_mkclean(pte) \
280 (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
281#define pte_mkold(pte) \
282 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
283
284/* Permanent address of a page. */
285#define __page_address(page) page_address(page)
286
287/* Be very careful when you change these three, they are delicate. */
288#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
289#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
290#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
63551ae0 291#define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE))
1da177e4
LT		 292
293/* to find an entry in a page-table-directory. */
294#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
295#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
296
297/* to find an entry in a kernel page-table-directory */
298#define pgd_offset_k(address) pgd_offset(&init_mm, address)
299
300/* extract the pgd cache used for optimizing the tlb miss
301 * slow path when executing 32-bit compat processes
302 */
303#define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11)
304
305/* Find an entry in the second-level page table.. */
306#define pmd_offset(pudp, address) \
307 ((pmd_t *) pud_page(*(pudp)) + \
308 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
309
310/* Find an entry in the third-level page table.. */
311#define pte_index(dir, address) \
312 ((pte_t *) __pmd_page(*(dir)) + \
313 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
314#define pte_offset_kernel pte_index
315#define pte_offset_map pte_index
316#define pte_offset_map_nested pte_index
317#define pte_unmap(pte) do { } while (0)
318#define pte_unmap_nested(pte) do { } while (0)
319
320/* Actual page table PTE updates. */
321extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
322
323static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
324{
325 pte_t orig = *ptep;
326
327 *ptep = pte;
328
329 /* It is more efficient to let flush_tlb_kernel_range()
330 * handle init_mm tlb flushes.
331 */
332 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
333 tlb_batch_add(mm, addr, ptep, orig);
334}
335
336#define pte_clear(mm,addr,ptep) \
337 set_pte_at((mm), (addr), (ptep), __pte(0UL))
338
56425306
DM		 339extern pgd_t swapper_pg_dir[2048];
340extern pmd_t swapper_low_pmd_dir[2048];
1da177e4
LT		 341
342/* These do nothing with the way I have things setup. */
343#define mmu_lockarea(vaddr, len) (vaddr)
344#define mmu_unlockarea(vaddr, len) do { } while(0)
345
346struct vm_area_struct;
347extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
348
349/* Make a non-present pseudo-TTE. */
350static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
351{
352 pte_t pte;
353 pte_val(pte) = (((page) | pgprot_val(prot) | _PAGE_E) &
354 ~(unsigned long)_PAGE_CACHE);
355 pte_val(pte) |= (((unsigned long)space) << 32);
356 return pte;
357}
358
359/* Encode and de-code a swap entry */
360#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
361#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
362#define __swp_entry(type, offset) \
363 ( (swp_entry_t) \
364 { \
365 (((long)(type) << PAGE_SHIFT) | \
366 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
367 } )
368#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
369#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
370
371/* File offset in PTE support. */
372#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
373#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
374#define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE))
375#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
376
377extern unsigned long prom_virt_to_phys(unsigned long, int *);
378
379static __inline__ unsigned long
380sun4u_get_pte (unsigned long addr)
381{
382 pgd_t *pgdp;
383 pud_t *pudp;
384 pmd_t *pmdp;
385 pte_t *ptep;
386
387 if (addr >= PAGE_OFFSET)
388 return addr & _PAGE_PADDR;
389 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
390 return prom_virt_to_phys(addr, NULL);
391 pgdp = pgd_offset_k(addr);
392 pudp = pud_offset(pgdp, addr);
393 pmdp = pmd_offset(pudp, addr);
394 ptep = pte_offset_kernel(pmdp, addr);
395 return pte_val(*ptep) & _PAGE_PADDR;
396}
397
398static __inline__ unsigned long
399__get_phys (unsigned long addr)
400{
401 return sun4u_get_pte (addr);
402}
403
404static __inline__ int
405__get_iospace (unsigned long addr)
406{
407 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
408}
409
410extern unsigned long *sparc64_valid_addr_bitmap;
411
412/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
413#define kern_addr_valid(addr) \
414 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
415
1da177e4
LT		 416extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
417 unsigned long pfn,
418 unsigned long size, pgprot_t prot);
419
d7be828e
DM		 420/* Clear virtual and physical cachability, set side-effect bit. */
421#define pgprot_noncached(prot) \
422 (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
423 _PAGE_E))
424
1da177e4
LT		 425/*
426 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
427 * its high 4 bits. These macros/functions put it there or get it from there.
428 */
429#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
430#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
431#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
432
1da177e4
LT		 433#include <asm-generic/pgtable.h>
434
435/* We provide our own get_unmapped_area to cope with VA holes for userland */
436#define HAVE_ARCH_UNMAPPED_AREA
437
438/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
439 * the largest alignment possible such that larget PTEs can be used.
440 */
441extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
442 unsigned long, unsigned long,
443 unsigned long);
444#define HAVE_ARCH_FB_UNMAPPED_AREA
445
446/*
447 * No page table caches to initialise
448 */
449#define pgtable_cache_init() do { } while (0)
450
451extern void check_pgt_cache(void);
452
453#endif /* !(__ASSEMBLY__) */
454
455#endif /* !(_SPARC64_PGTABLE_H) */
Linux kernel - Deliverables
This page took 0.085972 seconds and 5 git commands to generate.