Commit | Line | Data |
---|---|---|
77ef50a5 VN |
1 | #ifndef ASM_X86__APIC_H |
2 | #define ASM_X86__APIC_H | |
67c5fc5c TG |
3 | |
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
67c5fc5c TG |
8 | #include <asm/fixmap.h> |
9 | #include <asm/apicdef.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/system.h> | |
13c88fb5 SS |
12 | #include <asm/cpufeature.h> |
13 | #include <asm/msr.h> | |
67c5fc5c TG |
14 | |
15 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
16 | ||
67c5fc5c TG |
17 | /* |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
24 | /* | |
25 | * Define the default level of output to be very little | |
26 | * This can be turned up by using apic=verbose for more | |
27 | * information and apic=debug for _lots_ of information. | |
28 | * apic_verbosity is defined in apic.c | |
29 | */ | |
30 | #define apic_printk(v, s, a...) do { \ | |
31 | if ((v) <= apic_verbosity) \ | |
32 | printk(s, ##a); \ | |
33 | } while (0) | |
34 | ||
35 | ||
36 | extern void generic_apic_probe(void); | |
37 | ||
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
39 | ||
baa13188 | 40 | extern unsigned int apic_verbosity; |
67c5fc5c | 41 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 42 | |
3c999f14 | 43 | extern int disable_apic; |
67c5fc5c TG |
44 | /* |
45 | * Basic functions accessing APICs. | |
46 | */ | |
47 | #ifdef CONFIG_PARAVIRT | |
48 | #include <asm/paravirt.h> | |
96a388de | 49 | #else |
67c5fc5c TG |
50 | #define setup_boot_clock setup_boot_APIC_clock |
51 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 52 | #endif |
67c5fc5c | 53 | |
aa7d8e25 | 54 | extern int is_vsmp_box(void); |
2b97df06 JS |
55 | extern void xapic_wait_icr_idle(void); |
56 | extern u32 safe_xapic_wait_icr_idle(void); | |
57 | extern u64 xapic_icr_read(void); | |
58 | extern void xapic_icr_write(u32, u32); | |
59 | extern int setup_profiling_timer(unsigned int); | |
aa7d8e25 | 60 | |
1b374e4d | 61 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 62 | { |
593f4a78 | 63 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 64 | |
593f4a78 MR |
65 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
66 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
67 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
68 | } |
69 | ||
1b374e4d | 70 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
71 | { |
72 | return *((volatile u32 *)(APIC_BASE + reg)); | |
73 | } | |
74 | ||
13c88fb5 SS |
75 | static inline void native_apic_msr_write(u32 reg, u32 v) |
76 | { | |
77 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
78 | reg == APIC_LVR) | |
79 | return; | |
80 | ||
81 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
82 | } | |
83 | ||
84 | static inline u32 native_apic_msr_read(u32 reg) | |
85 | { | |
86 | u32 low, high; | |
87 | ||
88 | if (reg == APIC_DFR) | |
89 | return -1; | |
90 | ||
91 | rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); | |
92 | return low; | |
93 | } | |
94 | ||
c535b6a1 | 95 | #ifndef CONFIG_X86_32 |
6e1cb38a SS |
96 | extern int x2apic, x2apic_preenabled; |
97 | extern void check_x2apic(void); | |
98 | extern void enable_x2apic(void); | |
99 | extern void enable_IR_x2apic(void); | |
100 | extern void x2apic_icr_write(u32 low, u32 id); | |
c535b6a1 | 101 | #endif |
1b374e4d SS |
102 | |
103 | struct apic_ops { | |
104 | u32 (*read)(u32 reg); | |
105 | void (*write)(u32 reg, u32 v); | |
1b374e4d SS |
106 | u64 (*icr_read)(void); |
107 | void (*icr_write)(u32 low, u32 high); | |
108 | void (*wait_icr_idle)(void); | |
109 | u32 (*safe_wait_icr_idle)(void); | |
110 | }; | |
111 | ||
112 | extern struct apic_ops *apic_ops; | |
113 | ||
114 | #define apic_read (apic_ops->read) | |
115 | #define apic_write (apic_ops->write) | |
1b374e4d SS |
116 | #define apic_icr_read (apic_ops->icr_read) |
117 | #define apic_icr_write (apic_ops->icr_write) | |
118 | #define apic_wait_icr_idle (apic_ops->wait_icr_idle) | |
119 | #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle) | |
1b374e4d | 120 | |
67c5fc5c TG |
121 | extern int get_physical_broadcast(void); |
122 | ||
89027d35 SS |
123 | #ifdef CONFIG_X86_64 |
124 | static inline void ack_x2APIC_irq(void) | |
125 | { | |
126 | /* Docs say use 0 for future compatibility */ | |
127 | native_apic_msr_write(APIC_EOI, 0); | |
128 | } | |
129 | #endif | |
130 | ||
131 | ||
67c5fc5c TG |
132 | static inline void ack_APIC_irq(void) |
133 | { | |
134 | /* | |
0791e13f | 135 | * ack_APIC_irq() actually gets compiled as a single instruction |
67c5fc5c TG |
136 | * ... yummie. |
137 | */ | |
138 | ||
139 | /* Docs say use 0 for future compatibility */ | |
593f4a78 | 140 | apic_write(APIC_EOI, 0); |
67c5fc5c TG |
141 | } |
142 | ||
143 | extern int lapic_get_maxlvt(void); | |
144 | extern void clear_local_APIC(void); | |
145 | extern void connect_bsp_APIC(void); | |
146 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
147 | extern void disable_local_APIC(void); | |
148 | extern void lapic_shutdown(void); | |
149 | extern int verify_local_APIC(void); | |
150 | extern void cache_APIC_registers(void); | |
151 | extern void sync_Arb_IDs(void); | |
152 | extern void init_bsp_APIC(void); | |
153 | extern void setup_local_APIC(void); | |
739f33b3 | 154 | extern void end_local_APIC_setup(void); |
67c5fc5c | 155 | extern void init_apic_mappings(void); |
67c5fc5c TG |
156 | extern void setup_boot_APIC_clock(void); |
157 | extern void setup_secondary_APIC_clock(void); | |
158 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 159 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
160 | |
161 | /* | |
162 | * On 32bit this is mach-xxx local | |
163 | */ | |
164 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 165 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
166 | extern int apic_is_clustered_box(void); |
167 | #else | |
168 | static inline int apic_is_clustered_box(void) | |
169 | { | |
170 | return 0; | |
171 | } | |
67c5fc5c TG |
172 | #endif |
173 | ||
7b83dae7 RR |
174 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
175 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 176 | |
67c5fc5c TG |
177 | |
178 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
179 | static inline void lapic_shutdown(void) { } | |
180 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 181 | static inline void init_apic_mappings(void) { } |
67c5fc5c TG |
182 | |
183 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
184 | ||
77ef50a5 | 185 | #endif /* ASM_X86__APIC_H */ |