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67c5fc5c TG |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
3 | ||
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
67c5fc5c TG |
8 | #include <asm/fixmap.h> |
9 | #include <asm/apicdef.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/system.h> | |
12 | ||
13 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
14 | ||
67c5fc5c TG |
15 | /* |
16 | * Debugging macros | |
17 | */ | |
18 | #define APIC_QUIET 0 | |
19 | #define APIC_VERBOSE 1 | |
20 | #define APIC_DEBUG 2 | |
21 | ||
22 | /* | |
23 | * Define the default level of output to be very little | |
24 | * This can be turned up by using apic=verbose for more | |
25 | * information and apic=debug for _lots_ of information. | |
26 | * apic_verbosity is defined in apic.c | |
27 | */ | |
28 | #define apic_printk(v, s, a...) do { \ | |
29 | if ((v) <= apic_verbosity) \ | |
30 | printk(s, ##a); \ | |
31 | } while (0) | |
32 | ||
33 | ||
34 | extern void generic_apic_probe(void); | |
35 | ||
36 | #ifdef CONFIG_X86_LOCAL_APIC | |
37 | ||
baa13188 | 38 | extern unsigned int apic_verbosity; |
67c5fc5c | 39 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 40 | |
67c5fc5c | 41 | extern int ioapic_force; |
67c5fc5c | 42 | |
3c999f14 | 43 | extern int disable_apic; |
67c5fc5c TG |
44 | /* |
45 | * Basic functions accessing APICs. | |
46 | */ | |
47 | #ifdef CONFIG_PARAVIRT | |
48 | #include <asm/paravirt.h> | |
96a388de | 49 | #else |
67c5fc5c | 50 | #define apic_write native_apic_write |
67c5fc5c TG |
51 | #define apic_read native_apic_read |
52 | #define setup_boot_clock setup_boot_APIC_clock | |
53 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 54 | #endif |
67c5fc5c | 55 | |
aa7d8e25 RT |
56 | extern int is_vsmp_box(void); |
57 | ||
341d8854 | 58 | static inline void native_apic_write(unsigned long reg, u32 v) |
67c5fc5c | 59 | { |
593f4a78 | 60 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 61 | |
593f4a78 MR |
62 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
63 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
64 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
65 | } |
66 | ||
341d8854 | 67 | static inline u32 native_apic_read(unsigned long reg) |
67c5fc5c TG |
68 | { |
69 | return *((volatile u32 *)(APIC_BASE + reg)); | |
70 | } | |
71 | ||
72 | extern void apic_wait_icr_idle(void); | |
73 | extern u32 safe_apic_wait_icr_idle(void); | |
74 | extern int get_physical_broadcast(void); | |
75 | ||
67c5fc5c TG |
76 | static inline void ack_APIC_irq(void) |
77 | { | |
78 | /* | |
79 | * ack_APIC_irq() actually gets compiled as a single instruction: | |
80 | * - a single rmw on Pentium/82489DX | |
81 | * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC) | |
82 | * ... yummie. | |
83 | */ | |
84 | ||
85 | /* Docs say use 0 for future compatibility */ | |
593f4a78 | 86 | apic_write(APIC_EOI, 0); |
67c5fc5c TG |
87 | } |
88 | ||
89 | extern int lapic_get_maxlvt(void); | |
90 | extern void clear_local_APIC(void); | |
91 | extern void connect_bsp_APIC(void); | |
92 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
93 | extern void disable_local_APIC(void); | |
94 | extern void lapic_shutdown(void); | |
95 | extern int verify_local_APIC(void); | |
96 | extern void cache_APIC_registers(void); | |
97 | extern void sync_Arb_IDs(void); | |
98 | extern void init_bsp_APIC(void); | |
99 | extern void setup_local_APIC(void); | |
739f33b3 | 100 | extern void end_local_APIC_setup(void); |
67c5fc5c | 101 | extern void init_apic_mappings(void); |
67c5fc5c TG |
102 | extern void setup_boot_APIC_clock(void); |
103 | extern void setup_secondary_APIC_clock(void); | |
104 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 105 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
106 | |
107 | /* | |
108 | * On 32bit this is mach-xxx local | |
109 | */ | |
110 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 111 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
112 | extern int apic_is_clustered_box(void); |
113 | #else | |
114 | static inline int apic_is_clustered_box(void) | |
115 | { | |
116 | return 0; | |
117 | } | |
67c5fc5c TG |
118 | #endif |
119 | ||
7b83dae7 RR |
120 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
121 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 122 | |
67c5fc5c TG |
123 | |
124 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
125 | static inline void lapic_shutdown(void) { } | |
126 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 127 | static inline void init_apic_mappings(void) { } |
67c5fc5c TG |
128 | |
129 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
130 | ||
131 | #endif /* __ASM_APIC_H */ |