[deliverable/linux.git] / include / asm-x86 / desc.h

#ifndef _ASM_DESC_H_
#define _ASM_DESC_H_

#ifndef __ASSEMBLY__
#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>
#include <linux/smp.h>

static inline void fill_ldt(struct desc_struct *desc, struct user_desc *info)
{
	desc->limit0 = info->limit & 0x0ffff;
	desc->base0 = info->base_addr & 0x0000ffff;

	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	desc->type = (info->read_exec_only ^ 1) << 1;
	desc->type |= info->contents << 2;
	desc->s = 1;
	desc->dpl = 0x3;
	desc->p = info->seg_not_present ^ 1;
	desc->limit = (info->limit & 0xf0000) >> 16;
	desc->avl = info->useable;
	desc->d = info->seg_32bit;
	desc->g = info->limit_in_pages;
	desc->base2 = (info->base_addr & 0xff000000) >> 24;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];

#ifdef CONFIG_X86_64
extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
extern struct desc_ptr cpu_gdt_descr[];
/* the cpu gdt accessor */
#define get_cpu_gdt_table(x) ((struct desc_struct *)cpu_gdt_descr[x].address)

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low = PTR_LOW(func);
	gate->segment = __KERNEL_CS;
	gate->ist = ist;
	gate->p = 1;
	gate->dpl = dpl;
	gate->zero0 = 0;
	gate->zero1 = 0;
	gate->type = type;
	gate->offset_middle = PTR_MIDDLE(func);
	gate->offset_high = PTR_HIGH(func);
}

#else
struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));
DECLARE_PER_CPU(struct gdt_page, gdt_page);

static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

static inline void pack_gate(gate_desc *gate, unsigned char type,
       unsigned long base, unsigned dpl, unsigned flags, unsigned short seg)

{
	gate->a = (seg << 16) | (base & 0xffff);
	gate->b = (base & 0xffff0000) |
		  (((0x80 | type | (dpl << 5)) & 0xff) << 8);
}

#endif

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc() native_load_tr_desc()
#define load_gdt(dtr) native_load_gdt(dtr)
#define load_idt(dtr) native_load_idt(dtr)
#define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr) native_store_gdt(dtr)
#define store_idt(dtr) native_store_idt(dtr)
#define store_tr(tr) (tr = native_store_tr())
#define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))

#define load_TLS(t, cpu) native_load_tls(t, cpu)
#define set_ldt native_set_ldt

#define write_ldt_entry(dt, entry, desc) \
				native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type) \
				native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
#endif

static inline void native_write_idt_entry(gate_desc *idt, int entry,
					  const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
					  const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
					  const void *desc, int type)
{
	unsigned int size;
	switch (type) {
	case DESC_TSS:
		size = sizeof(tss_desc);
		break;
	case DESC_LDT:
		size = sizeof(ldt_desc);
		break;
	default:
		size = sizeof(struct desc_struct);
		break;
	}
	memcpy(&gdt[entry], desc, size);
}

static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
				   unsigned long limit, unsigned char type,
				   unsigned char flags)
{
	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
		  (limit & 0x000f0000) | ((type & 0xff) << 8) |
		  ((flags & 0xf) << 20);
	desc->p = 1;
}


static inline void set_tssldt_descriptor(void *d, unsigned long addr,
					 unsigned type, unsigned size)
{
#ifdef CONFIG_X86_64
	struct ldttss_desc64 *desc = d;
	memset(desc, 0, sizeof(*desc));
	desc->limit0 = size & 0xFFFF;
	desc->base0 = PTR_LOW(addr);
	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	desc->type = type;
	desc->p = 1;
	desc->limit1 = (size >> 16) & 0xF;
	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	desc->base3 = PTR_HIGH(addr);
#else

	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
{
	struct desc_struct *d = get_cpu_gdt_table(cpu);
	tss_desc tss;

	/*
	 * sizeof(unsigned long) coming from an extra "long" at the end
	 * of the iobitmap. See tss_struct definition in processor.h
	 *
	 * -1? seg base+limit should be pointing to the address of the
	 * last valid byte
	 */
	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
		IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		__asm__ __volatile__("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr,
				      DESC_LDT, entries * sizeof(ldt) - 1);
		write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		__asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void native_store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;
	asm volatile("str %0":"=r" (tr));
	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	unsigned int i;
	struct desc_struct *gdt = get_cpu_gdt_table(cpu);

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

#define _LDT_empty(info) (\
	(info)->base_addr	== 0	&& \
	(info)->limit		== 0	&& \
	(info)->contents	== 0	&& \
	(info)->read_exec_only	== 1	&& \
	(info)->seg_32bit	== 0	&& \
	(info)->limit_in_pages	== 0	&& \
	(info)->seg_not_present	== 1	&& \
	(info)->useable		== 0)

#ifdef CONFIG_X86_64
#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
#else
#define LDT_empty(info) (_LDT_empty(info))
#endif

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

/*
 * load one particular LDT into the current CPU
 */
static inline void load_LDT_nolock(mm_context_t *pc)
{
	set_ldt(pc->ldt, pc->size);
}

static inline void load_LDT(mm_context_t *pc)
{
	preempt_disable();
	load_LDT_nolock(pc);
	preempt_enable();
}

static inline unsigned long get_desc_base(struct desc_struct *desc)
{
	return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
}
static inline void _set_gate(int gate, unsigned type, void *addr,
			      unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;
	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_idt_entry(idt_table, gate, &s);
}

/*
 * This needs to use 'idt_table' rather than 'idt', and
 * thus use the _nonmapped_ version of the IDT, as the
 * Pentium F0 0F bugfix can have resulted in the mapped
 * IDT being write-protected.
 */
static inline void set_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
}

/*
 * This routine sets up an interrupt gate at directory privilege level 3.
 */
static inline void set_system_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
}

static inline void set_system_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
#ifdef CONFIG_X86_32
	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
#else
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
#endif
}

static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
}

static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
}

static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
}

#else
/*
 * GET_DESC_BASE reads the descriptor base of the specified segment.
 *
 * Args:
 *    idx - descriptor index
 *    gdt - GDT pointer
 *    base - 32bit register to which the base will be written
 *    lo_w - lo word of the "base" register
 *    lo_b - lo byte of the "base" register
 *    hi_b - hi byte of the low word of the "base" register
 *
 * Example:
 *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
 *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
 */
#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
	movb idx*8+4(gdt), lo_b; \
	movb idx*8+7(gdt), hi_b; \
	shll $16, base; \
	movw idx*8+2(gdt), lo_w;


#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
80fbb69a GOC	1	#ifndef _ASM_DESC_H_
	2	#define _ASM_DESC_H_
	3
	4	#ifndef __ASSEMBLY__
	5	#include <asm/desc_defs.h>
	6	#include <asm/ldt.h>
881c2975	7	#include <asm/mmu.h>
54cd0eac	8	#include <linux/smp.h>
80fbb69a GOC	9
	10	static inline void fill_ldt(struct desc_struct desc, struct user_desc info)
	11	{
	12	desc->limit0 = info->limit & 0x0ffff;
	13	desc->base0 = info->base_addr & 0x0000ffff;
	14
	15	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	16	desc->type = (info->read_exec_only ^ 1) << 1;
	17	desc->type \|= info->contents << 2;
	18	desc->s = 1;
	19	desc->dpl = 0x3;
	20	desc->p = info->seg_not_present ^ 1;
	21	desc->limit = (info->limit & 0xf0000) >> 16;
	22	desc->avl = info->useable;
	23	desc->d = info->seg_32bit;
	24	desc->g = info->limit_in_pages;
	25	desc->base2 = (info->base_addr & 0xff000000) >> 24;
	26	}
	27
881c2975 GOC	28	extern struct desc_ptr idt_descr;
881c2975 GOC	29	extern gate_desc idt_table[];
80fbb69a	30
54cd0eac GOC	31	#ifdef CONFIG_X86_64
	32	extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
	33	extern struct desc_ptr cpu_gdt_descr[];
	34	/* the cpu gdt accessor */
	35	#define get_cpu_gdt_table(x) ((struct desc_struct *)cpu_gdt_descr[x].address)
507f90c9 GOC	36
	37	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	38	unsigned dpl, unsigned ist, unsigned seg)
	39	{
	40	gate->offset_low = PTR_LOW(func);
	41	gate->segment = __KERNEL_CS;
	42	gate->ist = ist;
	43	gate->p = 1;
	44	gate->dpl = dpl;
	45	gate->zero0 = 0;
	46	gate->zero1 = 0;
	47	gate->type = type;
	48	gate->offset_middle = PTR_MIDDLE(func);
	49	gate->offset_high = PTR_HIGH(func);
	50	}
	51
54cd0eac GOC	52	#else
	53	struct gdt_page {
	54	struct desc_struct gdt[GDT_ENTRIES];
	55	} __attribute__((aligned(PAGE_SIZE)));
	56	DECLARE_PER_CPU(struct gdt_page, gdt_page);
	57
	58	static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
	59	{
	60	return per_cpu(gdt_page, cpu).gdt;
	61	}
507f90c9 GOC	62
	63	static inline void pack_gate(gate_desc *gate, unsigned char type,
	64	unsigned long base, unsigned dpl, unsigned flags, unsigned short seg)
	65
	66	{
	67	gate->a = (seg << 16) \| (base & 0xffff);
	68	gate->b = (base & 0xffff0000) \|
	69	(((0x80 \| type \| (dpl << 5)) & 0xff) << 8);
	70	}
	71
54cd0eac GOC	72	#endif
	73
	74	#ifdef CONFIG_PARAVIRT
	75	#include <asm/paravirt.h>
	76	#else
	77	#define load_TR_desc() native_load_tr_desc()
	78	#define load_gdt(dtr) native_load_gdt(dtr)
	79	#define load_idt(dtr) native_load_idt(dtr)
	80	#define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
	81	#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
	82
	83	#define store_gdt(dtr) native_store_gdt(dtr)
	84	#define store_idt(dtr) native_store_idt(dtr)
	85	#define store_tr(tr) (tr = native_store_tr())
	86	#define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
	87
	88	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	89	#define set_ldt native_set_ldt
	90
	91	#define write_ldt_entry(dt, entry, desc) \
	92	native_write_ldt_entry(dt, entry, desc)
	93	#define write_gdt_entry(dt, entry, desc, type) \
	94	native_write_gdt_entry(dt, entry, desc, type)
	95	#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
	96	#endif
	97
	98	static inline void native_write_idt_entry(gate_desc *idt, int entry,
	99	const gate_desc *gate)
	100	{
	101	memcpy(&idt[entry], gate, sizeof(*gate));
	102	}
	103
	104	static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
	105	const void *desc)
	106	{
	107	memcpy(&ldt[entry], desc, 8);
	108	}
	109
	110	static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
	111	const void *desc, int type)
	112	{
	113	unsigned int size;
	114	switch (type) {
	115	case DESC_TSS:
	116	size = sizeof(tss_desc);
	117	break;
	118	case DESC_LDT:
	119	size = sizeof(ldt_desc);
	120	break;
	121	default:
	122	size = sizeof(struct desc_struct);
	123	break;
	124	}
	125	memcpy(&gdt[entry], desc, size);
	126	}
	127
54cd0eac GOC	128	static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
	129	unsigned long limit, unsigned char type,
	130	unsigned char flags)
	131	{
	132	desc->a = ((base & 0xffff) << 16) \| (limit & 0xffff);
	133	desc->b = (base & 0xff000000) \| ((base & 0xff0000) >> 16) \|
	134	(limit & 0x000f0000) \| ((type & 0xff) << 8) \|
	135	((flags & 0xf) << 20);
	136	desc->p = 1;
	137	}
	138
54cd0eac	139
f6e0eba1 GOC	140	static inline void set_tssldt_descriptor(void *d, unsigned long addr,
f6e0eba1 GOC	141	unsigned type, unsigned size)
c81c6ca4 GOC	142	{
c81c6ca4 GOC	143	#ifdef CONFIG_X86_64
f6e0eba1 GOC	144	struct ldttss_desc64 *desc = d;
	145	memset(desc, 0, sizeof(*desc));
	146	desc->limit0 = size & 0xFFFF;
	147	desc->base0 = PTR_LOW(addr);
	148	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	149	desc->type = type;
	150	desc->p = 1;
	151	desc->limit1 = (size >> 16) & 0xF;
	152	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	153	desc->base3 = PTR_HIGH(addr);
c81c6ca4	154	#else
f6e0eba1 GOC	155
f6e0eba1 GOC	156	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 \| type, 0);
c81c6ca4 GOC	157	#endif
	158	}
	159
	160	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
	161	{
	162	struct desc_struct *d = get_cpu_gdt_table(cpu);
	163	tss_desc tss;
	164
	165	/*
	166	* sizeof(unsigned long) coming from an extra "long" at the end
	167	* of the iobitmap. See tss_struct definition in processor.h
	168	*
	169	* -1? seg base+limit should be pointing to the address of the
	170	* last valid byte
	171	*/
f6e0eba1 GOC	172	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
f6e0eba1 GOC	173	IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1);
c81c6ca4 GOC	174	write_gdt_entry(d, entry, &tss, DESC_TSS);
	175	}
	176
	177	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	178
54cd0eac GOC	179	static inline void native_set_ldt(const void *addr, unsigned int entries)
	180	{
	181	if (likely(entries == 0))
	182	__asm__ __volatile__("lldt %w0"::"q" (0));
	183	else {
	184	unsigned cpu = smp_processor_id();
	185	ldt_desc ldt;
	186
f6e0eba1 GOC	187	set_tssldt_descriptor(&ldt, (unsigned long)addr,
f6e0eba1 GOC	188	DESC_LDT, entries * sizeof(ldt) - 1);
54cd0eac GOC	189	write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
	190	&ldt, DESC_LDT);
	191	__asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	192	}
	193	}
	194
	195	static inline void native_load_tr_desc(void)
	196	{
	197	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	198	}
	199
	200	static inline void native_load_gdt(const struct desc_ptr *dtr)
	201	{
	202	asm volatile("lgdt %0"::"m" (*dtr));
	203	}
	204
	205	static inline void native_load_idt(const struct desc_ptr *dtr)
	206	{
	207	asm volatile("lidt %0"::"m" (*dtr));
	208	}
	209
	210	static inline void native_store_gdt(struct desc_ptr *dtr)
	211	{
	212	asm volatile("sgdt %0":"=m" (*dtr));
	213	}
	214
	215	static inline void native_store_idt(struct desc_ptr *dtr)
	216	{
	217	asm volatile("sidt %0":"=m" (*dtr));
	218	}
	219
	220	static inline unsigned long native_store_tr(void)
	221	{
	222	unsigned long tr;
	223	asm volatile("str %0":"=r" (tr));
	224	return tr;
	225	}
	226
	227	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	228	{
	229	unsigned int i;
	230	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
	231
	232	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	233	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
	234	}
	235
881c2975 GOC	236	#define _LDT_empty(info) (\
	237	(info)->base_addr == 0 && \
	238	(info)->limit == 0 && \
	239	(info)->contents == 0 && \
	240	(info)->read_exec_only == 1 && \
	241	(info)->seg_32bit == 0 && \
	242	(info)->limit_in_pages == 0 && \
	243	(info)->seg_not_present == 1 && \
	244	(info)->useable == 0)
	245
	246	#ifdef CONFIG_X86_64
	247	#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
	248	#else
	249	#define LDT_empty(info) (_LDT_empty(info))
	250	#endif
	251
	252	static inline void clear_LDT(void)
	253	{
	254	set_ldt(NULL, 0);
	255	}
	256
	257	/*
	258	* load one particular LDT into the current CPU
	259	*/
	260	static inline void load_LDT_nolock(mm_context_t *pc)
	261	{
	262	set_ldt(pc->ldt, pc->size);
	263	}
	264
	265	static inline void load_LDT(mm_context_t *pc)
	266	{
	267	preempt_disable();
	268	load_LDT_nolock(pc);
	269	preempt_enable();
	270	}
	271
cc697852 GOC	272	static inline unsigned long get_desc_base(struct desc_struct *desc)
	273	{
	274	return desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24);
	275	}
507f90c9 GOC	276	static inline void _set_gate(int gate, unsigned type, void *addr,
	277	unsigned dpl, unsigned ist, unsigned seg)
	278	{
	279	gate_desc s;
	280	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	281	/*
	282	* does not need to be atomic because it is only done once at
	283	* setup time
	284	*/
	285	write_idt_entry(idt_table, gate, &s);
	286	}
	287
	288	/*
	289	* This needs to use 'idt_table' rather than 'idt', and
	290	* thus use the _nonmapped_ version of the IDT, as the
	291	* Pentium F0 0F bugfix can have resulted in the mapped
	292	* IDT being write-protected.
	293	*/
	294	static inline void set_intr_gate(unsigned int n, void *addr)
	295	{
	296	BUG_ON((unsigned)n > 0xFF);
	297	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
	298	}
	299
	300	/*
	301	* This routine sets up an interrupt gate at directory privilege level 3.
	302	*/
	303	static inline void set_system_intr_gate(unsigned int n, void *addr)
	304	{
	305	BUG_ON((unsigned)n > 0xFF);
	306	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	307	}
	308
	309	static inline void set_trap_gate(unsigned int n, void *addr)
	310	{
	311	BUG_ON((unsigned)n > 0xFF);
	312	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
	313	}
	314
	315	static inline void set_system_gate(unsigned int n, void *addr)
	316	{
	317	BUG_ON((unsigned)n > 0xFF);
	318	#ifdef CONFIG_X86_32
	319	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
	320	#else
	321	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	322	#endif
	323	}
	324
	325	static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
	326	{
	327	BUG_ON((unsigned)n > 0xFF);
	328	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
	329	}
	330
	331	static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
	332	{
	333	BUG_ON((unsigned)n > 0xFF);
	334	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
	335	}
	336
	337	static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
	338	{
	339	BUG_ON((unsigned)n > 0xFF);
340	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
341	}
cc697852	342
881c2975 GOC	343	#else
	344	/*
	345	* GET_DESC_BASE reads the descriptor base of the specified segment.
	346	*
	347	* Args:
	348	* idx - descriptor index
	349	* gdt - GDT pointer
	350	* base - 32bit register to which the base will be written
	351	* lo_w - lo word of the "base" register
	352	* lo_b - lo byte of the "base" register
	353	* hi_b - hi byte of the low word of the "base" register
	354	*
	355	* Example:
	356	* GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
	357	* Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
	358	*/
	359	#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
	360	movb idx*8+4(gdt), lo_b; \
	361	movb idx*8+7(gdt), hi_b; \
	362	shll $16, base; \
	363	movw idx*8+2(gdt), lo_w;
	364
	365
	366	#endif /* __ASSEMBLY__ */
	367
80fbb69a	368	#endif