[deliverable/linux.git] / include / asm-x86 / i387.h

/*
 * Copyright (C) 1994 Linus Torvalds
 *
 * Pentium III FXSR, SSE support
 * General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 * x86-64 work by Andi Kleen 2002
 */

#ifndef ASM_X86__I387_H
#define ASM_X86__I387_H

#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/regset.h>
#include <asm/asm.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
#include <asm/uaccess.h>
#include <asm/xsave.h>

extern unsigned int sig_xstate_size;
extern void fpu_init(void);
extern void mxcsr_feature_mask_init(void);
extern int init_fpu(struct task_struct *child);
extern asmlinkage void math_state_restore(void);
extern void init_thread_xstate(void);

extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;

#ifdef CONFIG_IA32_EMULATION
extern unsigned int sig_xstate_ia32_size;
struct _fpstate_ia32;
struct _xstate_ia32;
extern int save_i387_xstate_ia32(void __user *buf);
extern int restore_i387_xstate_ia32(void __user *buf);
#endif

#define X87_FSW_ES (1 << 7)	/* Exception Summary */

#ifdef CONFIG_X86_64

/* Ignore delayed exceptions from user space */
static inline void tolerant_fwait(void)
{
	asm volatile("1: fwait\n"
		     "2:\n"
		     _ASM_EXTABLE(1b, 2b));
}

static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
{
	int err;

	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err)
#if 0 /* See comment in __save_init_fpu() below. */
		     : [fx] "r" (fx), "m" (*fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
#endif
	return err;
}

static inline int restore_fpu_checking(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE)
		return xrstor_checking(&tsk->thread.xstate->xsave);
	else
		return fxrstor_checking(&tsk->thread.xstate->fxsave);
}

/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
   is pending. Clear the x87 state here by setting it to fixed
   values. The kernel data segment can be sometimes 0 and sometimes
   new user value. Both should be ok.
   Use the PDA as safe address because it should be already in L1. */
static inline void clear_fpu_state(struct task_struct *tsk)
{
	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;

	/*
	 * xsave header may indicate the init state of the FP.
	 */
	if ((task_thread_info(tsk)->status & TS_XSAVE) &&
	    !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
		return;

	if (unlikely(fx->swd & X87_FSW_ES))
		asm volatile("fnclex");
	alternative_input(ASM_NOP8 ASM_NOP2,
			  "    emms\n"		/* clear stack tags */
			  "    fildl %%gs:0",	/* load to clear state */
			  X86_FEATURE_FXSAVE_LEAK);
}

static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
{
	int err;

	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     _ASM_EXTABLE(1b, 3b)
		     : [err] "=r" (err), "=m" (*fx)
#if 0 /* See comment in __fxsave_clear() below. */
		     : [fx] "r" (fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "0" (0));
#endif
	if (unlikely(err) &&
	    __clear_user(fx, sizeof(struct i387_fxsave_struct)))
		err = -EFAULT;
	/* No need to clear here because the caller clears USED_MATH */
	return err;
}

static inline void fxsave(struct task_struct *tsk)
{
	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	   uses any extended registers for addressing, a second REX prefix
	   will be generated (to the assembler, rex64 followed by semicolon
	   is a separate instruction), and hence the 64-bitness is lost. */
#if 0
	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	   starting with gas 2.16. */
	__asm__ __volatile__("fxsaveq %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#elif 0
	/* Using, as a workaround, the properly prefixed form below isn't
	   accepted by any binutils version so far released, complaining that
	   the same type of prefix is used twice if an extended register is
	   needed for addressing (fix submitted to mainline 2005-11-21). */
	__asm__ __volatile__("rex64/fxsave %0"
			     : "=m" (tsk->thread.xstate->fxsave));
#else
	/* This, however, we can work around by forcing the compiler to select
	   an addressing mode that doesn't require extended registers. */
	__asm__ __volatile__("rex64/fxsave (%1)"
			     : "=m" (tsk->thread.xstate->fxsave)
			     : "cdaSDb" (&tsk->thread.xstate->fxsave));
#endif
}

static inline void __save_init_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE)
		xsave(tsk);
	else
		fxsave(tsk);

	clear_fpu_state(tsk);
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

#else  /* CONFIG_X86_32 */

extern void finit(void);

static inline void tolerant_fwait(void)
{
	asm volatile("fnclex ; fwait");
}

static inline void restore_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE) {
		xrstor_checking(&tsk->thread.xstate->xsave);
		return;
	}
	/*
	 * The "nop" is needed to make the instructions the same
	 * length.
	 */
	alternative_input(
		"nop ; frstor %1",
		"fxrstor %1",
		X86_FEATURE_FXSR,
		"m" (tsk->thread.xstate->fxsave));
}

/* We need a safe address that is cheap to find and that is already
   in L1 during context switch. The best choices are unfortunately
   different for UP and SMP */
#ifdef CONFIG_SMP
#define safe_address (__per_cpu_offset[0])
#else
#define safe_address (kstat_cpu(0).cpustat.user)
#endif

/*
 * These must be called with preempt disabled
 */
static inline void __save_init_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_XSAVE) {
		struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
		struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;

		xsave(tsk);

		/*
		 * xsave header may indicate the init state of the FP.
		 */
		if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
			goto end;

		if (unlikely(fx->swd & X87_FSW_ES))
			asm volatile("fnclex");

		/*
		 * we can do a simple return here or be paranoid :)
		 */
		goto clear_state;
	}

	/* Use more nops than strictly needed in case the compiler
	   varies code */
	alternative_input(
		"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
		"fxsave %[fx]\n"
		"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
		X86_FEATURE_FXSR,
		[fx] "m" (tsk->thread.xstate->fxsave),
		[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
clear_state:
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	   is pending.  Clear the x87 state here by setting it to fixed
	   values. safe_address is a random variable that should be in L1 */
	alternative_input(
		GENERIC_NOP8 GENERIC_NOP2,
		"emms\n\t"	  	/* clear stack tags */
		"fildl %[addr]", 	/* set F?P to defined value */
		X86_FEATURE_FXSAVE_LEAK,
		[addr] "m" (safe_address));
end:
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

#endif	/* CONFIG_X86_64 */

/*
 * Signal frame handlers...
 */
extern int save_i387_xstate(void __user *buf);
extern int restore_i387_xstate(void __user *buf);

static inline void __unlazy_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		__save_init_fpu(tsk);
		stts();
	} else
		tsk->fpu_counter = 0;
}

static inline void __clear_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		tolerant_fwait();
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	}
}

static inline void kernel_fpu_begin(void)
{
	struct thread_info *me = current_thread_info();
	preempt_disable();
	if (me->status & TS_USEDFPU)
		__save_init_fpu(me->task);
	else
		clts();
}

static inline void kernel_fpu_end(void)
{
	stts();
	preempt_enable();
}

#ifdef CONFIG_X86_64

static inline void save_init_fpu(struct task_struct *tsk)
{
	__save_init_fpu(tsk);
	stts();
}

#define unlazy_fpu	__unlazy_fpu
#define clear_fpu	__clear_fpu

#else  /* CONFIG_X86_32 */

/*
 * These disable preemption on their own and are safe
 */
static inline void save_init_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__save_init_fpu(tsk);
	stts();
	preempt_enable();
}

static inline void unlazy_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__unlazy_fpu(tsk);
	preempt_enable();
}

static inline void clear_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__clear_fpu(tsk);
	preempt_enable();
}

#endif	/* CONFIG_X86_64 */

/*
 * i387 state interaction
 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.cwd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.cwd;
	}
}

static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.xstate->fxsave.swd;
	} else {
		return (unsigned short)tsk->thread.xstate->fsave.swd;
	}
}

static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
	if (cpu_has_xmm) {
		return tsk->thread.xstate->fxsave.mxcsr;
	} else {
		return MXCSR_DEFAULT;
	}
}

#endif /* ASM_X86__I387_H */
Commit	Line	Data
1eeaed76 RM	1	/*
	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	* x86-64 work by Andi Kleen 2002
	8	*/
	9
77ef50a5 VN	10	#ifndef ASM_X86__I387_H
77ef50a5 VN	11	#define ASM_X86__I387_H
1eeaed76 RM	12
	13	#include <linux/sched.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/regset.h>
92c37fa3	16	#include <asm/asm.h>
1eeaed76 RM	17	#include <asm/processor.h>
	18	#include <asm/sigcontext.h>
	19	#include <asm/user.h>
	20	#include <asm/uaccess.h>
dc1e35c6	21	#include <asm/xsave.h>
1eeaed76	22
3c1c7f10	23	extern unsigned int sig_xstate_size;
1eeaed76	24	extern void fpu_init(void);
1eeaed76	25	extern void mxcsr_feature_mask_init(void);
aa283f49	26	extern int init_fpu(struct task_struct *child);
1eeaed76	27	extern asmlinkage void math_state_restore(void);
61c4628b	28	extern void init_thread_xstate(void);
1eeaed76 RM	29
	30	extern user_regset_active_fn fpregs_active, xfpregs_active;
	31	extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
	32	extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
	33
	34	#ifdef CONFIG_IA32_EMULATION
3c1c7f10	35	extern unsigned int sig_xstate_ia32_size;
1eeaed76	36	struct _fpstate_ia32;
ab513701 SS	37	struct _xstate_ia32;
	38	extern int save_i387_xstate_ia32(void __user *buf);
	39	extern int restore_i387_xstate_ia32(void __user *buf);
1eeaed76 RM	40	#endif
1eeaed76 RM	41
b359e8a4 SS	42	#define X87_FSW_ES (1 << 7) /* Exception Summary */
b359e8a4 SS	43
1eeaed76 RM	44	#ifdef CONFIG_X86_64
	45
	46	/* Ignore delayed exceptions from user space */
	47	static inline void tolerant_fwait(void)
	48	{
	49	asm volatile("1: fwait\n"
	50	"2:\n"
affe6637	51	_ASM_EXTABLE(1b, 2b));
1eeaed76 RM	52	}
1eeaed76 RM	53
b359e8a4	54	static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
1eeaed76 RM	55	{
	56	int err;
	57
	58	asm volatile("1: rex64/fxrstor (%[fx])\n\t"
	59	"2:\n"
	60	".section .fixup,\"ax\"\n"
	61	"3: movl $-1,%[err]\n"
	62	" jmp 2b\n"
	63	".previous\n"
affe6637	64	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	65	: [err] "=r" (err)
	66	#if 0 /* See comment in __save_init_fpu() below. */
	67	: [fx] "r" (fx), "m" (*fx), "0" (0));
	68	#else
	69	: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
	70	#endif
1eeaed76 RM	71	return err;
	72	}
	73
b359e8a4 SS	74	static inline int restore_fpu_checking(struct task_struct *tsk)
	75	{
	76	if (task_thread_info(tsk)->status & TS_XSAVE)
	77	return xrstor_checking(&tsk->thread.xstate->xsave);
	78	else
	79	return fxrstor_checking(&tsk->thread.xstate->fxsave);
	80	}
1eeaed76 RM	81
	82	/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
	83	is pending. Clear the x87 state here by setting it to fixed
	84	values. The kernel data segment can be sometimes 0 and sometimes
	85	new user value. Both should be ok.
	86	Use the PDA as safe address because it should be already in L1. */
b359e8a4	87	static inline void clear_fpu_state(struct task_struct *tsk)
1eeaed76	88	{
b359e8a4 SS	89	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	90	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
	91
	92	/*
	93	* xsave header may indicate the init state of the FP.
	94	*/
	95	if ((task_thread_info(tsk)->status & TS_XSAVE) &&
	96	!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
	97	return;
	98
1eeaed76	99	if (unlikely(fx->swd & X87_FSW_ES))
affe6637	100	asm volatile("fnclex");
1eeaed76	101	alternative_input(ASM_NOP8 ASM_NOP2,
affe6637 JP	102	" emms\n" /* clear stack tags */
	103	" fildl %%gs:0", /* load to clear state */
	104	X86_FEATURE_FXSAVE_LEAK);
1eeaed76 RM	105	}
	106
	107	static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
	108	{
	109	int err;
	110
	111	asm volatile("1: rex64/fxsave (%[fx])\n\t"
	112	"2:\n"
	113	".section .fixup,\"ax\"\n"
	114	"3: movl $-1,%[err]\n"
	115	" jmp 2b\n"
	116	".previous\n"
affe6637	117	_ASM_EXTABLE(1b, 3b)
1eeaed76 RM	118	: [err] "=r" (err), "=m" (*fx)
	119	#if 0 /* See comment in __fxsave_clear() below. */
	120	: [fx] "r" (fx), "0" (0));
	121	#else
	122	: [fx] "cdaSDb" (fx), "0" (0));
	123	#endif
affe6637 JP	124	if (unlikely(err) &&
affe6637 JP	125	__clear_user(fx, sizeof(struct i387_fxsave_struct)))
1eeaed76 RM	126	err = -EFAULT;
	127	/* No need to clear here because the caller clears USED_MATH */
	128	return err;
	129	}
	130
b359e8a4	131	static inline void fxsave(struct task_struct *tsk)
1eeaed76 RM	132	{
	133	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	134	uses any extended registers for addressing, a second REX prefix
	135	will be generated (to the assembler, rex64 followed by semicolon
	136	is a separate instruction), and hence the 64-bitness is lost. */
	137	#if 0
	138	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	139	starting with gas 2.16. */
	140	__asm__ __volatile__("fxsaveq %0"
61c4628b	141	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	142	#elif 0
	143	/* Using, as a workaround, the properly prefixed form below isn't
	144	accepted by any binutils version so far released, complaining that
	145	the same type of prefix is used twice if an extended register is
	146	needed for addressing (fix submitted to mainline 2005-11-21). */
	147	__asm__ __volatile__("rex64/fxsave %0"
61c4628b	148	: "=m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	149	#else
	150	/* This, however, we can work around by forcing the compiler to select
	151	an addressing mode that doesn't require extended registers. */
61c4628b SS	152	__asm__ __volatile__("rex64/fxsave (%1)"
	153	: "=m" (tsk->thread.xstate->fxsave)
	154	: "cdaSDb" (&tsk->thread.xstate->fxsave));
1eeaed76	155	#endif
b359e8a4 SS	156	}
	157
	158	static inline void __save_init_fpu(struct task_struct *tsk)
	159	{
	160	if (task_thread_info(tsk)->status & TS_XSAVE)
	161	xsave(tsk);
	162	else
	163	fxsave(tsk);
	164
	165	clear_fpu_state(tsk);
1eeaed76 RM	166	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	167	}
	168
1eeaed76 RM	169	#else /* CONFIG_X86_32 */
1eeaed76 RM	170
e8a496ac SS	171	extern void finit(void);
e8a496ac SS	172
1eeaed76 RM	173	static inline void tolerant_fwait(void)
	174	{
	175	asm volatile("fnclex ; fwait");
	176	}
	177
	178	static inline void restore_fpu(struct task_struct *tsk)
	179	{
b359e8a4 SS	180	if (task_thread_info(tsk)->status & TS_XSAVE) {
	181	xrstor_checking(&tsk->thread.xstate->xsave);
	182	return;
	183	}
1eeaed76 RM	184	/*
	185	* The "nop" is needed to make the instructions the same
	186	* length.
	187	*/
	188	alternative_input(
	189	"nop ; frstor %1",
	190	"fxrstor %1",
	191	X86_FEATURE_FXSR,
61c4628b	192	"m" (tsk->thread.xstate->fxsave));
1eeaed76 RM	193	}
	194
	195	/* We need a safe address that is cheap to find and that is already
	196	in L1 during context switch. The best choices are unfortunately
	197	different for UP and SMP */
	198	#ifdef CONFIG_SMP
	199	#define safe_address (__per_cpu_offset[0])
	200	#else
	201	#define safe_address (kstat_cpu(0).cpustat.user)
	202	#endif
	203
	204	/*
	205	* These must be called with preempt disabled
	206	*/
	207	static inline void __save_init_fpu(struct task_struct *tsk)
	208	{
b359e8a4 SS	209	if (task_thread_info(tsk)->status & TS_XSAVE) {
	210	struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
	211	struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
	212
	213	xsave(tsk);
	214
	215	/*
	216	* xsave header may indicate the init state of the FP.
	217	*/
	218	if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
	219	goto end;
	220
	221	if (unlikely(fx->swd & X87_FSW_ES))
	222	asm volatile("fnclex");
	223
	224	/*
	225	* we can do a simple return here or be paranoid :)
	226	*/
	227	goto clear_state;
	228	}
	229
1eeaed76 RM	230	/* Use more nops than strictly needed in case the compiler
	231	varies code */
	232	alternative_input(
	233	"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
	234	"fxsave %[fx]\n"
	235	"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
	236	X86_FEATURE_FXSR,
61c4628b SS	237	[fx] "m" (tsk->thread.xstate->fxsave),
61c4628b SS	238	[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
b359e8a4	239	clear_state:
1eeaed76 RM	240	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	241	is pending. Clear the x87 state here by setting it to fixed
	242	values. safe_address is a random variable that should be in L1 */
	243	alternative_input(
	244	GENERIC_NOP8 GENERIC_NOP2,
	245	"emms\n\t" /* clear stack tags */
	246	"fildl %[addr]", /* set F?P to defined value */
	247	X86_FEATURE_FXSAVE_LEAK,
	248	[addr] "m" (safe_address));
b359e8a4	249	end:
1eeaed76 RM	250	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	251	}
	252
ab513701 SS	253	#endif /* CONFIG_X86_64 */
ab513701 SS	254
1eeaed76 RM	255	/*
	256	* Signal frame handlers...
	257	*/
ab513701 SS	258	extern int save_i387_xstate(void __user *buf);
ab513701 SS	259	extern int restore_i387_xstate(void __user *buf);
1eeaed76 RM	260
	261	static inline void __unlazy_fpu(struct task_struct *tsk)
	262	{
	263	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	264	__save_init_fpu(tsk);
	265	stts();
	266	} else
	267	tsk->fpu_counter = 0;
	268	}
	269
	270	static inline void __clear_fpu(struct task_struct *tsk)
	271	{
	272	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	273	tolerant_fwait();
	274	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	275	stts();
	276	}
	277	}
	278
	279	static inline void kernel_fpu_begin(void)
	280	{
	281	struct thread_info *me = current_thread_info();
	282	preempt_disable();
	283	if (me->status & TS_USEDFPU)
	284	__save_init_fpu(me->task);
	285	else
	286	clts();
	287	}
	288
	289	static inline void kernel_fpu_end(void)
	290	{
	291	stts();
	292	preempt_enable();
	293	}
	294
	295	#ifdef CONFIG_X86_64
	296
	297	static inline void save_init_fpu(struct task_struct *tsk)
	298	{
	299	__save_init_fpu(tsk);
	300	stts();
	301	}
	302
	303	#define unlazy_fpu __unlazy_fpu
	304	#define clear_fpu __clear_fpu
	305
	306	#else /* CONFIG_X86_32 */
	307
	308	/*
	309	* These disable preemption on their own and are safe
	310	*/
	311	static inline void save_init_fpu(struct task_struct *tsk)
	312	{
	313	preempt_disable();
	314	__save_init_fpu(tsk);
	315	stts();
	316	preempt_enable();
	317	}
	318
	319	static inline void unlazy_fpu(struct task_struct *tsk)
	320	{
	321	preempt_disable();
	322	__unlazy_fpu(tsk);
	323	preempt_enable();
324	}
325
326	static inline void clear_fpu(struct task_struct *tsk)
327	{
328	preempt_disable();
329	__clear_fpu(tsk);
330	preempt_enable();
331	}
332
333	#endif /* CONFIG_X86_64 */
334
1eeaed76 RM	335	/*
	336	* i387 state interaction
	337	*/
	338	static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
	339	{
	340	if (cpu_has_fxsr) {
61c4628b	341	return tsk->thread.xstate->fxsave.cwd;
1eeaed76	342	} else {
1679f271	343	return (unsigned short)tsk->thread.xstate->fsave.cwd;
1eeaed76 RM	344	}
	345	}
	346
	347	static inline unsigned short get_fpu_swd(struct task_struct *tsk)
	348	{
	349	if (cpu_has_fxsr) {
61c4628b	350	return tsk->thread.xstate->fxsave.swd;
1eeaed76	351	} else {
1679f271	352	return (unsigned short)tsk->thread.xstate->fsave.swd;
1eeaed76 RM	353	}
	354	}
	355
	356	static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
	357	{
	358	if (cpu_has_xmm) {
61c4628b	359	return tsk->thread.xstate->fxsave.mxcsr;
1eeaed76 RM	360	} else {
	361	return MXCSR_DEFAULT;
	362	}
	363	}
	364
77ef50a5	365	#endif /* ASM_X86__I387_H */