[deliverable/linux.git] / include / asm-x86 / i387_64.h

/*
 * Copyright (C) 1994 Linus Torvalds
 *
 * Pentium III FXSR, SSE support
 * General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 * x86-64 work by Andi Kleen 2002
 */

#ifndef _ASM_X86_I387_H
#define _ASM_X86_I387_H

#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
#include <asm/uaccess.h>

extern void fpu_init(void);
extern unsigned int mxcsr_feature_mask;
extern void mxcsr_feature_mask_init(void);
extern void init_fpu(struct task_struct *child);
extern asmlinkage void math_state_restore(void);

#ifdef CONFIG_X86_64

/* Ignore delayed exceptions from user space */
static inline void tolerant_fwait(void)
{
	asm volatile("1: fwait\n"
		     "2:\n"
		     "   .section __ex_table,\"a\"\n"
		     "	.align 8\n"
		     "	.quad 1b,2b\n"
		     "	.previous\n");
}

static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
{
	int err;

	asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     ".section __ex_table,\"a\"\n"
		     "   .align 8\n"
		     "   .quad  1b,3b\n"
		     ".previous"
		     : [err] "=r" (err)
#if 0 /* See comment in __save_init_fpu() below. */
		     : [fx] "r" (fx), "m" (*fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
#endif
	if (unlikely(err))
		init_fpu(current);
	return err;
}

#define X87_FSW_ES (1 << 7)	/* Exception Summary */

/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
   is pending. Clear the x87 state here by setting it to fixed
   values. The kernel data segment can be sometimes 0 and sometimes
   new user value. Both should be ok.
   Use the PDA as safe address because it should be already in L1. */
static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
{
	if (unlikely(fx->swd & X87_FSW_ES))
		 asm volatile("fnclex");
	alternative_input(ASM_NOP8 ASM_NOP2,
		     "    emms\n"		/* clear stack tags */
		     "    fildl %%gs:0",	/* load to clear state */
		     X86_FEATURE_FXSAVE_LEAK);
}

static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
{
	int err;

	asm volatile("1:  rex64/fxsave (%[fx])\n\t"
		     "2:\n"
		     ".section .fixup,\"ax\"\n"
		     "3:  movl $-1,%[err]\n"
		     "    jmp  2b\n"
		     ".previous\n"
		     ".section __ex_table,\"a\"\n"
		     "   .align 8\n"
		     "   .quad  1b,3b\n"
		     ".previous"
		     : [err] "=r" (err), "=m" (*fx)
#if 0 /* See comment in __fxsave_clear() below. */
		     : [fx] "r" (fx), "0" (0));
#else
		     : [fx] "cdaSDb" (fx), "0" (0));
#endif
	if (unlikely(err) && __clear_user(fx, sizeof(struct i387_fxsave_struct)))
		err = -EFAULT;
	/* No need to clear here because the caller clears USED_MATH */
	return err;
}

static inline void __save_init_fpu(struct task_struct *tsk)
{
	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	   uses any extended registers for addressing, a second REX prefix
	   will be generated (to the assembler, rex64 followed by semicolon
	   is a separate instruction), and hence the 64-bitness is lost. */
#if 0
	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	   starting with gas 2.16. */
	__asm__ __volatile__("fxsaveq %0"
			     : "=m" (tsk->thread.i387.fxsave));
#elif 0
	/* Using, as a workaround, the properly prefixed form below isn't
	   accepted by any binutils version so far released, complaining that
	   the same type of prefix is used twice if an extended register is
	   needed for addressing (fix submitted to mainline 2005-11-21). */
	__asm__ __volatile__("rex64/fxsave %0"
			     : "=m" (tsk->thread.i387.fxsave));
#else
	/* This, however, we can work around by forcing the compiler to select
	   an addressing mode that doesn't require extended registers. */
	__asm__ __volatile__("rex64/fxsave %P2(%1)"
			     : "=m" (tsk->thread.i387.fxsave)
			     : "cdaSDb" (tsk),
				"i" (offsetof(__typeof__(*tsk),
					      thread.i387.fxsave)));
#endif
	clear_fpu_state(&tsk->thread.i387.fxsave);
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

/*
 * Signal frame handlers.
 */

static inline int save_i387(struct _fpstate __user *buf)
{
	struct task_struct *tsk = current;
	int err = 0;

	BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
			sizeof(tsk->thread.i387.fxsave));

	if ((unsigned long)buf % 16)
		printk("save_i387: bad fpstate %p\n", buf);

	if (!used_math())
		return 0;
	clear_used_math(); /* trigger finit */
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		err = save_i387_checking((struct i387_fxsave_struct __user *)buf);
		if (err) return err;
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	} else {
		if (__copy_to_user(buf, &tsk->thread.i387.fxsave,
				   sizeof(struct i387_fxsave_struct)))
			return -1;
	}
	return 1;
}

/*
 * This restores directly out of user space. Exceptions are handled.
 */
static inline int restore_i387(struct _fpstate __user *buf)
{
	set_used_math();
	if (!(task_thread_info(current)->status & TS_USEDFPU)) {
		clts();
		task_thread_info(current)->status |= TS_USEDFPU;
	}
	return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
}

#else  /* CONFIG_X86_32 */

static inline void tolerant_fwait(void)
{
	asm volatile("fnclex ; fwait");
}

static inline void restore_fpu(struct task_struct *tsk)
{
	/*
	 * The "nop" is needed to make the instructions the same
	 * length.
	 */
	alternative_input(
		"nop ; frstor %1",
		"fxrstor %1",
		X86_FEATURE_FXSR,
		"m" ((tsk)->thread.i387.fxsave));
}

/* We need a safe address that is cheap to find and that is already
   in L1 during context switch. The best choices are unfortunately
   different for UP and SMP */
#ifdef CONFIG_SMP
#define safe_address (__per_cpu_offset[0])
#else
#define safe_address (kstat_cpu(0).cpustat.user)
#endif

/*
 * These must be called with preempt disabled
 */
static inline void __save_init_fpu(struct task_struct *tsk)
{
	/* Use more nops than strictly needed in case the compiler
	   varies code */
	alternative_input(
		"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
		"fxsave %[fx]\n"
		"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
		X86_FEATURE_FXSR,
		[fx] "m" (tsk->thread.i387.fxsave),
		[fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	   is pending.  Clear the x87 state here by setting it to fixed
	   values. safe_address is a random variable that should be in L1 */
	alternative_input(
		GENERIC_NOP8 GENERIC_NOP2,
		"emms\n\t"	  	/* clear stack tags */
		"fildl %[addr]", 	/* set F?P to defined value */
		X86_FEATURE_FXSAVE_LEAK,
		[addr] "m" (safe_address));
	task_thread_info(tsk)->status &= ~TS_USEDFPU;
}

/*
 * Signal frame handlers...
 */
extern int save_i387(struct _fpstate __user *buf);
extern int restore_i387(struct _fpstate __user *buf);

#endif	/* CONFIG_X86_64 */

static inline void __unlazy_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		__save_init_fpu(tsk);
		stts();
	} else
		tsk->fpu_counter = 0;
}

static inline void __clear_fpu(struct task_struct *tsk)
{
	if (task_thread_info(tsk)->status & TS_USEDFPU) {
		tolerant_fwait();
		task_thread_info(tsk)->status &= ~TS_USEDFPU;
		stts();
	}
}

static inline void kernel_fpu_begin(void)
{
	struct thread_info *me = current_thread_info();
	preempt_disable();
	if (me->status & TS_USEDFPU)
		__save_init_fpu(me->task);
	else
		clts();
}

static inline void kernel_fpu_end(void)
{
	stts();
	preempt_enable();
}

#ifdef CONFIG_X86_64

static inline void save_init_fpu(struct task_struct *tsk)
{
	__save_init_fpu(tsk);
	stts();
}

#define unlazy_fpu	__unlazy_fpu
#define clear_fpu	__clear_fpu

#else  /* CONFIG_X86_32 */

/*
 * These disable preemption on their own and are safe
 */
static inline void save_init_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__save_init_fpu(tsk);
	stts();
	preempt_enable();
}

static inline void unlazy_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__unlazy_fpu(tsk);
	preempt_enable();
}

static inline void clear_fpu(struct task_struct *tsk)
{
	preempt_disable();
	__clear_fpu(tsk);
	preempt_enable();
}

#endif	/* CONFIG_X86_64 */

/*
 * ptrace request handlers...
 */
extern int get_fpregs(struct user_i387_struct __user *buf,
		      struct task_struct *tsk);
extern int set_fpregs(struct task_struct *tsk,
		      struct user_i387_struct __user *buf);

struct user_fxsr_struct;
extern int get_fpxregs(struct user_fxsr_struct __user *buf,
		       struct task_struct *tsk);
extern int set_fpxregs(struct task_struct *tsk,
		       struct user_fxsr_struct __user *buf);

/*
 * i387 state interaction
 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.i387.fxsave.cwd;
	} else {
		return (unsigned short)tsk->thread.i387.fsave.cwd;
	}
}

static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.i387.fxsave.swd;
	} else {
		return (unsigned short)tsk->thread.i387.fsave.swd;
	}
}

static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
	if (cpu_has_xmm) {
		return tsk->thread.i387.fxsave.mxcsr;
	} else {
		return MXCSR_DEFAULT;
	}
}

#endif	/* _ASM_X86_I387_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	* x86-64 work by Andi Kleen 2002
	8	*/
	9
cc927a25 RM	10	#ifndef _ASM_X86_I387_H
cc927a25 RM	11	#define _ASM_X86_I387_H
1da177e4 LT	12
1da177e4 LT	13	#include <linux/sched.h>
cc927a25	14	#include <linux/kernel_stat.h>
1da177e4 LT	15	#include <asm/processor.h>
	16	#include <asm/sigcontext.h>
	17	#include <asm/user.h>
1da177e4 LT	18	#include <asm/uaccess.h>
	19
	20	extern void fpu_init(void);
	21	extern unsigned int mxcsr_feature_mask;
	22	extern void mxcsr_feature_mask_init(void);
	23	extern void init_fpu(struct task_struct *child);
e07e23e1	24	extern asmlinkage void math_state_restore(void);
1da177e4	25
cc927a25	26	#ifdef CONFIG_X86_64
1da177e4 LT	27
	28	/* Ignore delayed exceptions from user space */
	29	static inline void tolerant_fwait(void)
	30	{
	31	asm volatile("1: fwait\n"
	32	"2:\n"
	33	" .section __ex_table,\"a\"\n"
	34	" .align 8\n"
	35	" .quad 1b,2b\n"
	36	" .previous\n");
	37	}
	38
cc927a25	39	static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
18bd057b	40	{
1da177e4	41	int err;
7180d4fb JB	42
7180d4fb JB	43	asm volatile("1: rex64/fxrstor (%[fx])\n\t"
1da177e4 LT	44	"2:\n"
	45	".section .fixup,\"ax\"\n"
	46	"3: movl $-1,%[err]\n"
	47	" jmp 2b\n"
	48	".previous\n"
	49	".section __ex_table,\"a\"\n"
	50	" .align 8\n"
	51	" .quad 1b,3b\n"
	52	".previous"
	53	: [err] "=r" (err)
cc927a25	54	#if 0 /* See comment in __save_init_fpu() below. */
7180d4fb JB	55	: [fx] "r" (fx), "m" (*fx), "0" (0));
	56	#else
	57	: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
	58	#endif
1da177e4 LT	59	if (unlikely(err))
	60	init_fpu(current);
	61	return err;
cc927a25	62	}
1da177e4	63
cc927a25 RM	64	#define X87_FSW_ES (1 << 7) /* Exception Summary */
	65
	66	/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
	67	is pending. Clear the x87 state here by setting it to fixed
	68	values. The kernel data segment can be sometimes 0 and sometimes
	69	new user value. Both should be ok.
	70	Use the PDA as safe address because it should be already in L1. */
	71	static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
	72	{
	73	if (unlikely(fx->swd & X87_FSW_ES))
	74	asm volatile("fnclex");
	75	alternative_input(ASM_NOP8 ASM_NOP2,
	76	" emms\n" /* clear stack tags */
	77	" fildl %%gs:0", /* load to clear state */
	78	X86_FEATURE_FXSAVE_LEAK);
	79	}
	80
	81	static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
	82	{
1da177e4	83	int err;
7180d4fb JB	84
7180d4fb JB	85	asm volatile("1: rex64/fxsave (%[fx])\n\t"
1da177e4 LT	86	"2:\n"
	87	".section .fixup,\"ax\"\n"
	88	"3: movl $-1,%[err]\n"
	89	" jmp 2b\n"
	90	".previous\n"
	91	".section __ex_table,\"a\"\n"
	92	" .align 8\n"
	93	" .quad 1b,3b\n"
	94	".previous"
7180d4fb JB	95	: [err] "=r" (err), "=m" (*fx)
	96	#if 0 /* See comment in __fxsave_clear() below. */
	97	: [fx] "r" (fx), "0" (0));
	98	#else
	99	: [fx] "cdaSDb" (fx), "0" (0));
	100	#endif
95912008 AK	101	if (unlikely(err) && __clear_user(fx, sizeof(struct i387_fxsave_struct)))
95912008 AK	102	err = -EFAULT;
18bd057b	103	/* No need to clear here because the caller clears USED_MATH */
1da177e4	104	return err;
cc927a25	105	}
1da177e4	106
cc927a25	107	static inline void __save_init_fpu(struct task_struct *tsk)
7180d4fb JB	108	{
	109	/* Using "rex64; fxsave %0" is broken because, if the memory operand
	110	uses any extended registers for addressing, a second REX prefix
	111	will be generated (to the assembler, rex64 followed by semicolon
	112	is a separate instruction), and hence the 64-bitness is lost. */
	113	#if 0
	114	/* Using "fxsaveq %0" would be the ideal choice, but is only supported
	115	starting with gas 2.16. */
	116	__asm__ __volatile__("fxsaveq %0"
	117	: "=m" (tsk->thread.i387.fxsave));
	118	#elif 0
	119	/* Using, as a workaround, the properly prefixed form below isn't
	120	accepted by any binutils version so far released, complaining that
	121	the same type of prefix is used twice if an extended register is
	122	needed for addressing (fix submitted to mainline 2005-11-21). */
	123	__asm__ __volatile__("rex64/fxsave %0"
	124	: "=m" (tsk->thread.i387.fxsave));
	125	#else
	126	/* This, however, we can work around by forcing the compiler to select
	127	an addressing mode that doesn't require extended registers. */
	128	__asm__ __volatile__("rex64/fxsave %P2(%1)"
	129	: "=m" (tsk->thread.i387.fxsave)
	130	: "cdaSDb" (tsk),
	131	"i" (offsetof(__typeof__(*tsk),
	132	thread.i387.fxsave)));
	133	#endif
18bd057b	134	clear_fpu_state(&tsk->thread.i387.fxsave);
cc927a25 RM	135	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	136	}
	137
	138	/*
	139	* Signal frame handlers.
	140	*/
	141
	142	static inline int save_i387(struct _fpstate __user *buf)
	143	{
	144	struct task_struct *tsk = current;
	145	int err = 0;
	146
	147	BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
	148	sizeof(tsk->thread.i387.fxsave));
	149
	150	if ((unsigned long)buf % 16)
	151	printk("save_i387: bad fpstate %p\n", buf);
	152
	153	if (!used_math())
	154	return 0;
	155	clear_used_math(); /* trigger finit */
	156	if (task_thread_info(tsk)->status & TS_USEDFPU) {
	157	err = save_i387_checking((struct i387_fxsave_struct __user *)buf);
	158	if (err) return err;
	159	task_thread_info(tsk)->status &= ~TS_USEDFPU;
	160	stts();
	161	} else {
	162	if (__copy_to_user(buf, &tsk->thread.i387.fxsave,
	163	sizeof(struct i387_fxsave_struct)))
	164	return -1;
	165	}
	166	return 1;
	167	}
	168
	169	/*
	170	* This restores directly out of user space. Exceptions are handled.
	171	*/
	172	static inline int restore_i387(struct _fpstate __user *buf)
	173	{
	174	set_used_math();
	175	if (!(task_thread_info(current)->status & TS_USEDFPU)) {
	176	clts();
	177	task_thread_info(current)->status \|= TS_USEDFPU;
	178	}
	179	return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
	180	}
	181
	182	#else /* CONFIG_X86_32 */
	183
	184	static inline void tolerant_fwait(void)
	185	{
	186	asm volatile("fnclex ; fwait");
	187	}
	188
	189	static inline void restore_fpu(struct task_struct *tsk)
	190	{
	191	/*
	192	* The "nop" is needed to make the instructions the same
	193	* length.
	194	*/
	195	alternative_input(
	196	"nop ; frstor %1",
	197	"fxrstor %1",
	198	X86_FEATURE_FXSR,
199	"m" ((tsk)->thread.i387.fxsave));
200	}
201
202	/* We need a safe address that is cheap to find and that is already
203	in L1 during context switch. The best choices are unfortunately
204	different for UP and SMP */
205	#ifdef CONFIG_SMP
206	#define safe_address (__per_cpu_offset[0])
207	#else
208	#define safe_address (kstat_cpu(0).cpustat.user)
209	#endif
210
211	/*
212	* These must be called with preempt disabled
213	*/
214	static inline void __save_init_fpu(struct task_struct *tsk)
215	{
216	/* Use more nops than strictly needed in case the compiler
217	varies code */
218	alternative_input(
219	"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
220	"fxsave %[fx]\n"
221	"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
222	X86_FEATURE_FXSR,
223	[fx] "m" (tsk->thread.i387.fxsave),
224	[fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
225	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
226	is pending. Clear the x87 state here by setting it to fixed
227	values. safe_address is a random variable that should be in L1 */
228	alternative_input(
229	GENERIC_NOP8 GENERIC_NOP2,
230	"emms\n\t" /* clear stack tags */
231	"fildl %[addr]", /* set F?P to defined value */
232	X86_FEATURE_FXSAVE_LEAK,
233	[addr] "m" (safe_address));
234	task_thread_info(tsk)->status &= ~TS_USEDFPU;
235	}
236
237	/*
238	* Signal frame handlers...
239	*/
240	extern int save_i387(struct _fpstate __user *buf);
241	extern int restore_i387(struct _fpstate __user *buf);
242
243	#endif /* CONFIG_X86_64 */
244
245	static inline void __unlazy_fpu(struct task_struct *tsk)
246	{
247	if (task_thread_info(tsk)->status & TS_USEDFPU) {
248	__save_init_fpu(tsk);
249	stts();
250	} else
251	tsk->fpu_counter = 0;
252	}
253
254	static inline void __clear_fpu(struct task_struct *tsk)
255	{
256	if (task_thread_info(tsk)->status & TS_USEDFPU) {
257	tolerant_fwait();
258	task_thread_info(tsk)->status &= ~TS_USEDFPU;
259	stts();
260	}
7180d4fb JB	261	}
7180d4fb JB	262
1da177e4 LT	263	static inline void kernel_fpu_begin(void)
	264	{
	265	struct thread_info *me = current_thread_info();
	266	preempt_disable();
cc927a25 RM	267	if (me->status & TS_USEDFPU)
	268	__save_init_fpu(me->task);
	269	else
	270	clts();
1da177e4 LT	271	}
	272
	273	static inline void kernel_fpu_end(void)
	274	{
	275	stts();
	276	preempt_enable();
	277	}
	278
cc927a25 RM	279	#ifdef CONFIG_X86_64
cc927a25 RM	280
e4f17c43	281	static inline void save_init_fpu(struct task_struct *tsk)
1da177e4	282	{
cc927a25	283	__save_init_fpu(tsk);
1da177e4 LT	284	stts();
	285	}
	286
cc927a25 RM	287	#define unlazy_fpu __unlazy_fpu
	288	#define clear_fpu __clear_fpu
	289
	290	#else /* CONFIG_X86_32 */
	291
	292	/*
	293	* These disable preemption on their own and are safe
1da177e4	294	*/
cc927a25	295	static inline void save_init_fpu(struct task_struct *tsk)
1da177e4	296	{
cc927a25 RM	297	preempt_disable();
	298	__save_init_fpu(tsk);
	299	stts();
	300	preempt_enable();
	301	}
	302
	303	static inline void unlazy_fpu(struct task_struct *tsk)
	304	{
	305	preempt_disable();
	306	__unlazy_fpu(tsk);
	307	preempt_enable();
	308	}
	309
	310	static inline void clear_fpu(struct task_struct *tsk)
	311	{
	312	preempt_disable();
	313	__clear_fpu(tsk);
	314	preempt_enable();
	315	}
	316
	317	#endif /* CONFIG_X86_64 */
	318
	319	/*
	320	* ptrace request handlers...
	321	*/
	322	extern int get_fpregs(struct user_i387_struct __user *buf,
	323	struct task_struct *tsk);
	324	extern int set_fpregs(struct task_struct *tsk,
	325	struct user_i387_struct __user *buf);
	326
	327	struct user_fxsr_struct;
	328	extern int get_fpxregs(struct user_fxsr_struct __user *buf,
	329	struct task_struct *tsk);
	330	extern int set_fpxregs(struct task_struct *tsk,
	331	struct user_fxsr_struct __user *buf);
	332
	333	/*
	334	* i387 state interaction
	335	*/
	336	static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
	337	{
	338	if (cpu_has_fxsr) {
	339	return tsk->thread.i387.fxsave.cwd;
	340	} else {
	341	return (unsigned short)tsk->thread.i387.fsave.cwd;
	342	}
	343	}
	344
	345	static inline unsigned short get_fpu_swd(struct task_struct *tsk)
	346	{
	347	if (cpu_has_fxsr) {
	348	return tsk->thread.i387.fxsave.swd;
	349	} else {
	350	return (unsigned short)tsk->thread.i387.fsave.swd;
	351	}
	352	}
	353
	354	static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
	355	{
	356	if (cpu_has_xmm) {
	357	return tsk->thread.i387.fxsave.mxcsr;
	358	} else {
	359	return MXCSR_DEFAULT;
92d140e2	360	}
1da177e4 LT	361	}
1da177e4 LT	362
cc927a25	363	#endif /* _ASM_X86_I387_H */