[deliverable/linux.git] / include / asm-x86 / io_apic.h

#ifndef ASM_X86__IO_APIC_H
#define ASM_X86__IO_APIC_H

#include <linux/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>

/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

/* I/O Unit Redirection Table */
#define IO_APIC_REDIR_VECTOR_MASK	0x000FF
#define IO_APIC_REDIR_DEST_LOGICAL	0x00800
#define IO_APIC_REDIR_DEST_PHYSICAL	0x00000
#define IO_APIC_REDIR_SEND_PENDING	(1 << 12)
#define IO_APIC_REDIR_REMOTE_IRR	(1 << 14)
#define IO_APIC_REDIR_LEVEL_TRIGGER	(1 << 15)
#define IO_APIC_REDIR_MASKED		(1 << 16)

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
			__reserved_2	:  7,
			PRQ		:  1,
			entries		:  8,
			__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
			arbitration	:  4,
			__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

enum ioapic_irq_destination_types {
	dest_Fixed = 0,
	dest_LowestPrio = 1,
	dest_SMI = 2,
	dest__reserved_1 = 3,
	dest_NMI = 4,
	dest_INIT = 5,
	dest__reserved_2 = 6,
	dest_ExtINT = 7
};

struct IO_APIC_route_entry {
	__u32	vector		:  8,
		delivery_mode	:  3,	/* 000: FIXED
					 * 001: lowest prio
					 * 111: ExtINT
					 */
		dest_mode	:  1,	/* 0: physical, 1: logical */
		delivery_status	:  1,
		polarity	:  1,
		irr		:  1,
		trigger		:  1,	/* 0: edge, 1: level */
		mask		:  1,	/* 0: enabled, 1: disabled */
		__reserved_2	: 15;

	__u32	__reserved_3	: 24,
		dest		:  8;
} __attribute__ ((packed));

struct IR_IO_APIC_route_entry {
	__u64	vector		: 8,
		zero		: 3,
		index2		: 1,
		delivery_status : 1,
		polarity	: 1,
		irr		: 1,
		trigger		: 1,
		mask		: 1,
		reserved	: 31,
		format		: 1,
		index		: 15;
} __attribute__ ((packed));

#ifdef CONFIG_X86_IO_APIC

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;
extern int nr_ioapic_registers[MAX_IO_APICS];

/*
 * MP-BIOS irq configuration table structures:
 */

#define MP_MAX_IOAPIC_PIN 127

struct mp_config_ioapic {
	unsigned long mp_apicaddr;
	unsigned int mp_apicid;
	unsigned char mp_type;
	unsigned char mp_apicver;
	unsigned char mp_flags;
};

struct mp_config_intsrc {
	unsigned int mp_dstapic;
	unsigned char mp_type;
	unsigned char mp_irqtype;
	unsigned short mp_irqflag;
	unsigned char mp_srcbus;
	unsigned char mp_srcbusirq;
	unsigned char mp_dstirq;
};

/* I/O APIC entries */
extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* non-0 if default (table-less) MP configuration */
extern int mpc_default_type;

/* Older SiS APIC requires we rewrite the index register */
extern int sis_apic_bug;

/* 1 if "noapic" boot option passed */
extern int skip_ioapic_setup;

/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
extern int timer_through_8259;

static inline void disable_ioapic_setup(void)
{
	skip_ioapic_setup = 1;
}

/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs \
	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)

#ifdef CONFIG_ACPI
extern int io_apic_get_unique_id(int ioapic, int apic_id);
extern int io_apic_get_version(int ioapic);
extern int io_apic_get_redir_entries(int ioapic);
extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
				   int edge_level, int active_high_low);
#endif /* CONFIG_ACPI */

extern int (*ioapic_renumber_irq)(int ioapic, int irq);
extern void ioapic_init_mappings(void);

#ifdef CONFIG_X86_64
extern int save_mask_IO_APIC_setup(void);
extern void restore_IO_APIC_setup(void);
extern void reinit_intr_remapped_IO_APIC(int);
#endif

#else  /* !CONFIG_X86_IO_APIC */
#define io_apic_assign_pci_irqs 0
static const int timer_through_8259 = 0;
static inline void ioapic_init_mappings(void) { }
#endif

#endif /* ASM_X86__IO_APIC_H */
Commit	Line	Data
77ef50a5 VN	1	#ifndef ASM_X86__IO_APIC_H
77ef50a5 VN	2	#define ASM_X86__IO_APIC_H
e1d91978	3
a1a33fa3	4	#include <linux/types.h>
e1d91978 TG	5	#include <asm/mpspec.h>
	6	#include <asm/apicdef.h>
	7
	8	/*
	9	* Intel IO-APIC support for SMP and UP systems.
	10	*
	11	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	12	*/
	13
d3f020d2 CG	14	/* I/O Unit Redirection Table */
	15	#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
	16	#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
	17	#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
	18	#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
	19	#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
	20	#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
	21	#define IO_APIC_REDIR_MASKED (1 << 16)
	22
e1d91978 TG	23	/*
	24	* The structure of the IO-APIC:
	25	*/
	26	union IO_APIC_reg_00 {
	27	u32 raw;
	28	struct {
	29	u32 __reserved_2 : 14,
	30	LTS : 1,
	31	delivery_type : 1,
	32	__reserved_1 : 8,
	33	ID : 8;
	34	} __attribute__ ((packed)) bits;
	35	};
	36
	37	union IO_APIC_reg_01 {
	38	u32 raw;
	39	struct {
	40	u32 version : 8,
	41	__reserved_2 : 7,
	42	PRQ : 1,
	43	entries : 8,
	44	__reserved_1 : 8;
	45	} __attribute__ ((packed)) bits;
	46	};
	47
	48	union IO_APIC_reg_02 {
	49	u32 raw;
	50	struct {
	51	u32 __reserved_2 : 24,
	52	arbitration : 4,
	53	__reserved_1 : 4;
	54	} __attribute__ ((packed)) bits;
	55	};
	56
	57	union IO_APIC_reg_03 {
	58	u32 raw;
	59	struct {
	60	u32 boot_DT : 1,
	61	__reserved_1 : 31;
	62	} __attribute__ ((packed)) bits;
	63	};
	64
	65	enum ioapic_irq_destination_types {
	66	dest_Fixed = 0,
	67	dest_LowestPrio = 1,
	68	dest_SMI = 2,
	69	dest__reserved_1 = 3,
	70	dest_NMI = 4,
	71	dest_INIT = 5,
	72	dest__reserved_2 = 6,
	73	dest_ExtINT = 7
	74	};
	75
	76	struct IO_APIC_route_entry {
	77	__u32 vector : 8,
	78	delivery_mode : 3, /* 000: FIXED
	79	* 001: lowest prio
	80	* 111: ExtINT
	81	*/
	82	dest_mode : 1, /* 0: physical, 1: logical */
	83	delivery_status : 1,
	84	polarity : 1,
	85	irr : 1,
	86	trigger : 1, /* 0: edge, 1: level */
87	mask : 1, /* 0: enabled, 1: disabled */
88	__reserved_2 : 15;
89
e1d91978 TG	90	__u32 __reserved_3 : 24,
e1d91978 TG	91	dest : 8;
e1d91978 TG	92	} __attribute__ ((packed));
e1d91978 TG	93
89027d35 SS	94	struct IR_IO_APIC_route_entry {
	95	__u64 vector : 8,
	96	zero : 3,
	97	index2 : 1,
	98	delivery_status : 1,
	99	polarity : 1,
	100	irr : 1,
	101	trigger : 1,
	102	mask : 1,
	103	reserved : 31,
	104	format : 1,
	105	index : 15;
	106	} __attribute__ ((packed));
	107
e1d91978 TG	108	#ifdef CONFIG_X86_IO_APIC
	109
	110	/*
	111	* # of IO-APICs and # of IRQ routing registers
	112	*/
	113	extern int nr_ioapics;
	114	extern int nr_ioapic_registers[MAX_IO_APICS];
	115
	116	/*
	117	* MP-BIOS irq configuration table structures:
	118	*/
	119
a1a33fa3 AM	120	#define MP_MAX_IOAPIC_PIN 127
a1a33fa3 AM	121
ec2cd0a2 AS	122	struct mp_config_ioapic {
	123	unsigned long mp_apicaddr;
	124	unsigned int mp_apicid;
	125	unsigned char mp_type;
	126	unsigned char mp_apicver;
	127	unsigned char mp_flags;
	128	};
	129
2fddb6e2 AS	130	struct mp_config_intsrc {
	131	unsigned int mp_dstapic;
	132	unsigned char mp_type;
	133	unsigned char mp_irqtype;
	134	unsigned short mp_irqflag;
	135	unsigned char mp_srcbus;
	136	unsigned char mp_srcbusirq;
	137	unsigned char mp_dstirq;
9e5c5f1d AS	138	};
9e5c5f1d AS	139
e1d91978	140	/* I/O APIC entries */
ec2cd0a2	141	extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
e1d91978 TG	142
	143	/* # of MP IRQ source entries */
	144	extern int mp_irq_entries;
	145
	146	/* MP IRQ source entries */
2fddb6e2	147	extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
e1d91978 TG	148
	149	/* non-0 if default (table-less) MP configuration */
	150	extern int mpc_default_type;
	151
	152	/* Older SiS APIC requires we rewrite the index register */
	153	extern int sis_apic_bug;
	154
	155	/* 1 if "noapic" boot option passed */
	156	extern int skip_ioapic_setup;
	157
35542c5e MR	158	/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
	159	extern int timer_through_8259;
	160
e1d91978 TG	161	static inline void disable_ioapic_setup(void)
	162	{
	163	skip_ioapic_setup = 1;
	164	}
	165
	166	/*
	167	* If we use the IO-APIC for IRQ routing, disable automatic
	168	* assignment of PCI IRQ's.
	169	*/
	170	#define io_apic_assign_pci_irqs \
	171	(mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
	172
	173	#ifdef CONFIG_ACPI
	174	extern int io_apic_get_unique_id(int ioapic, int apic_id);
	175	extern int io_apic_get_version(int ioapic);
	176	extern int io_apic_get_redir_entries(int ioapic);
	177	extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
	178	int edge_level, int active_high_low);
e1d91978 TG	179	#endif /* CONFIG_ACPI */
	180
	181	extern int (*ioapic_renumber_irq)(int ioapic, int irq);
	182	extern void ioapic_init_mappings(void);
	183
4dc2f96c SS	184	#ifdef CONFIG_X86_64
	185	extern int save_mask_IO_APIC_setup(void);
	186	extern void restore_IO_APIC_setup(void);
	187	extern void reinit_intr_remapped_IO_APIC(int);
	188	#endif
	189
e1d91978 TG	190	#else /* !CONFIG_X86_IO_APIC */
e1d91978 TG	191	#define io_apic_assign_pci_irqs 0
35542c5e	192	static const int timer_through_8259 = 0;
f3294a33	193	static inline void ioapic_init_mappings(void) { }
e1d91978 TG	194	#endif
e1d91978 TG	195
77ef50a5	196	#endif /* ASM_X86__IO_APIC_H */