[deliverable/linux.git] / include / asm-x86 / irq_vectors.h

#ifndef _ASM_IRQ_VECTORS_H
#define _ASM_IRQ_VECTORS_H

#include <linux/threads.h>

#define NMI_VECTOR		0x02

/*
 * IDT vectors usable for external interrupt sources start
 * at 0x20:
 */
#define FIRST_EXTERNAL_VECTOR	0x20

#ifdef CONFIG_X86_32
# define SYSCALL_VECTOR		0x80
#else
# define IA32_SYSCALL_VECTOR	0x80
#endif

/*
 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
 * cleanup after irq migration on 64 bit.
 */
#define IRQ_MOVE_CLEANUP_VECTOR	FIRST_EXTERNAL_VECTOR

/*
 * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
 * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
 */
#ifdef CONFIG_X86_32
#define IRQ0_VECTOR		(FIRST_EXTERNAL_VECTOR)
#else
#define IRQ0_VECTOR		(FIRST_EXTERNAL_VECTOR + 0x10)
#endif
#define IRQ1_VECTOR		(IRQ0_VECTOR + 1)
#define IRQ2_VECTOR		(IRQ0_VECTOR + 2)
#define IRQ3_VECTOR		(IRQ0_VECTOR + 3)
#define IRQ4_VECTOR		(IRQ0_VECTOR + 4)
#define IRQ5_VECTOR		(IRQ0_VECTOR + 5)
#define IRQ6_VECTOR		(IRQ0_VECTOR + 6)
#define IRQ7_VECTOR		(IRQ0_VECTOR + 7)
#define IRQ8_VECTOR		(IRQ0_VECTOR + 8)
#define IRQ9_VECTOR		(IRQ0_VECTOR + 9)
#define IRQ10_VECTOR		(IRQ0_VECTOR + 10)
#define IRQ11_VECTOR		(IRQ0_VECTOR + 11)
#define IRQ12_VECTOR		(IRQ0_VECTOR + 12)
#define IRQ13_VECTOR		(IRQ0_VECTOR + 13)
#define IRQ14_VECTOR		(IRQ0_VECTOR + 14)
#define IRQ15_VECTOR		(IRQ0_VECTOR + 15)

/*
 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
 *
 *  some of the following vectors are 'rare', they are merged
 *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
 *  TLB, reschedule and local APIC vectors are performance-critical.
 *
 *  Vectors 0xf0-0xfa are free (reserved for future Linux use).
 */
#ifdef CONFIG_X86_32

# define SPURIOUS_APIC_VECTOR		0xff
# define ERROR_APIC_VECTOR		0xfe
# define INVALIDATE_TLB_VECTOR		0xfd
# define RESCHEDULE_VECTOR		0xfc
# define CALL_FUNCTION_VECTOR		0xfb
# define CALL_FUNCTION_SINGLE_VECTOR	0xfa
# define THERMAL_APIC_VECTOR		0xf0

#else

#define SPURIOUS_APIC_VECTOR		0xff
#define ERROR_APIC_VECTOR		0xfe
#define RESCHEDULE_VECTOR		0xfd
#define CALL_FUNCTION_VECTOR		0xfc
#define CALL_FUNCTION_SINGLE_VECTOR	0xfb
#define THERMAL_APIC_VECTOR		0xfa
#define THRESHOLD_APIC_VECTOR		0xf9
#define UV_BAU_MESSAGE			0xf8
#define INVALIDATE_TLB_VECTOR_END	0xf7
#define INVALIDATE_TLB_VECTOR_START	0xf0	/* f0-f7 used for TLB flush */

#define NUM_INVALIDATE_TLB_VECTORS	8

#endif

/*
 * Local APIC timer IRQ vector is on a different priority level,
 * to work around the 'lost local interrupt if more than 2 IRQ
 * sources per level' errata.
 */
#define LOCAL_TIMER_VECTOR	0xef

/*
 * First APIC vector available to drivers: (vectors 0x30-0xee) we
 * start at 0x31(0x41) to spread out vectors evenly between priority
 * levels. (0x80 is the syscall vector)
 */
#ifdef CONFIG_X86_32
# define FIRST_DEVICE_VECTOR	0x31
#else
# define FIRST_DEVICE_VECTOR	(IRQ15_VECTOR + 2)
#endif

#define NR_VECTORS		256

#define FPU_IRQ			13

#define	FIRST_VM86_IRQ		3
#define LAST_VM86_IRQ		15
#define invalid_vm86_irq(irq)	((irq) < 3 || (irq) > 15)

#ifdef CONFIG_X86_64
# if NR_CPUS < MAX_IO_APICS
#  define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
# else
#  define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
# endif
# define NR_IRQ_VECTORS NR_IRQS

#elif !defined(CONFIG_X86_VOYAGER)

# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)

#  define NR_IRQS		224

#  if (224 >= 32 * NR_CPUS)
#   define NR_IRQ_VECTORS	NR_IRQS
#  else
#   define NR_IRQ_VECTORS	(32 * NR_CPUS)
#  endif

# else /* IO_APIC || PARAVIRT */

#  define NR_IRQS		16
#  define NR_IRQ_VECTORS	NR_IRQS

# endif

#else /* !VISWS && !VOYAGER */

# define NR_IRQS		224
# define NR_IRQ_VECTORS		NR_IRQS

#endif /* VISWS */

/* Voyager specific defines */
/* These define the CPIs we use in linux */
#define VIC_CPI_LEVEL0			0
#define VIC_CPI_LEVEL1			1
/* now the fake CPIs */
#define VIC_TIMER_CPI			2
#define VIC_INVALIDATE_CPI		3
#define VIC_RESCHEDULE_CPI		4
#define VIC_ENABLE_IRQ_CPI		5
#define VIC_CALL_FUNCTION_CPI		6
#define VIC_CALL_FUNCTION_SINGLE_CPI	7

/* Now the QIC CPIs:  Since we don't need the two initial levels,
 * these are 2 less than the VIC CPIs */
#define QIC_CPI_OFFSET			1
#define QIC_TIMER_CPI			(VIC_TIMER_CPI - QIC_CPI_OFFSET)
#define QIC_INVALIDATE_CPI		(VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
#define QIC_RESCHEDULE_CPI		(VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
#define QIC_ENABLE_IRQ_CPI		(VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
#define QIC_CALL_FUNCTION_CPI		(VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
#define QIC_CALL_FUNCTION_SINGLE_CPI	(VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)

#define VIC_START_FAKE_CPI		VIC_TIMER_CPI
#define VIC_END_FAKE_CPI		VIC_CALL_FUNCTION_SINGLE_CPI

/* this is the SYS_INT CPI. */
#define VIC_SYS_INT			8
#define VIC_CMN_INT			15

/* This is the boot CPI for alternate processors.  It gets overwritten
 * by the above once the system has activated all available processors */
#define VIC_CPU_BOOT_CPI		VIC_CPI_LEVEL0
#define VIC_CPU_BOOT_ERRATA_CPI		(VIC_CPI_LEVEL0 + 8)


#endif /* _ASM_IRQ_VECTORS_H */
Commit	Line	Data
9b7dc567 TG	1	#ifndef _ASM_IRQ_VECTORS_H
	2	#define _ASM_IRQ_VECTORS_H
	3
	4	#include <linux/threads.h>
	5
	6	#define NMI_VECTOR 0x02
	7
	8	/*
	9	* IDT vectors usable for external interrupt sources start
	10	* at 0x20:
	11	*/
	12	#define FIRST_EXTERNAL_VECTOR 0x20
	13
	14	#ifdef CONFIG_X86_32
	15	# define SYSCALL_VECTOR 0x80
	16	#else
	17	# define IA32_SYSCALL_VECTOR 0x80
	18	#endif
	19
	20	/*
9b7dc567 TG	21	* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
	22	* cleanup after irq migration on 64 bit.
	23	*/
	24	#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
	25
	26	/*
c46e62f7 PM	27	* Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
c46e62f7 PM	28	* Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
9b7dc567	29	*/
c46e62f7 PM	30	#ifdef CONFIG_X86_32
	31	#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
	32	#else
9b7dc567	33	#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
c46e62f7	34	#endif
9b7dc567 TG	35	#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
	36	#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
	37	#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
	38	#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
	39	#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
	40	#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
	41	#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
	42	#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
	43	#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
	44	#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
	45	#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
	46	#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
	47	#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
	48	#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
	49	#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
	50
	51	/*
	52	* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
	53	*
	54	* some of the following vectors are 'rare', they are merged
	55	* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
	56	* TLB, reschedule and local APIC vectors are performance-critical.
	57	*
	58	* Vectors 0xf0-0xfa are free (reserved for future Linux use).
	59	*/
	60	#ifdef CONFIG_X86_32
	61
	62	# define SPURIOUS_APIC_VECTOR 0xff
	63	# define ERROR_APIC_VECTOR 0xfe
	64	# define INVALIDATE_TLB_VECTOR 0xfd
	65	# define RESCHEDULE_VECTOR 0xfc
	66	# define CALL_FUNCTION_VECTOR 0xfb
1a781a77	67	# define CALL_FUNCTION_SINGLE_VECTOR 0xfa
9b7dc567 TG	68	# define THERMAL_APIC_VECTOR 0xf0
	69
	70	#else
	71
	72	#define SPURIOUS_APIC_VECTOR 0xff
	73	#define ERROR_APIC_VECTOR 0xfe
	74	#define RESCHEDULE_VECTOR 0xfd
	75	#define CALL_FUNCTION_VECTOR 0xfc
1a781a77	76	#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
9b7dc567 TG	77	#define THERMAL_APIC_VECTOR 0xfa
9b7dc567 TG	78	#define THRESHOLD_APIC_VECTOR 0xf9
99dd8713	79	#define UV_BAU_MESSAGE 0xf8
9b7dc567 TG	80	#define INVALIDATE_TLB_VECTOR_END 0xf7
	81	#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
	82
	83	#define NUM_INVALIDATE_TLB_VECTORS 8
	84
	85	#endif
	86
	87	/*
	88	* Local APIC timer IRQ vector is on a different priority level,
	89	* to work around the 'lost local interrupt if more than 2 IRQ
	90	* sources per level' errata.
	91	*/
	92	#define LOCAL_TIMER_VECTOR 0xef
	93
	94	/*
	95	* First APIC vector available to drivers: (vectors 0x30-0xee) we
	96	* start at 0x31(0x41) to spread out vectors evenly between priority
	97	* levels. (0x80 is the syscall vector)
	98	*/
	99	#ifdef CONFIG_X86_32
	100	# define FIRST_DEVICE_VECTOR 0x31
	101	#else
	102	# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
	103	#endif
	104
9b7dc567 TG	105	#define NR_VECTORS 256
	106
	107	#define FPU_IRQ 13
	108
	109	#define FIRST_VM86_IRQ 3
	110	#define LAST_VM86_IRQ 15
	111	#define invalid_vm86_irq(irq) ((irq) < 3 \|\| (irq) > 15)
	112
3c7569b2 EB	113	#ifdef CONFIG_X86_64
	114	# if NR_CPUS < MAX_IO_APICS
	115	# define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
	116	# else
	117	# define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
	118	# endif
	119	# define NR_IRQ_VECTORS NR_IRQS
	120
	121	#elif !defined(CONFIG_X86_VOYAGER)
9b7dc567	122
8bfaba87	123	# if defined(CONFIG_X86_IO_APIC) \|\| defined(CONFIG_PARAVIRT) \|\| defined(CONFIG_X86_VISWS)
9b7dc567 TG	124
	125	# define NR_IRQS 224
	126
	127	# if (224 >= 32 * NR_CPUS)
	128	# define NR_IRQ_VECTORS NR_IRQS
	129	# else
	130	# define NR_IRQ_VECTORS (32 * NR_CPUS)
	131	# endif
	132
	133	# else /* IO_APIC \|\| PARAVIRT */
	134
	135	# define NR_IRQS 16
	136	# define NR_IRQ_VECTORS NR_IRQS
	137
	138	# endif
	139
	140	#else /* !VISWS && !VOYAGER */
	141
	142	# define NR_IRQS 224
	143	# define NR_IRQ_VECTORS NR_IRQS
	144
	145	#endif /* VISWS */
	146
	147	/* Voyager specific defines */
	148	/* These define the CPIs we use in linux */
	149	#define VIC_CPI_LEVEL0 0
	150	#define VIC_CPI_LEVEL1 1
	151	/* now the fake CPIs */
	152	#define VIC_TIMER_CPI 2
	153	#define VIC_INVALIDATE_CPI 3
	154	#define VIC_RESCHEDULE_CPI 4
	155	#define VIC_ENABLE_IRQ_CPI 5
	156	#define VIC_CALL_FUNCTION_CPI 6
1a781a77	157	#define VIC_CALL_FUNCTION_SINGLE_CPI 7
9b7dc567 TG	158
	159	/* Now the QIC CPIs: Since we don't need the two initial levels,
	160	* these are 2 less than the VIC CPIs */
	161	#define QIC_CPI_OFFSET 1
	162	#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
	163	#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
	164	#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
	165	#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
	166	#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
1a781a77	167	#define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
9b7dc567 TG	168
9b7dc567 TG	169	#define VIC_START_FAKE_CPI VIC_TIMER_CPI
1a781a77	170	#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI
9b7dc567 TG	171
	172	/* this is the SYS_INT CPI. */
	173	#define VIC_SYS_INT 8
	174	#define VIC_CMN_INT 15
	175
	176	/* This is the boot CPI for alternate processors. It gets overwritten
	177	* by the above once the system has activated all available processors */
	178	#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
	179	#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
	180
	181
	182	#endif /* _ASM_IRQ_VECTORS_H */