cfq-iosched: fix rcu freeing of cfq io contexts
[deliverable/linux.git] / include / asm-x86 / kvm_host.h
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1#/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
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11#ifndef ASM_KVM_HOST_H
12#define ASM_KVM_HOST_H
043405e1 13
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14#include <linux/types.h>
15#include <linux/mm.h>
16
17#include <linux/kvm.h>
18#include <linux/kvm_para.h>
edf88417 19#include <linux/kvm_types.h>
34c16eec 20
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21#include <asm/desc.h>
22
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23#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
24#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
25#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS|0xFFFFFF0000000000ULL)
26
27#define KVM_GUEST_CR0_MASK \
28 (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \
29 | X86_CR0_NW | X86_CR0_CD)
30#define KVM_VM_CR0_ALWAYS_ON \
31 (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \
32 | X86_CR0_MP)
33#define KVM_GUEST_CR4_MASK \
34 (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
35#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
36#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
37
38#define INVALID_PAGE (~(hpa_t)0)
39#define UNMAPPED_GVA (~(gpa_t)0)
40
41#define DE_VECTOR 0
42#define UD_VECTOR 6
43#define NM_VECTOR 7
44#define DF_VECTOR 8
45#define TS_VECTOR 10
46#define NP_VECTOR 11
47#define SS_VECTOR 12
48#define GP_VECTOR 13
49#define PF_VECTOR 14
50
51#define SELECTOR_TI_MASK (1 << 2)
52#define SELECTOR_RPL_MASK 0x03
53
54#define IOPL_SHIFT 12
55
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56#define KVM_ALIAS_SLOTS 4
57
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58#define KVM_PERMILLE_MMU_PAGES 20
59#define KVM_MIN_ALLOC_MMU_PAGES 64
60#define KVM_NUM_MMU_PAGES 1024
61#define KVM_MIN_FREE_MMU_PAGES 5
62#define KVM_REFILL_PAGES 25
63#define KVM_MAX_CPUID_ENTRIES 40
64
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65extern spinlock_t kvm_lock;
66extern struct list_head vm_list;
67
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68struct kvm_vcpu;
69struct kvm;
70
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71enum {
72 VCPU_REGS_RAX = 0,
73 VCPU_REGS_RCX = 1,
74 VCPU_REGS_RDX = 2,
75 VCPU_REGS_RBX = 3,
76 VCPU_REGS_RSP = 4,
77 VCPU_REGS_RBP = 5,
78 VCPU_REGS_RSI = 6,
79 VCPU_REGS_RDI = 7,
80#ifdef CONFIG_X86_64
81 VCPU_REGS_R8 = 8,
82 VCPU_REGS_R9 = 9,
83 VCPU_REGS_R10 = 10,
84 VCPU_REGS_R11 = 11,
85 VCPU_REGS_R12 = 12,
86 VCPU_REGS_R13 = 13,
87 VCPU_REGS_R14 = 14,
88 VCPU_REGS_R15 = 15,
89#endif
90 NR_VCPU_REGS
91};
92
93enum {
94 VCPU_SREG_CS,
95 VCPU_SREG_DS,
96 VCPU_SREG_ES,
97 VCPU_SREG_FS,
98 VCPU_SREG_GS,
99 VCPU_SREG_SS,
100 VCPU_SREG_TR,
101 VCPU_SREG_LDTR,
102};
103
edf88417 104#include <asm/kvm_x86_emulate.h>
2b3ccfa0 105
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106#define KVM_NR_MEM_OBJS 40
107
108/*
109 * We don't want allocation failures within the mmu code, so we preallocate
110 * enough memory for a single page fault in a cache.
111 */
112struct kvm_mmu_memory_cache {
113 int nobjs;
114 void *objects[KVM_NR_MEM_OBJS];
115};
116
117#define NR_PTE_CHAIN_ENTRIES 5
118
119struct kvm_pte_chain {
120 u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
121 struct hlist_node link;
122};
123
124/*
125 * kvm_mmu_page_role, below, is defined as:
126 *
127 * bits 0:3 - total guest paging levels (2-4, or zero for real mode)
128 * bits 4:7 - page table level for this shadow (1-4)
129 * bits 8:9 - page table quadrant for 2-level guests
130 * bit 16 - "metaphysical" - gfn is not a real page (huge page/real mode)
131 * bits 17:19 - common access permissions for all ptes in this shadow page
132 */
133union kvm_mmu_page_role {
134 unsigned word;
135 struct {
136 unsigned glevels : 4;
137 unsigned level : 4;
138 unsigned quadrant : 2;
139 unsigned pad_for_nice_hex_output : 6;
140 unsigned metaphysical : 1;
141 unsigned access : 3;
142 };
143};
144
145struct kvm_mmu_page {
146 struct list_head link;
147 struct hlist_node hash_link;
148
149 /*
150 * The following two entries are used to key the shadow page in the
151 * hash table.
152 */
153 gfn_t gfn;
154 union kvm_mmu_page_role role;
155
156 u64 *spt;
157 /* hold the gfn of each spte inside spt */
158 gfn_t *gfns;
159 unsigned long slot_bitmap; /* One bit set per slot which has memory
160 * in this shadow page.
161 */
162 int multimapped; /* More than one parent_pte? */
163 int root_count; /* Currently serving as active root */
164 union {
165 u64 *parent_pte; /* !multimapped */
166 struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
167 };
168};
169
170/*
171 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
172 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu
173 * mode.
174 */
175struct kvm_mmu {
176 void (*new_cr3)(struct kvm_vcpu *vcpu);
177 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err);
178 void (*free)(struct kvm_vcpu *vcpu);
179 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva);
180 void (*prefetch_page)(struct kvm_vcpu *vcpu,
181 struct kvm_mmu_page *page);
182 hpa_t root_hpa;
183 int root_level;
184 int shadow_root_level;
185
186 u64 *pae_root;
187};
188
ad312c7c 189struct kvm_vcpu_arch {
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190 u64 host_tsc;
191 int interrupt_window_open;
192 unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */
193 DECLARE_BITMAP(irq_pending, KVM_NR_INTERRUPTS);
194 unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */
195 unsigned long rip; /* needs vcpu_load_rsp_rip() */
196
197 unsigned long cr0;
198 unsigned long cr2;
199 unsigned long cr3;
200 unsigned long cr4;
201 unsigned long cr8;
202 u64 pdptrs[4]; /* pae */
203 u64 shadow_efer;
204 u64 apic_base;
205 struct kvm_lapic *apic; /* kernel irqchip context */
206#define VCPU_MP_STATE_RUNNABLE 0
207#define VCPU_MP_STATE_UNINITIALIZED 1
208#define VCPU_MP_STATE_INIT_RECEIVED 2
209#define VCPU_MP_STATE_SIPI_RECEIVED 3
210#define VCPU_MP_STATE_HALTED 4
211 int mp_state;
212 int sipi_vector;
213 u64 ia32_misc_enable_msr;
b209749f 214 bool tpr_access_reporting;
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215
216 struct kvm_mmu mmu;
217
218 struct kvm_mmu_memory_cache mmu_pte_chain_cache;
219 struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
220 struct kvm_mmu_memory_cache mmu_page_cache;
221 struct kvm_mmu_memory_cache mmu_page_header_cache;
222
223 gfn_t last_pt_write_gfn;
224 int last_pt_write_count;
225 u64 *last_pte_updated;
226
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227 struct {
228 gfn_t gfn; /* presumed gfn during guest pte update */
229 struct page *page; /* page corresponding to that gfn */
230 } update_pte;
231
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232 struct i387_fxsave_struct host_fx_image;
233 struct i387_fxsave_struct guest_fx_image;
234
235 gva_t mmio_fault_cr2;
236 struct kvm_pio_request pio;
237 void *pio_data;
238
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239 struct kvm_queued_exception {
240 bool pending;
241 bool has_error_code;
242 u8 nr;
243 u32 error_code;
244 } exception;
245
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246 struct {
247 int active;
248 u8 save_iopl;
249 struct kvm_save_segment {
250 u16 selector;
251 unsigned long base;
252 u32 limit;
253 u32 ar;
254 } tr, es, ds, fs, gs;
255 } rmode;
256 int halt_request; /* real mode on Intel only */
257
258 int cpuid_nent;
07716717 259 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
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260 /* emulate context */
261
262 struct x86_emulate_ctxt emulate_ctxt;
263};
264
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265struct kvm_mem_alias {
266 gfn_t base_gfn;
267 unsigned long npages;
268 gfn_t target_gfn;
269};
270
271struct kvm_arch{
272 int naliases;
273 struct kvm_mem_alias aliases[KVM_ALIAS_SLOTS];
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274
275 unsigned int n_free_mmu_pages;
276 unsigned int n_requested_mmu_pages;
277 unsigned int n_alloc_mmu_pages;
278 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
279 /*
280 * Hash table of struct kvm_mmu_page.
281 */
282 struct list_head active_mmu_pages;
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283 struct kvm_pic *vpic;
284 struct kvm_ioapic *vioapic;
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285
286 int round_robin_prev_vcpu;
287 unsigned int tss_addr;
288 struct page *apic_access_page;
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289};
290
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291struct kvm_vm_stat {
292 u32 mmu_shadow_zapped;
293 u32 mmu_pte_write;
294 u32 mmu_pte_updated;
295 u32 mmu_pde_zapped;
296 u32 mmu_flooded;
297 u32 mmu_recycled;
dfc5aa00 298 u32 mmu_cache_miss;
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299 u32 remote_tlb_flush;
300};
301
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302struct kvm_vcpu_stat {
303 u32 pf_fixed;
304 u32 pf_guest;
305 u32 tlb_flush;
306 u32 invlpg;
307
308 u32 exits;
309 u32 io_exits;
310 u32 mmio_exits;
311 u32 signal_exits;
312 u32 irq_window_exits;
313 u32 halt_exits;
314 u32 halt_wakeup;
315 u32 request_irq_exits;
316 u32 irq_exits;
317 u32 host_state_reload;
318 u32 efer_reload;
319 u32 fpu_reload;
320 u32 insn_emulation;
321 u32 insn_emulation_fail;
322};
ad312c7c 323
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324struct descriptor_table {
325 u16 limit;
326 unsigned long base;
327} __attribute__((packed));
328
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329struct kvm_x86_ops {
330 int (*cpu_has_kvm_support)(void); /* __init */
331 int (*disabled_by_bios)(void); /* __init */
332 void (*hardware_enable)(void *dummy); /* __init */
333 void (*hardware_disable)(void *dummy);
334 void (*check_processor_compatibility)(void *rtn);
335 int (*hardware_setup)(void); /* __init */
336 void (*hardware_unsetup)(void); /* __exit */
774ead3a 337 bool (*cpu_has_accelerated_tpr)(void);
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338
339 /* Create, but do not attach this VCPU */
340 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
341 void (*vcpu_free)(struct kvm_vcpu *vcpu);
342 int (*vcpu_reset)(struct kvm_vcpu *vcpu);
343
344 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
345 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
346 void (*vcpu_put)(struct kvm_vcpu *vcpu);
347 void (*vcpu_decache)(struct kvm_vcpu *vcpu);
348
349 int (*set_guest_debug)(struct kvm_vcpu *vcpu,
350 struct kvm_debug_guest *dbg);
351 void (*guest_debug_pre)(struct kvm_vcpu *vcpu);
352 int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
353 int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
354 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
355 void (*get_segment)(struct kvm_vcpu *vcpu,
356 struct kvm_segment *var, int seg);
357 void (*set_segment)(struct kvm_vcpu *vcpu,
358 struct kvm_segment *var, int seg);
359 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
360 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
361 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
362 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
363 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
364 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
365 void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
366 void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
367 void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
368 void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
369 unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr);
370 void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value,
371 int *exception);
372 void (*cache_regs)(struct kvm_vcpu *vcpu);
373 void (*decache_regs)(struct kvm_vcpu *vcpu);
374 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
375 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
376
377 void (*tlb_flush)(struct kvm_vcpu *vcpu);
ea4a5ff8 378
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379 void (*run)(struct kvm_vcpu *vcpu, struct kvm_run *run);
380 int (*handle_exit)(struct kvm_run *run, struct kvm_vcpu *vcpu);
381 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
382 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
383 unsigned char *hypercall_addr);
384 int (*get_irq)(struct kvm_vcpu *vcpu);
385 void (*set_irq)(struct kvm_vcpu *vcpu, int vec);
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386 void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr,
387 bool has_error_code, u32 error_code);
388 bool (*exception_injected)(struct kvm_vcpu *vcpu);
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389 void (*inject_pending_irq)(struct kvm_vcpu *vcpu);
390 void (*inject_pending_vectors)(struct kvm_vcpu *vcpu,
391 struct kvm_run *run);
392
393 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
394};
395
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396extern struct kvm_x86_ops *kvm_x86_ops;
397
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398int kvm_mmu_module_init(void);
399void kvm_mmu_module_exit(void);
400
401void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
402int kvm_mmu_create(struct kvm_vcpu *vcpu);
403int kvm_mmu_setup(struct kvm_vcpu *vcpu);
404void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
405
406int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
407void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
408void kvm_mmu_zap_all(struct kvm *kvm);
3ad82a7e 409unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
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410void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
411
412enum emulation_result {
413 EMULATE_DONE, /* no further processing */
414 EMULATE_DO_MMIO, /* kvm_run filled with mmio request */
415 EMULATE_FAIL, /* can't emulate this instruction */
416};
417
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418#define EMULTYPE_NO_DECODE (1 << 0)
419#define EMULTYPE_TRAP_UD (1 << 1)
54f1585a 420int emulate_instruction(struct kvm_vcpu *vcpu, struct kvm_run *run,
571008da 421 unsigned long cr2, u16 error_code, int emulation_type);
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422void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context);
423void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
424void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
425void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
426 unsigned long *rflags);
427
428unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr);
429void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long value,
430 unsigned long *rflags);
431int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
432int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
433
434struct x86_emulate_ctxt;
435
436int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
437 int size, unsigned port);
438int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
439 int size, unsigned long count, int down,
440 gva_t address, int rep, unsigned port);
441void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
442int kvm_emulate_halt(struct kvm_vcpu *vcpu);
443int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address);
444int emulate_clts(struct kvm_vcpu *vcpu);
445int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
446 unsigned long *dest);
447int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
448 unsigned long value);
449
450void set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
451void set_cr3(struct kvm_vcpu *vcpu, unsigned long cr0);
452void set_cr4(struct kvm_vcpu *vcpu, unsigned long cr0);
453void set_cr8(struct kvm_vcpu *vcpu, unsigned long cr0);
454unsigned long get_cr8(struct kvm_vcpu *vcpu);
455void lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
456void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
457
458int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
459int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
460
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461void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
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463void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2,
464 u32 error_code);
298101da 465
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466void fx_init(struct kvm_vcpu *vcpu);
467
468int emulator_read_std(unsigned long addr,
469 void *val,
470 unsigned int bytes,
471 struct kvm_vcpu *vcpu);
472int emulator_write_emulated(unsigned long addr,
473 const void *val,
474 unsigned int bytes,
475 struct kvm_vcpu *vcpu);
476
477unsigned long segment_base(u16 selector);
478
d835dfec 479void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
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480void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
481 const u8 *new, int bytes);
482int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
483void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
484int kvm_mmu_load(struct kvm_vcpu *vcpu);
485void kvm_mmu_unload(struct kvm_vcpu *vcpu);
486
487int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
488
489int kvm_fix_hypercall(struct kvm_vcpu *vcpu);
490
3067714c 491int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code);
34c16eec 492
a03490ed 493int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
de7d789a 494int complete_pio(struct kvm_vcpu *vcpu);
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495
496static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
497{
498 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
499
500 return (struct kvm_mmu_page *)page_private(page);
501}
502
503static inline u16 read_fs(void)
504{
505 u16 seg;
506 asm("mov %%fs, %0" : "=g"(seg));
507 return seg;
508}
509
510static inline u16 read_gs(void)
511{
512 u16 seg;
513 asm("mov %%gs, %0" : "=g"(seg));
514 return seg;
515}
516
517static inline u16 read_ldt(void)
518{
519 u16 ldt;
520 asm("sldt %0" : "=g"(ldt));
521 return ldt;
522}
523
524static inline void load_fs(u16 sel)
525{
526 asm("mov %0, %%fs" : : "rm"(sel));
527}
528
529static inline void load_gs(u16 sel)
530{
531 asm("mov %0, %%gs" : : "rm"(sel));
532}
533
534#ifndef load_ldt
535static inline void load_ldt(u16 sel)
536{
537 asm("lldt %0" : : "rm"(sel));
538}
539#endif
540
541static inline void get_idt(struct descriptor_table *table)
542{
543 asm("sidt %0" : "=m"(*table));
544}
545
546static inline void get_gdt(struct descriptor_table *table)
547{
548 asm("sgdt %0" : "=m"(*table));
549}
550
551static inline unsigned long read_tr_base(void)
552{
553 u16 tr;
554 asm("str %0" : "=g"(tr));
555 return segment_base(tr);
556}
557
558#ifdef CONFIG_X86_64
559static inline unsigned long read_msr(unsigned long msr)
560{
561 u64 value;
562
563 rdmsrl(msr, value);
564 return value;
565}
566#endif
567
568static inline void fx_save(struct i387_fxsave_struct *image)
569{
570 asm("fxsave (%0)":: "r" (image));
571}
572
573static inline void fx_restore(struct i387_fxsave_struct *image)
574{
575 asm("fxrstor (%0)":: "r" (image));
576}
577
578static inline void fpu_init(void)
579{
580 asm("finit");
581}
582
583static inline u32 get_rdx_init_val(void)
584{
585 return 0x600; /* P6 family */
586}
587
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588static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
589{
590 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
591}
592
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593#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
594#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
595#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
596#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
597#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
598#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
599#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
600#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
601#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
602
603#define MSR_IA32_TIME_STAMP_COUNTER 0x010
604
605#define TSS_IOPB_BASE_OFFSET 0x66
606#define TSS_BASE_SIZE 0x68
607#define TSS_IOPB_SIZE (65536 / 8)
608#define TSS_REDIRECTION_SIZE (256 / 8)
609#define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
53e0aa7b 610
043405e1 611#endif
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