Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef __ASM_MACH_APIC_H |
2 | #define __ASM_MACH_APIC_H | |
3 | ||
4 | #include <asm/io.h> | |
5 | #include <linux/mmzone.h> | |
6 | #include <linux/nodemask.h> | |
7 | ||
8 | #define APIC_DFR_VALUE (APIC_DFR_CLUSTER) | |
9 | ||
10 | static inline cpumask_t target_cpus(void) | |
11 | { | |
12 | return CPU_MASK_ALL; | |
13 | } | |
14 | ||
15 | #define TARGET_CPUS (target_cpus()) | |
16 | ||
17 | #define NO_BALANCE_IRQ (1) | |
18 | #define esr_disable (1) | |
19 | ||
1da177e4 LT |
20 | #define INT_DELIVERY_MODE dest_LowestPrio |
21 | #define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */ | |
22 | ||
d49c4288 YL |
23 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
24 | { | |
25 | return physid_isset(apicid, bitmap); | |
26 | } | |
27 | static inline unsigned long check_apicid_present(int bit) | |
28 | { | |
29 | return physid_isset(bit, phys_cpu_present_map); | |
30 | } | |
1da177e4 LT |
31 | #define apicid_cluster(apicid) (apicid & 0xF0) |
32 | ||
33 | static inline int apic_id_registered(void) | |
34 | { | |
35 | return 1; | |
36 | } | |
37 | ||
38 | static inline void init_apic_ldr(void) | |
39 | { | |
40 | /* Already done in NUMA-Q firmware */ | |
41 | } | |
42 | ||
3c43f039 | 43 | static inline void setup_apic_routing(void) |
1da177e4 LT |
44 | { |
45 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", | |
46 | "NUMA-Q", nr_ioapics); | |
47 | } | |
48 | ||
49 | /* | |
50 | * Skip adding the timer int on secondary nodes, which causes | |
51 | * a small but painful rift in the time-space continuum. | |
52 | */ | |
53 | static inline int multi_timer_check(int apic, int irq) | |
54 | { | |
55 | return apic != 0 && irq == 0; | |
56 | } | |
57 | ||
58 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) | |
59 | { | |
60 | /* We don't have a good way to do this yet - hack */ | |
61 | return physids_promote(0xFUL); | |
62 | } | |
63 | ||
64 | /* Mapping from cpu number to logical apicid */ | |
65 | extern u8 cpu_2_logical_apicid[]; | |
66 | static inline int cpu_to_logical_apicid(int cpu) | |
67 | { | |
68 | if (cpu >= NR_CPUS) | |
69 | return BAD_APICID; | |
70 | return (int)cpu_2_logical_apicid[cpu]; | |
71 | } | |
72 | ||
73 | /* | |
74 | * Supporting over 60 cpus on NUMA-Q requires a locality-dependent | |
75 | * cpu to APIC ID relation to properly interact with the intelligent | |
76 | * mode of the cluster controller. | |
77 | */ | |
78 | static inline int cpu_present_to_apicid(int mps_cpu) | |
79 | { | |
80 | if (mps_cpu < 60) | |
81 | return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3)); | |
82 | else | |
83 | return BAD_APICID; | |
84 | } | |
85 | ||
1da177e4 LT |
86 | static inline int apicid_to_node(int logical_apicid) |
87 | { | |
88 | return logical_apicid >> 4; | |
89 | } | |
90 | ||
91 | static inline physid_mask_t apicid_to_cpu_present(int logical_apicid) | |
92 | { | |
93 | int node = apicid_to_node(logical_apicid); | |
94 | int cpu = __ffs(logical_apicid & 0xf); | |
95 | ||
96 | return physid_mask_of_physid(cpu + 4*node); | |
97 | } | |
98 | ||
c7e844f0 AK |
99 | extern void *xquad_portio; |
100 | ||
1da177e4 LT |
101 | static inline void setup_portio_remap(void) |
102 | { | |
103 | int num_quads = num_online_nodes(); | |
104 | ||
105 | if (num_quads <= 1) | |
106 | return; | |
107 | ||
108 | printk("Remapping cross-quad port I/O for %d quads\n", num_quads); | |
109 | xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD); | |
110 | printk("xquad_portio vaddr 0x%08lx, len %08lx\n", | |
111 | (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD); | |
112 | } | |
113 | ||
114 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
115 | { | |
116 | return (1); | |
117 | } | |
118 | ||
119 | static inline void enable_apic_mode(void) | |
120 | { | |
121 | } | |
122 | ||
123 | /* | |
124 | * We use physical apicids here, not logical, so just return the default | |
125 | * physical broadcast to stop people from breaking us | |
126 | */ | |
127 | static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) | |
128 | { | |
129 | return (int) 0xF; | |
130 | } | |
131 | ||
132 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | |
133 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) | |
134 | { | |
135 | return cpuid_apic >> index_msb; | |
136 | } | |
137 | ||
138 | #endif /* __ASM_MACH_APIC_H */ |