rename io_apic_64.c and io_apic_32.c to io_apic.c
[deliverable/linux.git] / include / asm-x86 / mpspec.h
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1#ifndef ASM_X86__MPSPEC_H
2#define ASM_X86__MPSPEC_H
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4#include <linux/init.h>
5
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6#include <asm/mpspec_def.h>
7
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8extern int apic_version[MAX_APICS];
9
96a388de 10#ifdef CONFIG_X86_32
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11#include <mach_mpspec.h>
12
c2805aa1 13extern unsigned int def_to_bigsmp;
ae9d983b 14extern u8 apicid_2_node[];
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15extern int pic_mode;
16
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17#ifdef CONFIG_X86_NUMAQ
18extern int mp_bus_id_to_node[MAX_MP_BUSSES];
19extern int mp_bus_id_to_local[MAX_MP_BUSSES];
20extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
21#endif
22
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23#define MAX_APICID 256
24
96a388de 25#else
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26
27#define MAX_MP_BUSSES 256
28/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
29#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
30
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31#endif
32
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33extern void early_find_smp_config(void);
34extern void early_get_smp_config(void);
35
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36#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
37extern int mp_bus_id_to_type[MAX_MP_BUSSES];
38#endif
39
a6333c3c 40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
c0a282c2 41
c2805aa1 42extern unsigned int boot_cpu_physical_apicid;
e0da3364 43extern unsigned int max_physical_apicid;
c2805aa1 44extern int smp_found_config;
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45extern int mpc_default_type;
46extern unsigned long mp_lapic_addr;
47
48extern void find_smp_config(void);
49extern void get_smp_config(void);
af1cf204 50#ifdef CONFIG_X86_MPPARSE
2944e16b 51extern void early_reserve_e820_mpc_new(void);
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52#else
53static inline void early_reserve_e820_mpc_new(void) { }
54#endif
c2805aa1 55
903dcb5a 56void __cpuinit generic_processor_info(int apicid, int version);
c2805aa1 57#ifdef CONFIG_ACPI
a65d1d64 58extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
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59extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
60 u32 gsi);
61extern void mp_config_acpi_legacy_irqs(void);
62extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
71f521bb 63extern int get_nr_irqs_via_madt(void);
835fc943 64#ifdef CONFIG_X86_IO_APIC
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65extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
66 u32 gsi, int triggering, int polarity);
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67#else
68static inline int
69mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
70 u32 gsi, int triggering, int polarity)
71{
72 return 0;
73}
74#endif
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75#endif /* CONFIG_ACPI */
76
77#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
78
30971e17 79struct physid_mask {
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80 unsigned long mask[PHYSID_ARRAY_SIZE];
81};
82
83typedef struct physid_mask physid_mask_t;
84
85#define physid_set(physid, map) set_bit(physid, (map).mask)
86#define physid_clear(physid, map) clear_bit(physid, (map).mask)
87#define physid_isset(physid, map) test_bit(physid, (map).mask)
30971e17 88#define physid_test_and_set(physid, map) \
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89 test_and_set_bit(physid, (map).mask)
90
30971e17 91#define physids_and(dst, src1, src2) \
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92 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
93
30971e17 94#define physids_or(dst, src1, src2) \
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95 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
96
30971e17 97#define physids_clear(map) \
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98 bitmap_zero((map).mask, MAX_APICS)
99
30971e17 100#define physids_complement(dst, src) \
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101 bitmap_complement((dst).mask, (src).mask, MAX_APICS)
102
30971e17 103#define physids_empty(map) \
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104 bitmap_empty((map).mask, MAX_APICS)
105
30971e17 106#define physids_equal(map1, map2) \
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107 bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
108
30971e17 109#define physids_weight(map) \
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110 bitmap_weight((map).mask, MAX_APICS)
111
30971e17 112#define physids_shift_right(d, s, n) \
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113 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
114
30971e17 115#define physids_shift_left(d, s, n) \
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116 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
117
118#define physids_coerce(map) ((map).mask[0])
119
120#define physids_promote(physids) \
121 ({ \
122 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
123 __physid_mask.mask[0] = physids; \
124 __physid_mask; \
125 })
126
b6df1b8b 127/* Note: will create very large stack frames if physid_mask_t is big */
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128#define physid_mask_of_physid(physid) \
129 ({ \
130 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
131 physid_set(physid, __physid_mask); \
132 __physid_mask; \
133 })
134
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135static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
136{
137 physids_clear(*map);
138 physid_set(physid, *map);
139}
140
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141#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
142#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
143
144extern physid_mask_t phys_cpu_present_map;
145
77ef50a5 146#endif /* ASM_X86__MPSPEC_H */
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