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c2805aa1 TG |
1 | #ifndef _AM_X86_MPSPEC_H |
2 | #define _AM_X86_MPSPEC_H | |
3 | ||
4 | #include <asm/mpspec_def.h> | |
5 | ||
96a388de | 6 | #ifdef CONFIG_X86_32 |
c2805aa1 TG |
7 | #include <mach_mpspec.h> |
8 | ||
c2805aa1 TG |
9 | extern unsigned int def_to_bigsmp; |
10 | extern int apic_version[MAX_APICS]; | |
ae9d983b | 11 | extern u8 apicid_2_node[]; |
c2805aa1 TG |
12 | extern int pic_mode; |
13 | ||
ae9d983b TG |
14 | #define MAX_APICID 256 |
15 | ||
96a388de | 16 | #else |
c2805aa1 TG |
17 | |
18 | #define MAX_MP_BUSSES 256 | |
19 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ | |
20 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) | |
21 | ||
8643f9d0 YL |
22 | extern void early_find_smp_config(void); |
23 | extern void early_get_smp_config(void); | |
24 | ||
c2805aa1 TG |
25 | #endif |
26 | ||
c0a282c2 AS |
27 | #if defined(CONFIG_MCA) || defined(CONFIG_EISA) |
28 | extern int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
29 | #endif | |
30 | ||
a6333c3c | 31 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
c0a282c2 | 32 | |
c2805aa1 TG |
33 | extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES]; |
34 | ||
35 | extern unsigned int boot_cpu_physical_apicid; | |
36 | extern int smp_found_config; | |
37 | extern int nr_ioapics; | |
38 | extern int mp_irq_entries; | |
39 | extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
40 | extern int mpc_default_type; | |
41 | extern unsigned long mp_lapic_addr; | |
42 | ||
43 | extern void find_smp_config(void); | |
44 | extern void get_smp_config(void); | |
45 | ||
46 | #ifdef CONFIG_ACPI | |
47 | extern void mp_register_lapic(u8 id, u8 enabled); | |
48 | extern void mp_register_lapic_address(u64 address); | |
49 | extern void mp_register_ioapic(u8 id, u32 address, u32 gsi_base); | |
50 | extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, | |
51 | u32 gsi); | |
52 | extern void mp_config_acpi_legacy_irqs(void); | |
53 | extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); | |
54 | #endif /* CONFIG_ACPI */ | |
55 | ||
56 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
57 | ||
58 | struct physid_mask | |
59 | { | |
60 | unsigned long mask[PHYSID_ARRAY_SIZE]; | |
61 | }; | |
62 | ||
63 | typedef struct physid_mask physid_mask_t; | |
64 | ||
65 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
66 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
67 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
68 | #define physid_test_and_set(physid, map) \ | |
69 | test_and_set_bit(physid, (map).mask) | |
70 | ||
71 | #define physids_and(dst, src1, src2) \ | |
72 | bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
73 | ||
74 | #define physids_or(dst, src1, src2) \ | |
75 | bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
76 | ||
77 | #define physids_clear(map) \ | |
78 | bitmap_zero((map).mask, MAX_APICS) | |
79 | ||
80 | #define physids_complement(dst, src) \ | |
81 | bitmap_complement((dst).mask, (src).mask, MAX_APICS) | |
82 | ||
83 | #define physids_empty(map) \ | |
84 | bitmap_empty((map).mask, MAX_APICS) | |
85 | ||
86 | #define physids_equal(map1, map2) \ | |
87 | bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | |
88 | ||
89 | #define physids_weight(map) \ | |
90 | bitmap_weight((map).mask, MAX_APICS) | |
91 | ||
92 | #define physids_shift_right(d, s, n) \ | |
93 | bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | |
94 | ||
95 | #define physids_shift_left(d, s, n) \ | |
96 | bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | |
97 | ||
98 | #define physids_coerce(map) ((map).mask[0]) | |
99 | ||
100 | #define physids_promote(physids) \ | |
101 | ({ \ | |
102 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
103 | __physid_mask.mask[0] = physids; \ | |
104 | __physid_mask; \ | |
105 | }) | |
106 | ||
107 | #define physid_mask_of_physid(physid) \ | |
108 | ({ \ | |
109 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
110 | physid_set(physid, __physid_mask); \ | |
111 | __physid_mask; \ | |
112 | }) | |
113 | ||
114 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
115 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
116 | ||
117 | extern physid_mask_t phys_cpu_present_map; | |
118 | ||
96a388de | 119 | #endif |