Commit | Line | Data |
---|---|---|
c2805aa1 TG |
1 | #ifndef _AM_X86_MPSPEC_H |
2 | #define _AM_X86_MPSPEC_H | |
3 | ||
86c9835b IM |
4 | #include <linux/init.h> |
5 | ||
c2805aa1 TG |
6 | #include <asm/mpspec_def.h> |
7 | ||
96a388de | 8 | #ifdef CONFIG_X86_32 |
c2805aa1 TG |
9 | #include <mach_mpspec.h> |
10 | ||
c2805aa1 TG |
11 | extern unsigned int def_to_bigsmp; |
12 | extern int apic_version[MAX_APICS]; | |
ae9d983b | 13 | extern u8 apicid_2_node[]; |
c2805aa1 TG |
14 | extern int pic_mode; |
15 | ||
d49c4288 YL |
16 | #ifdef CONFIG_X86_NUMAQ |
17 | extern int mp_bus_id_to_node[MAX_MP_BUSSES]; | |
18 | extern int mp_bus_id_to_local[MAX_MP_BUSSES]; | |
19 | extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; | |
20 | #endif | |
21 | ||
ae9d983b TG |
22 | #define MAX_APICID 256 |
23 | ||
96a388de | 24 | #else |
c2805aa1 TG |
25 | |
26 | #define MAX_MP_BUSSES 256 | |
27 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ | |
28 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) | |
29 | ||
ab530e1f YL |
30 | #endif |
31 | ||
8643f9d0 YL |
32 | extern void early_find_smp_config(void); |
33 | extern void early_get_smp_config(void); | |
34 | ||
c0a282c2 AS |
35 | #if defined(CONFIG_MCA) || defined(CONFIG_EISA) |
36 | extern int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
37 | #endif | |
38 | ||
a6333c3c | 39 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
c0a282c2 | 40 | |
c2805aa1 | 41 | extern unsigned int boot_cpu_physical_apicid; |
e0da3364 | 42 | extern unsigned int max_physical_apicid; |
c2805aa1 | 43 | extern int smp_found_config; |
c2805aa1 TG |
44 | extern int mpc_default_type; |
45 | extern unsigned long mp_lapic_addr; | |
46 | ||
47 | extern void find_smp_config(void); | |
48 | extern void get_smp_config(void); | |
2944e16b | 49 | extern void early_reserve_e820_mpc_new(void); |
c2805aa1 | 50 | |
903dcb5a | 51 | void __cpuinit generic_processor_info(int apicid, int version); |
c2805aa1 | 52 | #ifdef CONFIG_ACPI |
a65d1d64 | 53 | extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); |
c2805aa1 TG |
54 | extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, |
55 | u32 gsi); | |
56 | extern void mp_config_acpi_legacy_irqs(void); | |
57 | extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); | |
2944e16b | 58 | extern void MP_intsrc_info(struct mpc_config_intsrc *m); |
835fc943 | 59 | #ifdef CONFIG_X86_IO_APIC |
2944e16b YL |
60 | extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, |
61 | u32 gsi, int triggering, int polarity); | |
835fc943 IM |
62 | #else |
63 | static inline int | |
64 | mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, | |
65 | u32 gsi, int triggering, int polarity) | |
66 | { | |
67 | return 0; | |
68 | } | |
69 | #endif | |
c2805aa1 TG |
70 | #endif /* CONFIG_ACPI */ |
71 | ||
72 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
73 | ||
30971e17 | 74 | struct physid_mask { |
c2805aa1 TG |
75 | unsigned long mask[PHYSID_ARRAY_SIZE]; |
76 | }; | |
77 | ||
78 | typedef struct physid_mask physid_mask_t; | |
79 | ||
80 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
81 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
82 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
30971e17 | 83 | #define physid_test_and_set(physid, map) \ |
c2805aa1 TG |
84 | test_and_set_bit(physid, (map).mask) |
85 | ||
30971e17 | 86 | #define physids_and(dst, src1, src2) \ |
c2805aa1 TG |
87 | bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
88 | ||
30971e17 | 89 | #define physids_or(dst, src1, src2) \ |
c2805aa1 TG |
90 | bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
91 | ||
30971e17 | 92 | #define physids_clear(map) \ |
c2805aa1 TG |
93 | bitmap_zero((map).mask, MAX_APICS) |
94 | ||
30971e17 | 95 | #define physids_complement(dst, src) \ |
c2805aa1 TG |
96 | bitmap_complement((dst).mask, (src).mask, MAX_APICS) |
97 | ||
30971e17 | 98 | #define physids_empty(map) \ |
c2805aa1 TG |
99 | bitmap_empty((map).mask, MAX_APICS) |
100 | ||
30971e17 | 101 | #define physids_equal(map1, map2) \ |
c2805aa1 TG |
102 | bitmap_equal((map1).mask, (map2).mask, MAX_APICS) |
103 | ||
30971e17 | 104 | #define physids_weight(map) \ |
c2805aa1 TG |
105 | bitmap_weight((map).mask, MAX_APICS) |
106 | ||
30971e17 | 107 | #define physids_shift_right(d, s, n) \ |
c2805aa1 TG |
108 | bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) |
109 | ||
30971e17 | 110 | #define physids_shift_left(d, s, n) \ |
c2805aa1 TG |
111 | bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) |
112 | ||
113 | #define physids_coerce(map) ((map).mask[0]) | |
114 | ||
115 | #define physids_promote(physids) \ | |
116 | ({ \ | |
117 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
118 | __physid_mask.mask[0] = physids; \ | |
119 | __physid_mask; \ | |
120 | }) | |
121 | ||
122 | #define physid_mask_of_physid(physid) \ | |
123 | ({ \ | |
124 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
125 | physid_set(physid, __physid_mask); \ | |
126 | __physid_mask; \ | |
127 | }) | |
128 | ||
129 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
130 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
131 | ||
132 | extern physid_mask_t phys_cpu_present_map; | |
133 | ||
96a388de | 134 | #endif |