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d3561b7f RR |
1 | #ifndef __ASM_PARAVIRT_H |
2 | #define __ASM_PARAVIRT_H | |
3 | /* Various instructions on x86 need to be replaced for | |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
da181a8b | 7 | #include <asm/page.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
139ec7c4 | 10 | /* Bitmask of what can be clobbered: usually at least eax. */ |
21438f7c GOC |
11 | #define CLBR_NONE 0 |
12 | #define CLBR_EAX (1 << 0) | |
13 | #define CLBR_ECX (1 << 1) | |
14 | #define CLBR_EDX (1 << 2) | |
15 | ||
16 | #ifdef CONFIG_X86_64 | |
17 | #define CLBR_RSI (1 << 3) | |
18 | #define CLBR_RDI (1 << 4) | |
19 | #define CLBR_R8 (1 << 5) | |
20 | #define CLBR_R9 (1 << 6) | |
21 | #define CLBR_R10 (1 << 7) | |
22 | #define CLBR_R11 (1 << 8) | |
23 | #define CLBR_ANY ((1 << 9) - 1) | |
24 | #include <asm/desc_defs.h> | |
25 | #else | |
26 | /* CLBR_ANY should match all regs platform has. For i386, that's just it */ | |
27 | #define CLBR_ANY ((1 << 3) - 1) | |
28 | #endif /* X86_64 */ | |
139ec7c4 | 29 | |
d3561b7f | 30 | #ifndef __ASSEMBLY__ |
3dc494e8 | 31 | #include <linux/types.h> |
d4c10477 | 32 | #include <linux/cpumask.h> |
ce6234b5 | 33 | #include <asm/kmap_types.h> |
8d947344 | 34 | #include <asm/desc_defs.h> |
3dc494e8 | 35 | |
ce6234b5 | 36 | struct page; |
d3561b7f | 37 | struct thread_struct; |
6b68f01b | 38 | struct desc_ptr; |
d3561b7f | 39 | struct tss_struct; |
da181a8b | 40 | struct mm_struct; |
90a0a06a | 41 | struct desc_struct; |
294688c0 | 42 | |
93b1eab3 JF |
43 | /* general info */ |
44 | struct pv_info { | |
d3561b7f | 45 | unsigned int kernel_rpl; |
5311ab62 | 46 | int shared_kernel_pmd; |
93b1eab3 | 47 | int paravirt_enabled; |
d3561b7f | 48 | const char *name; |
93b1eab3 | 49 | }; |
d3561b7f | 50 | |
93b1eab3 | 51 | struct pv_init_ops { |
139ec7c4 | 52 | /* |
93b1eab3 JF |
53 | * Patch may replace one of the defined code sequences with |
54 | * arbitrary code, subject to the same register constraints. | |
55 | * This generally means the code is not free to clobber any | |
56 | * registers other than EAX. The patch function should return | |
57 | * the number of bytes of code generated, as we nop pad the | |
58 | * rest in generic code. | |
139ec7c4 | 59 | */ |
ab144f5e AK |
60 | unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, |
61 | unsigned long addr, unsigned len); | |
139ec7c4 | 62 | |
294688c0 | 63 | /* Basic arch-specific setup */ |
d3561b7f RR |
64 | void (*arch_setup)(void); |
65 | char *(*memory_setup)(void); | |
6996d3b6 JF |
66 | void (*post_allocator_init)(void); |
67 | ||
294688c0 | 68 | /* Print a banner to identify the environment */ |
d3561b7f | 69 | void (*banner)(void); |
93b1eab3 JF |
70 | }; |
71 | ||
72 | ||
8965c1c0 | 73 | struct pv_lazy_ops { |
93b1eab3 | 74 | /* Set deferred update mode, used for batching operations. */ |
8965c1c0 JF |
75 | void (*enter)(void); |
76 | void (*leave)(void); | |
93b1eab3 JF |
77 | }; |
78 | ||
79 | struct pv_time_ops { | |
80 | void (*time_init)(void); | |
d3561b7f | 81 | |
294688c0 | 82 | /* Set and set time of day */ |
d3561b7f RR |
83 | unsigned long (*get_wallclock)(void); |
84 | int (*set_wallclock)(unsigned long); | |
d3561b7f | 85 | |
93b1eab3 JF |
86 | unsigned long long (*sched_clock)(void); |
87 | unsigned long (*get_cpu_khz)(void); | |
88 | }; | |
d3561b7f | 89 | |
93b1eab3 | 90 | struct pv_cpu_ops { |
294688c0 | 91 | /* hooks for various privileged instructions */ |
1a1eecd1 AK |
92 | unsigned long (*get_debugreg)(int regno); |
93 | void (*set_debugreg)(int regno, unsigned long value); | |
d3561b7f | 94 | |
1a1eecd1 | 95 | void (*clts)(void); |
d3561b7f | 96 | |
1a1eecd1 AK |
97 | unsigned long (*read_cr0)(void); |
98 | void (*write_cr0)(unsigned long); | |
d3561b7f | 99 | |
1a1eecd1 AK |
100 | unsigned long (*read_cr4_safe)(void); |
101 | unsigned long (*read_cr4)(void); | |
102 | void (*write_cr4)(unsigned long); | |
d3561b7f | 103 | |
4c9890c2 GOC |
104 | #ifdef CONFIG_X86_64 |
105 | unsigned long (*read_cr8)(void); | |
106 | void (*write_cr8)(unsigned long); | |
107 | #endif | |
108 | ||
294688c0 | 109 | /* Segment descriptor handling */ |
1a1eecd1 | 110 | void (*load_tr_desc)(void); |
6b68f01b GOC |
111 | void (*load_gdt)(const struct desc_ptr *); |
112 | void (*load_idt)(const struct desc_ptr *); | |
113 | void (*store_gdt)(struct desc_ptr *); | |
114 | void (*store_idt)(struct desc_ptr *); | |
1a1eecd1 AK |
115 | void (*set_ldt)(const void *desc, unsigned entries); |
116 | unsigned long (*store_tr)(void); | |
117 | void (*load_tls)(struct thread_struct *t, unsigned int cpu); | |
75b8bb3e GOC |
118 | void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum, |
119 | const void *desc); | |
90a0a06a | 120 | void (*write_gdt_entry)(struct desc_struct *, |
014b15be | 121 | int entrynum, const void *desc, int size); |
8d947344 GOC |
122 | void (*write_idt_entry)(gate_desc *, |
123 | int entrynum, const gate_desc *gate); | |
faca6227 | 124 | void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t); |
d3561b7f | 125 | |
1a1eecd1 | 126 | void (*set_iopl_mask)(unsigned mask); |
93b1eab3 JF |
127 | |
128 | void (*wbinvd)(void); | |
1a1eecd1 | 129 | void (*io_delay)(void); |
d3561b7f | 130 | |
93b1eab3 JF |
131 | /* cpuid emulation, mostly so that caps bits can be disabled */ |
132 | void (*cpuid)(unsigned int *eax, unsigned int *ebx, | |
133 | unsigned int *ecx, unsigned int *edx); | |
134 | ||
135 | /* MSR, PMC and TSR operations. | |
136 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | |
137 | u64 (*read_msr)(unsigned int msr, int *err); | |
c9dcda5c | 138 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); |
93b1eab3 JF |
139 | |
140 | u64 (*read_tsc)(void); | |
b8d1fae7 | 141 | u64 (*read_pmc)(int counter); |
e5aaac44 | 142 | unsigned long long (*read_tscp)(unsigned int *aux); |
93b1eab3 JF |
143 | |
144 | /* These two are jmp to, not actually called. */ | |
6abcd98f | 145 | void (*irq_enable_syscall_ret)(void); |
93b1eab3 | 146 | void (*iret)(void); |
8965c1c0 | 147 | |
e801f864 GOC |
148 | void (*swapgs)(void); |
149 | ||
8965c1c0 | 150 | struct pv_lazy_ops lazy_mode; |
93b1eab3 JF |
151 | }; |
152 | ||
153 | struct pv_irq_ops { | |
154 | void (*init_IRQ)(void); | |
155 | ||
294688c0 | 156 | /* |
93b1eab3 JF |
157 | * Get/set interrupt state. save_fl and restore_fl are only |
158 | * expected to use X86_EFLAGS_IF; all other bits | |
159 | * returned from save_fl are undefined, and may be ignored by | |
160 | * restore_fl. | |
294688c0 | 161 | */ |
93b1eab3 JF |
162 | unsigned long (*save_fl)(void); |
163 | void (*restore_fl)(unsigned long); | |
164 | void (*irq_disable)(void); | |
165 | void (*irq_enable)(void); | |
166 | void (*safe_halt)(void); | |
167 | void (*halt)(void); | |
168 | }; | |
d6dd61c8 | 169 | |
93b1eab3 | 170 | struct pv_apic_ops { |
13623d79 | 171 | #ifdef CONFIG_X86_LOCAL_APIC |
294688c0 JF |
172 | /* |
173 | * Direct APIC operations, principally for VMI. Ideally | |
174 | * these shouldn't be in this interface. | |
175 | */ | |
42e0a9aa TG |
176 | void (*apic_write)(unsigned long reg, u32 v); |
177 | void (*apic_write_atomic)(unsigned long reg, u32 v); | |
178 | u32 (*apic_read)(unsigned long reg); | |
bbab4f3b ZA |
179 | void (*setup_boot_clock)(void); |
180 | void (*setup_secondary_clock)(void); | |
294688c0 JF |
181 | |
182 | void (*startup_ipi_hook)(int phys_apicid, | |
183 | unsigned long start_eip, | |
184 | unsigned long start_esp); | |
13623d79 | 185 | #endif |
93b1eab3 JF |
186 | }; |
187 | ||
188 | struct pv_mmu_ops { | |
189 | /* | |
190 | * Called before/after init_mm pagetable setup. setup_start | |
191 | * may reset %cr3, and may pre-install parts of the pagetable; | |
192 | * pagetable setup is expected to preserve any existing | |
193 | * mapping. | |
194 | */ | |
195 | void (*pagetable_setup_start)(pgd_t *pgd_base); | |
196 | void (*pagetable_setup_done)(pgd_t *pgd_base); | |
197 | ||
198 | unsigned long (*read_cr2)(void); | |
199 | void (*write_cr2)(unsigned long); | |
200 | ||
201 | unsigned long (*read_cr3)(void); | |
202 | void (*write_cr3)(unsigned long); | |
203 | ||
204 | /* | |
205 | * Hooks for intercepting the creation/use/destruction of an | |
206 | * mm_struct. | |
207 | */ | |
208 | void (*activate_mm)(struct mm_struct *prev, | |
209 | struct mm_struct *next); | |
210 | void (*dup_mmap)(struct mm_struct *oldmm, | |
211 | struct mm_struct *mm); | |
212 | void (*exit_mmap)(struct mm_struct *mm); | |
213 | ||
13623d79 | 214 | |
294688c0 | 215 | /* TLB operations */ |
1a1eecd1 AK |
216 | void (*flush_tlb_user)(void); |
217 | void (*flush_tlb_kernel)(void); | |
f8822f42 | 218 | void (*flush_tlb_single)(unsigned long addr); |
d4c10477 JF |
219 | void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, |
220 | unsigned long va); | |
1a1eecd1 | 221 | |
294688c0 | 222 | /* Hooks for allocating/releasing pagetable pages */ |
fdb4c338 | 223 | void (*alloc_pt)(struct mm_struct *mm, u32 pfn); |
1a1eecd1 AK |
224 | void (*alloc_pd)(u32 pfn); |
225 | void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); | |
226 | void (*release_pt)(u32 pfn); | |
227 | void (*release_pd)(u32 pfn); | |
228 | ||
294688c0 | 229 | /* Pagetable manipulation functions */ |
1a1eecd1 | 230 | void (*set_pte)(pte_t *ptep, pte_t pteval); |
294688c0 JF |
231 | void (*set_pte_at)(struct mm_struct *mm, unsigned long addr, |
232 | pte_t *ptep, pte_t pteval); | |
1a1eecd1 | 233 | void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval); |
3dc494e8 | 234 | void (*pte_update)(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
294688c0 JF |
235 | void (*pte_update_defer)(struct mm_struct *mm, |
236 | unsigned long addr, pte_t *ptep); | |
3dc494e8 | 237 | |
5b8dd1e9 JF |
238 | pteval_t (*pte_val)(pte_t); |
239 | pte_t (*make_pte)(pteval_t pte); | |
240 | ||
241 | pgdval_t (*pgd_val)(pgd_t); | |
242 | pgd_t (*make_pgd)(pgdval_t pgd); | |
243 | ||
244 | #if PAGETABLE_LEVELS >= 3 | |
da181a8b | 245 | #ifdef CONFIG_X86_PAE |
1a1eecd1 | 246 | void (*set_pte_atomic)(pte_t *ptep, pte_t pteval); |
93b1eab3 JF |
247 | void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, |
248 | pte_t *ptep, pte_t pte); | |
93b1eab3 | 249 | void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
1a1eecd1 | 250 | void (*pmd_clear)(pmd_t *pmdp); |
3dc494e8 | 251 | |
5b8dd1e9 | 252 | #endif /* CONFIG_X86_PAE */ |
3dc494e8 | 253 | |
5b8dd1e9 | 254 | void (*set_pud)(pud_t *pudp, pud_t pudval); |
3dc494e8 | 255 | |
5b8dd1e9 JF |
256 | pmdval_t (*pmd_val)(pmd_t); |
257 | pmd_t (*make_pmd)(pmdval_t pmd); | |
258 | ||
259 | #if PAGETABLE_LEVELS == 4 | |
260 | pudval_t (*pud_val)(pud_t); | |
261 | pud_t (*make_pud)(pudval_t pud); | |
262 | #endif /* PAGETABLE_LEVELS == 4 */ | |
263 | #endif /* PAGETABLE_LEVELS >= 3 */ | |
da181a8b | 264 | |
93b1eab3 JF |
265 | #ifdef CONFIG_HIGHPTE |
266 | void *(*kmap_atomic_pte)(struct page *page, enum km_type type); | |
267 | #endif | |
8965c1c0 JF |
268 | |
269 | struct pv_lazy_ops lazy_mode; | |
93b1eab3 | 270 | }; |
9226d125 | 271 | |
93b1eab3 JF |
272 | /* This contains all the paravirt structures: we get a convenient |
273 | * number for each function using the offset which we use to indicate | |
274 | * what to patch. */ | |
275 | struct paravirt_patch_template | |
276 | { | |
277 | struct pv_init_ops pv_init_ops; | |
93b1eab3 JF |
278 | struct pv_time_ops pv_time_ops; |
279 | struct pv_cpu_ops pv_cpu_ops; | |
280 | struct pv_irq_ops pv_irq_ops; | |
281 | struct pv_apic_ops pv_apic_ops; | |
282 | struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f RR |
283 | }; |
284 | ||
93b1eab3 JF |
285 | extern struct pv_info pv_info; |
286 | extern struct pv_init_ops pv_init_ops; | |
93b1eab3 JF |
287 | extern struct pv_time_ops pv_time_ops; |
288 | extern struct pv_cpu_ops pv_cpu_ops; | |
289 | extern struct pv_irq_ops pv_irq_ops; | |
290 | extern struct pv_apic_ops pv_apic_ops; | |
291 | extern struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f | 292 | |
d5822035 | 293 | #define PARAVIRT_PATCH(x) \ |
93b1eab3 | 294 | (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) |
d5822035 | 295 | |
93b1eab3 JF |
296 | #define paravirt_type(op) \ |
297 | [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ | |
298 | [paravirt_opptr] "m" (op) | |
d5822035 JF |
299 | #define paravirt_clobber(clobber) \ |
300 | [paravirt_clobber] "i" (clobber) | |
301 | ||
294688c0 JF |
302 | /* |
303 | * Generate some code, and mark it as patchable by the | |
304 | * apply_paravirt() alternate instruction patcher. | |
305 | */ | |
d5822035 JF |
306 | #define _paravirt_alt(insn_string, type, clobber) \ |
307 | "771:\n\t" insn_string "\n" "772:\n" \ | |
308 | ".pushsection .parainstructions,\"a\"\n" \ | |
658be9d3 GOC |
309 | _ASM_ALIGN "\n" \ |
310 | _ASM_PTR " 771b\n" \ | |
d5822035 JF |
311 | " .byte " type "\n" \ |
312 | " .byte 772b-771b\n" \ | |
313 | " .short " clobber "\n" \ | |
314 | ".popsection\n" | |
315 | ||
294688c0 | 316 | /* Generate patchable code, with the default asm parameters. */ |
f8822f42 | 317 | #define paravirt_alt(insn_string) \ |
d5822035 JF |
318 | _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]") |
319 | ||
2f485ef5 GOC |
320 | /* Simple instruction patching code. */ |
321 | #define DEF_NATIVE(ops, name, code) \ | |
322 | extern const char start_##ops##_##name[], end_##ops##_##name[]; \ | |
323 | asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":") | |
324 | ||
63f70270 JF |
325 | unsigned paravirt_patch_nop(void); |
326 | unsigned paravirt_patch_ignore(unsigned len); | |
ab144f5e AK |
327 | unsigned paravirt_patch_call(void *insnbuf, |
328 | const void *target, u16 tgt_clobbers, | |
329 | unsigned long addr, u16 site_clobbers, | |
63f70270 | 330 | unsigned len); |
93b1eab3 | 331 | unsigned paravirt_patch_jmp(void *insnbuf, const void *target, |
ab144f5e AK |
332 | unsigned long addr, unsigned len); |
333 | unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, | |
334 | unsigned long addr, unsigned len); | |
63f70270 | 335 | |
ab144f5e | 336 | unsigned paravirt_patch_insns(void *insnbuf, unsigned len, |
63f70270 JF |
337 | const char *start, const char *end); |
338 | ||
2f485ef5 GOC |
339 | unsigned native_patch(u8 type, u16 clobbers, void *ibuf, |
340 | unsigned long addr, unsigned len); | |
341 | ||
d572929c | 342 | int paravirt_disable_iospace(void); |
63f70270 | 343 | |
294688c0 JF |
344 | /* |
345 | * This generates an indirect call based on the operation type number. | |
346 | * The type number, computed in PARAVIRT_PATCH, is derived from the | |
93b1eab3 JF |
347 | * offset into the paravirt_patch_template structure, and can therefore be |
348 | * freely converted back into a structure offset. | |
294688c0 | 349 | */ |
93b1eab3 | 350 | #define PARAVIRT_CALL "call *%[paravirt_opptr];" |
294688c0 JF |
351 | |
352 | /* | |
93b1eab3 JF |
353 | * These macros are intended to wrap calls through one of the paravirt |
354 | * ops structs, so that they can be later identified and patched at | |
294688c0 JF |
355 | * runtime. |
356 | * | |
357 | * Normally, a call to a pv_op function is a simple indirect call: | |
a4746364 | 358 | * (pv_op_struct.operations)(args...). |
294688c0 JF |
359 | * |
360 | * Unfortunately, this is a relatively slow operation for modern CPUs, | |
361 | * because it cannot necessarily determine what the destination | |
362 | * address is. In this case, the address is a runtime constant, so at | |
363 | * the very least we can patch the call to e a simple direct call, or | |
364 | * ideally, patch an inline implementation into the callsite. (Direct | |
365 | * calls are essentially free, because the call and return addresses | |
366 | * are completely predictable.) | |
367 | * | |
a4746364 | 368 | * For i386, these macros rely on the standard gcc "regparm(3)" calling |
294688c0 JF |
369 | * convention, in which the first three arguments are placed in %eax, |
370 | * %edx, %ecx (in that order), and the remaining arguments are placed | |
371 | * on the stack. All caller-save registers (eax,edx,ecx) are expected | |
372 | * to be modified (either clobbered or used for return values). | |
a4746364 GOC |
373 | * X86_64, on the other hand, already specifies a register-based calling |
374 | * conventions, returning at %rax, with parameteres going on %rdi, %rsi, | |
375 | * %rdx, and %rcx. Note that for this reason, x86_64 does not need any | |
376 | * special handling for dealing with 4 arguments, unlike i386. | |
377 | * However, x86_64 also have to clobber all caller saved registers, which | |
378 | * unfortunately, are quite a bit (r8 - r11) | |
294688c0 JF |
379 | * |
380 | * The call instruction itself is marked by placing its start address | |
381 | * and size into the .parainstructions section, so that | |
382 | * apply_paravirt() in arch/i386/kernel/alternative.c can do the | |
93b1eab3 | 383 | * appropriate patching under the control of the backend pv_init_ops |
294688c0 JF |
384 | * implementation. |
385 | * | |
386 | * Unfortunately there's no way to get gcc to generate the args setup | |
387 | * for the call, and then allow the call itself to be generated by an | |
388 | * inline asm. Because of this, we must do the complete arg setup and | |
389 | * return value handling from within these macros. This is fairly | |
390 | * cumbersome. | |
391 | * | |
392 | * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments. | |
393 | * It could be extended to more arguments, but there would be little | |
394 | * to be gained from that. For each number of arguments, there are | |
395 | * the two VCALL and CALL variants for void and non-void functions. | |
396 | * | |
397 | * When there is a return value, the invoker of the macro must specify | |
398 | * the return type. The macro then uses sizeof() on that type to | |
399 | * determine whether its a 32 or 64 bit value, and places the return | |
400 | * in the right register(s) (just %eax for 32-bit, and %edx:%eax for | |
a4746364 GOC |
401 | * 64-bit). For x86_64 machines, it just returns at %rax regardless of |
402 | * the return value size. | |
294688c0 JF |
403 | * |
404 | * 64-bit arguments are passed as a pair of adjacent 32-bit arguments | |
a4746364 GOC |
405 | * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments |
406 | * in low,high order | |
294688c0 JF |
407 | * |
408 | * Small structures are passed and returned in registers. The macro | |
409 | * calling convention can't directly deal with this, so the wrapper | |
410 | * functions must do this. | |
411 | * | |
412 | * These PVOP_* macros are only defined within this header. This | |
413 | * means that all uses must be wrapped in inline functions. This also | |
414 | * makes sure the incoming and outgoing types are always correct. | |
415 | */ | |
a4746364 GOC |
416 | #ifdef CONFIG_X86_32 |
417 | #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx | |
418 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS | |
419 | #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \ | |
420 | "=c" (__ecx) | |
421 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS | |
422 | #define EXTRA_CLOBBERS | |
423 | #define VEXTRA_CLOBBERS | |
424 | #else | |
425 | #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx | |
426 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax | |
427 | #define PVOP_VCALL_CLOBBERS "=D" (__edi), \ | |
428 | "=S" (__esi), "=d" (__edx), \ | |
429 | "=c" (__ecx) | |
430 | ||
431 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax) | |
432 | ||
433 | #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11" | |
434 | #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11" | |
435 | #endif | |
436 | ||
1a45b7aa | 437 | #define __PVOP_CALL(rettype, op, pre, post, ...) \ |
f8822f42 | 438 | ({ \ |
1a45b7aa | 439 | rettype __ret; \ |
a4746364 GOC |
440 | PVOP_CALL_ARGS; \ |
441 | /* This is 32-bit specific, but is okay in 64-bit */ \ | |
442 | /* since this condition will never hold */ \ | |
1a45b7aa JF |
443 | if (sizeof(rettype) > sizeof(unsigned long)) { \ |
444 | asm volatile(pre \ | |
445 | paravirt_alt(PARAVIRT_CALL) \ | |
446 | post \ | |
a4746364 | 447 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
448 | : paravirt_type(op), \ |
449 | paravirt_clobber(CLBR_ANY), \ | |
450 | ##__VA_ARGS__ \ | |
a4746364 | 451 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 452 | __ret = (rettype)((((u64)__edx) << 32) | __eax); \ |
f8822f42 | 453 | } else { \ |
1a45b7aa | 454 | asm volatile(pre \ |
f8822f42 | 455 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 456 | post \ |
a4746364 | 457 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
458 | : paravirt_type(op), \ |
459 | paravirt_clobber(CLBR_ANY), \ | |
460 | ##__VA_ARGS__ \ | |
a4746364 | 461 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 462 | __ret = (rettype)__eax; \ |
f8822f42 JF |
463 | } \ |
464 | __ret; \ | |
465 | }) | |
1a45b7aa | 466 | #define __PVOP_VCALL(op, pre, post, ...) \ |
f8822f42 | 467 | ({ \ |
a4746364 | 468 | PVOP_VCALL_ARGS; \ |
1a45b7aa | 469 | asm volatile(pre \ |
f8822f42 | 470 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 471 | post \ |
a4746364 | 472 | : PVOP_VCALL_CLOBBERS \ |
1a45b7aa JF |
473 | : paravirt_type(op), \ |
474 | paravirt_clobber(CLBR_ANY), \ | |
475 | ##__VA_ARGS__ \ | |
a4746364 | 476 | : "memory", "cc" VEXTRA_CLOBBERS); \ |
f8822f42 JF |
477 | }) |
478 | ||
1a45b7aa JF |
479 | #define PVOP_CALL0(rettype, op) \ |
480 | __PVOP_CALL(rettype, op, "", "") | |
481 | #define PVOP_VCALL0(op) \ | |
482 | __PVOP_VCALL(op, "", "") | |
483 | ||
484 | #define PVOP_CALL1(rettype, op, arg1) \ | |
a4746364 | 485 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa | 486 | #define PVOP_VCALL1(op, arg1) \ |
a4746364 | 487 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa JF |
488 | |
489 | #define PVOP_CALL2(rettype, op, arg1, arg2) \ | |
a4746364 GOC |
490 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
491 | "1" ((unsigned long)(arg2))) | |
1a45b7aa | 492 | #define PVOP_VCALL2(op, arg1, arg2) \ |
a4746364 GOC |
493 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
494 | "1" ((unsigned long)(arg2))) | |
1a45b7aa JF |
495 | |
496 | #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \ | |
a4746364 GOC |
497 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
498 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 499 | #define PVOP_VCALL3(op, arg1, arg2, arg3) \ |
a4746364 GOC |
500 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
501 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 502 | |
a4746364 GOC |
503 | /* This is the only difference in x86_64. We can make it much simpler */ |
504 | #ifdef CONFIG_X86_32 | |
1a45b7aa JF |
505 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ |
506 | __PVOP_CALL(rettype, op, \ | |
507 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
508 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
509 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
510 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
511 | __PVOP_VCALL(op, \ | |
512 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
513 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
514 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
a4746364 GOC |
515 | #else |
516 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ | |
517 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ | |
518 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
519 | "3"((unsigned long)(arg4))) | |
520 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
521 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ | |
522 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
523 | "3"((unsigned long)(arg4))) | |
524 | #endif | |
1a45b7aa | 525 | |
f8822f42 JF |
526 | static inline int paravirt_enabled(void) |
527 | { | |
93b1eab3 | 528 | return pv_info.paravirt_enabled; |
f8822f42 | 529 | } |
d3561b7f | 530 | |
faca6227 | 531 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
532 | struct thread_struct *thread) |
533 | { | |
faca6227 | 534 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
535 | } |
536 | ||
93b1eab3 | 537 | #define ARCH_SETUP pv_init_ops.arch_setup(); |
d3561b7f RR |
538 | static inline unsigned long get_wallclock(void) |
539 | { | |
93b1eab3 | 540 | return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); |
d3561b7f RR |
541 | } |
542 | ||
543 | static inline int set_wallclock(unsigned long nowtime) | |
544 | { | |
93b1eab3 | 545 | return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); |
d3561b7f RR |
546 | } |
547 | ||
e30fab3a | 548 | static inline void (*choose_time_init(void))(void) |
d3561b7f | 549 | { |
93b1eab3 | 550 | return pv_time_ops.time_init; |
d3561b7f RR |
551 | } |
552 | ||
553 | /* The paravirtualized CPUID instruction. */ | |
554 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
555 | unsigned int *ecx, unsigned int *edx) | |
556 | { | |
93b1eab3 | 557 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
558 | } |
559 | ||
560 | /* | |
561 | * These special macros can be used to get or set a debugging register | |
562 | */ | |
f8822f42 JF |
563 | static inline unsigned long paravirt_get_debugreg(int reg) |
564 | { | |
93b1eab3 | 565 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
566 | } |
567 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
568 | static inline void set_debugreg(unsigned long val, int reg) | |
569 | { | |
93b1eab3 | 570 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 571 | } |
d3561b7f | 572 | |
f8822f42 JF |
573 | static inline void clts(void) |
574 | { | |
93b1eab3 | 575 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 576 | } |
d3561b7f | 577 | |
f8822f42 JF |
578 | static inline unsigned long read_cr0(void) |
579 | { | |
93b1eab3 | 580 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 581 | } |
d3561b7f | 582 | |
f8822f42 JF |
583 | static inline void write_cr0(unsigned long x) |
584 | { | |
93b1eab3 | 585 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
586 | } |
587 | ||
588 | static inline unsigned long read_cr2(void) | |
589 | { | |
93b1eab3 | 590 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
591 | } |
592 | ||
593 | static inline void write_cr2(unsigned long x) | |
594 | { | |
93b1eab3 | 595 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
596 | } |
597 | ||
598 | static inline unsigned long read_cr3(void) | |
599 | { | |
93b1eab3 | 600 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 601 | } |
d3561b7f | 602 | |
f8822f42 JF |
603 | static inline void write_cr3(unsigned long x) |
604 | { | |
93b1eab3 | 605 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 606 | } |
d3561b7f | 607 | |
f8822f42 JF |
608 | static inline unsigned long read_cr4(void) |
609 | { | |
93b1eab3 | 610 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
611 | } |
612 | static inline unsigned long read_cr4_safe(void) | |
613 | { | |
93b1eab3 | 614 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 615 | } |
d3561b7f | 616 | |
f8822f42 JF |
617 | static inline void write_cr4(unsigned long x) |
618 | { | |
93b1eab3 | 619 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 620 | } |
3dc494e8 | 621 | |
4c9890c2 GOC |
622 | static inline unsigned long read_cr8(void) |
623 | { | |
624 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
625 | } | |
626 | ||
627 | static inline void write_cr8(unsigned long x) | |
628 | { | |
629 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
630 | } | |
631 | ||
d3561b7f RR |
632 | static inline void raw_safe_halt(void) |
633 | { | |
93b1eab3 | 634 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
635 | } |
636 | ||
637 | static inline void halt(void) | |
638 | { | |
93b1eab3 | 639 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
f8822f42 JF |
640 | } |
641 | ||
642 | static inline void wbinvd(void) | |
643 | { | |
93b1eab3 | 644 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 645 | } |
d3561b7f | 646 | |
93b1eab3 | 647 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 648 | |
f8822f42 JF |
649 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
650 | { | |
93b1eab3 | 651 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 JF |
652 | } |
653 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | |
654 | { | |
93b1eab3 | 655 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
656 | } |
657 | ||
90a0a06a | 658 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
f8822f42 JF |
659 | #define rdmsr(msr,val1,val2) do { \ |
660 | int _err; \ | |
661 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
662 | val1 = (u32)_l; \ | |
663 | val2 = _l >> 32; \ | |
d3561b7f RR |
664 | } while(0) |
665 | ||
f8822f42 JF |
666 | #define wrmsr(msr,val1,val2) do { \ |
667 | paravirt_write_msr(msr, val1, val2); \ | |
d3561b7f RR |
668 | } while(0) |
669 | ||
f8822f42 JF |
670 | #define rdmsrl(msr,val) do { \ |
671 | int _err; \ | |
672 | val = paravirt_read_msr(msr, &_err); \ | |
d3561b7f RR |
673 | } while(0) |
674 | ||
b9e3614f | 675 | #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
f8822f42 | 676 | #define wrmsr_safe(msr,a,b) paravirt_write_msr(msr, a, b) |
d3561b7f RR |
677 | |
678 | /* rdmsr with exception handling */ | |
f8822f42 JF |
679 | #define rdmsr_safe(msr,a,b) ({ \ |
680 | int _err; \ | |
681 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
682 | (*a) = (u32)_l; \ | |
683 | (*b) = _l >> 32; \ | |
d3561b7f RR |
684 | _err; }) |
685 | ||
f8822f42 JF |
686 | |
687 | static inline u64 paravirt_read_tsc(void) | |
688 | { | |
93b1eab3 | 689 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 690 | } |
d3561b7f | 691 | |
f8822f42 JF |
692 | #define rdtscl(low) do { \ |
693 | u64 _l = paravirt_read_tsc(); \ | |
694 | low = (int)_l; \ | |
d3561b7f RR |
695 | } while(0) |
696 | ||
f8822f42 | 697 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 698 | |
688340ea JF |
699 | static inline unsigned long long paravirt_sched_clock(void) |
700 | { | |
93b1eab3 | 701 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 702 | } |
93b1eab3 | 703 | #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) |
6cb9a835 | 704 | |
f8822f42 JF |
705 | static inline unsigned long long paravirt_read_pmc(int counter) |
706 | { | |
93b1eab3 | 707 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 708 | } |
d3561b7f | 709 | |
f8822f42 JF |
710 | #define rdpmc(counter,low,high) do { \ |
711 | u64 _l = paravirt_read_pmc(counter); \ | |
712 | low = (u32)_l; \ | |
713 | high = _l >> 32; \ | |
714 | } while(0) | |
3dc494e8 | 715 | |
e5aaac44 GOC |
716 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
717 | { | |
718 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | |
719 | } | |
720 | ||
721 | #define rdtscp(low, high, aux) \ | |
722 | do { \ | |
723 | int __aux; \ | |
724 | unsigned long __val = paravirt_rdtscp(&__aux); \ | |
725 | (low) = (u32)__val; \ | |
726 | (high) = (u32)(__val >> 32); \ | |
727 | (aux) = __aux; \ | |
728 | } while (0) | |
729 | ||
730 | #define rdtscpll(val, aux) \ | |
731 | do { \ | |
732 | unsigned long __aux; \ | |
733 | val = paravirt_rdtscp(&__aux); \ | |
734 | (aux) = __aux; \ | |
735 | } while (0) | |
736 | ||
f8822f42 JF |
737 | static inline void load_TR_desc(void) |
738 | { | |
93b1eab3 | 739 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 740 | } |
6b68f01b | 741 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 742 | { |
93b1eab3 | 743 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 744 | } |
6b68f01b | 745 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 746 | { |
93b1eab3 | 747 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
748 | } |
749 | static inline void set_ldt(const void *addr, unsigned entries) | |
750 | { | |
93b1eab3 | 751 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 752 | } |
6b68f01b | 753 | static inline void store_gdt(struct desc_ptr *dtr) |
f8822f42 | 754 | { |
93b1eab3 | 755 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 | 756 | } |
6b68f01b | 757 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 758 | { |
93b1eab3 | 759 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
760 | } |
761 | static inline unsigned long paravirt_store_tr(void) | |
762 | { | |
93b1eab3 | 763 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
764 | } |
765 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
766 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
767 | { | |
93b1eab3 | 768 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 769 | } |
75b8bb3e GOC |
770 | |
771 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, | |
772 | const void *desc) | |
f8822f42 | 773 | { |
75b8bb3e | 774 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 775 | } |
014b15be GOC |
776 | |
777 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
778 | void *desc, int type) | |
f8822f42 | 779 | { |
014b15be | 780 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 781 | } |
014b15be | 782 | |
8d947344 | 783 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 784 | { |
8d947344 | 785 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
786 | } |
787 | static inline void set_iopl_mask(unsigned mask) | |
788 | { | |
93b1eab3 | 789 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 790 | } |
3dc494e8 | 791 | |
d3561b7f RR |
792 | /* The paravirtualized I/O functions */ |
793 | static inline void slow_down_io(void) { | |
93b1eab3 | 794 | pv_cpu_ops.io_delay(); |
d3561b7f | 795 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
796 | pv_cpu_ops.io_delay(); |
797 | pv_cpu_ops.io_delay(); | |
798 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
799 | #endif |
800 | } | |
801 | ||
13623d79 RR |
802 | #ifdef CONFIG_X86_LOCAL_APIC |
803 | /* | |
804 | * Basic functions accessing APICs. | |
805 | */ | |
42e0a9aa | 806 | static inline void apic_write(unsigned long reg, u32 v) |
13623d79 | 807 | { |
93b1eab3 | 808 | PVOP_VCALL2(pv_apic_ops.apic_write, reg, v); |
13623d79 RR |
809 | } |
810 | ||
42e0a9aa | 811 | static inline void apic_write_atomic(unsigned long reg, u32 v) |
13623d79 | 812 | { |
93b1eab3 | 813 | PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v); |
13623d79 RR |
814 | } |
815 | ||
42e0a9aa | 816 | static inline u32 apic_read(unsigned long reg) |
13623d79 | 817 | { |
93b1eab3 | 818 | return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg); |
13623d79 | 819 | } |
bbab4f3b ZA |
820 | |
821 | static inline void setup_boot_clock(void) | |
822 | { | |
93b1eab3 | 823 | PVOP_VCALL0(pv_apic_ops.setup_boot_clock); |
bbab4f3b ZA |
824 | } |
825 | ||
826 | static inline void setup_secondary_clock(void) | |
827 | { | |
93b1eab3 | 828 | PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); |
bbab4f3b | 829 | } |
13623d79 RR |
830 | #endif |
831 | ||
6996d3b6 JF |
832 | static inline void paravirt_post_allocator_init(void) |
833 | { | |
93b1eab3 JF |
834 | if (pv_init_ops.post_allocator_init) |
835 | (*pv_init_ops.post_allocator_init)(); | |
6996d3b6 JF |
836 | } |
837 | ||
b239fb25 JF |
838 | static inline void paravirt_pagetable_setup_start(pgd_t *base) |
839 | { | |
93b1eab3 | 840 | (*pv_mmu_ops.pagetable_setup_start)(base); |
b239fb25 JF |
841 | } |
842 | ||
843 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
844 | { | |
93b1eab3 | 845 | (*pv_mmu_ops.pagetable_setup_done)(base); |
b239fb25 | 846 | } |
3dc494e8 | 847 | |
ae5da273 ZA |
848 | #ifdef CONFIG_SMP |
849 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
850 | unsigned long start_esp) | |
851 | { | |
93b1eab3 JF |
852 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
853 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
854 | } |
855 | #endif | |
13623d79 | 856 | |
d6dd61c8 JF |
857 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
858 | struct mm_struct *next) | |
859 | { | |
93b1eab3 | 860 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
861 | } |
862 | ||
863 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
864 | struct mm_struct *mm) | |
865 | { | |
93b1eab3 | 866 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
867 | } |
868 | ||
869 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
870 | { | |
93b1eab3 | 871 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
872 | } |
873 | ||
f8822f42 JF |
874 | static inline void __flush_tlb(void) |
875 | { | |
93b1eab3 | 876 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
877 | } |
878 | static inline void __flush_tlb_global(void) | |
879 | { | |
93b1eab3 | 880 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
881 | } |
882 | static inline void __flush_tlb_single(unsigned long addr) | |
883 | { | |
93b1eab3 | 884 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 885 | } |
da181a8b | 886 | |
d4c10477 JF |
887 | static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, |
888 | unsigned long va) | |
889 | { | |
93b1eab3 | 890 | PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); |
d4c10477 JF |
891 | } |
892 | ||
fdb4c338 | 893 | static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 894 | { |
93b1eab3 | 895 | PVOP_VCALL2(pv_mmu_ops.alloc_pt, mm, pfn); |
f8822f42 JF |
896 | } |
897 | static inline void paravirt_release_pt(unsigned pfn) | |
898 | { | |
93b1eab3 | 899 | PVOP_VCALL1(pv_mmu_ops.release_pt, pfn); |
f8822f42 | 900 | } |
c119ecce | 901 | |
f8822f42 JF |
902 | static inline void paravirt_alloc_pd(unsigned pfn) |
903 | { | |
93b1eab3 | 904 | PVOP_VCALL1(pv_mmu_ops.alloc_pd, pfn); |
f8822f42 | 905 | } |
c119ecce | 906 | |
f8822f42 JF |
907 | static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn, |
908 | unsigned start, unsigned count) | |
909 | { | |
93b1eab3 | 910 | PVOP_VCALL4(pv_mmu_ops.alloc_pd_clone, pfn, clonepfn, start, count); |
f8822f42 JF |
911 | } |
912 | static inline void paravirt_release_pd(unsigned pfn) | |
da181a8b | 913 | { |
93b1eab3 | 914 | PVOP_VCALL1(pv_mmu_ops.release_pd, pfn); |
da181a8b RR |
915 | } |
916 | ||
ce6234b5 JF |
917 | #ifdef CONFIG_HIGHPTE |
918 | static inline void *kmap_atomic_pte(struct page *page, enum km_type type) | |
919 | { | |
920 | unsigned long ret; | |
93b1eab3 | 921 | ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type); |
ce6234b5 JF |
922 | return (void *)ret; |
923 | } | |
924 | #endif | |
925 | ||
f8822f42 JF |
926 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
927 | pte_t *ptep) | |
da181a8b | 928 | { |
93b1eab3 | 929 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b RR |
930 | } |
931 | ||
f8822f42 JF |
932 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
933 | pte_t *ptep) | |
da181a8b | 934 | { |
93b1eab3 | 935 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
936 | } |
937 | ||
773221f4 | 938 | static inline pte_t __pte(pteval_t val) |
da181a8b | 939 | { |
773221f4 JF |
940 | pteval_t ret; |
941 | ||
942 | if (sizeof(pteval_t) > sizeof(long)) | |
943 | ret = PVOP_CALL2(pteval_t, | |
944 | pv_mmu_ops.make_pte, | |
945 | val, (u64)val >> 32); | |
946 | else | |
947 | ret = PVOP_CALL1(pteval_t, | |
948 | pv_mmu_ops.make_pte, | |
949 | val); | |
950 | ||
c8e5393a | 951 | return (pte_t) { .pte = ret }; |
da181a8b RR |
952 | } |
953 | ||
773221f4 JF |
954 | static inline pteval_t pte_val(pte_t pte) |
955 | { | |
956 | pteval_t ret; | |
957 | ||
958 | if (sizeof(pteval_t) > sizeof(long)) | |
959 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val, | |
960 | pte.pte, (u64)pte.pte >> 32); | |
961 | else | |
962 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val, | |
963 | pte.pte); | |
964 | ||
965 | return ret; | |
966 | } | |
967 | ||
ef38503e | 968 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 969 | { |
ef38503e JF |
970 | pgdval_t ret; |
971 | ||
972 | if (sizeof(pgdval_t) > sizeof(long)) | |
973 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd, | |
974 | val, (u64)val >> 32); | |
975 | else | |
976 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd, | |
977 | val); | |
978 | ||
979 | return (pgd_t) { ret }; | |
980 | } | |
981 | ||
982 | static inline pgdval_t pgd_val(pgd_t pgd) | |
983 | { | |
984 | pgdval_t ret; | |
985 | ||
986 | if (sizeof(pgdval_t) > sizeof(long)) | |
987 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val, | |
988 | pgd.pgd, (u64)pgd.pgd >> 32); | |
989 | else | |
990 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val, | |
991 | pgd.pgd); | |
992 | ||
993 | return ret; | |
f8822f42 JF |
994 | } |
995 | ||
4eed80cd JF |
996 | static inline void set_pte(pte_t *ptep, pte_t pte) |
997 | { | |
998 | if (sizeof(pteval_t) > sizeof(long)) | |
999 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
1000 | pte.pte, (u64)pte.pte >> 32); | |
1001 | else | |
1002 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
1003 | pte.pte); | |
1004 | } | |
1005 | ||
1006 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1007 | pte_t *ptep, pte_t pte) | |
1008 | { | |
1009 | if (sizeof(pteval_t) > sizeof(long)) | |
1010 | /* 5 arg words */ | |
1011 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
1012 | else | |
1013 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
1014 | } | |
1015 | ||
60b3f626 JF |
1016 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
1017 | { | |
1018 | pmdval_t val = native_pmd_val(pmd); | |
1019 | ||
1020 | if (sizeof(pmdval_t) > sizeof(long)) | |
1021 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
1022 | else | |
1023 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
1024 | } | |
1025 | ||
4eed80cd JF |
1026 | #ifdef CONFIG_X86_PAE |
1027 | /* Special-case pte-setting operations for PAE, which can't update a | |
1028 | 64-bit pte atomically */ | |
1029 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1030 | { | |
1031 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
1032 | pte.pte, pte.pte >> 32); | |
1033 | } | |
1034 | ||
1035 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1036 | pte_t *ptep, pte_t pte) | |
1037 | { | |
1038 | /* 5 arg words */ | |
1039 | pv_mmu_ops.set_pte_present(mm, addr, ptep, pte); | |
1040 | } | |
1041 | ||
1042 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1043 | pte_t *ptep) | |
1044 | { | |
1045 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
1046 | } | |
60b3f626 JF |
1047 | |
1048 | static inline void pmd_clear(pmd_t *pmdp) | |
1049 | { | |
1050 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
1051 | } | |
4eed80cd JF |
1052 | #else /* !CONFIG_X86_PAE */ |
1053 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1054 | { | |
1055 | set_pte(ptep, pte); | |
1056 | } | |
1057 | ||
1058 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1059 | pte_t *ptep, pte_t pte) | |
1060 | { | |
1061 | set_pte(ptep, pte); | |
1062 | } | |
1063 | ||
1064 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1065 | pte_t *ptep) | |
1066 | { | |
1067 | set_pte_at(mm, addr, ptep, __pte(0)); | |
1068 | } | |
60b3f626 JF |
1069 | |
1070 | static inline void pmd_clear(pmd_t *pmdp) | |
1071 | { | |
1072 | set_pmd(pmdp, __pmd(0)); | |
1073 | } | |
4eed80cd JF |
1074 | #endif /* CONFIG_X86_PAE */ |
1075 | ||
a632da2f JF |
1076 | #if PAGETABLE_LEVELS >= 3 |
1077 | static inline pmd_t __pmd(pmdval_t val) | |
f8822f42 | 1078 | { |
a632da2f JF |
1079 | pmdval_t ret; |
1080 | ||
1081 | if (sizeof(pmdval_t) > sizeof(long)) | |
1082 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd, | |
1083 | val, (u64)val >> 32); | |
1084 | else | |
1085 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd, | |
1086 | val); | |
1087 | ||
1088 | return (pmd_t) { ret }; | |
f8822f42 JF |
1089 | } |
1090 | ||
a632da2f | 1091 | static inline pmdval_t pmd_val(pmd_t pmd) |
f8822f42 | 1092 | { |
a632da2f JF |
1093 | pmdval_t ret; |
1094 | ||
1095 | if (sizeof(pmdval_t) > sizeof(long)) | |
1096 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val, | |
1097 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1098 | else | |
1099 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val, | |
1100 | pmd.pmd); | |
1101 | ||
1102 | return ret; | |
f8822f42 JF |
1103 | } |
1104 | ||
28c6075c | 1105 | static inline void set_pud(pud_t *pudp, pud_t pud) |
da181a8b | 1106 | { |
28c6075c | 1107 | pudval_t val = native_pud_val(pud); |
da181a8b | 1108 | |
28c6075c JF |
1109 | if (sizeof(pudval_t) > sizeof(long)) |
1110 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
1111 | val, (u64)val >> 32); | |
1112 | else | |
1113 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
1114 | val); | |
1115 | } | |
1116 | #endif /* PAGETABLE_LEVELS >= 3 */ | |
da181a8b | 1117 | |
8965c1c0 JF |
1118 | /* Lazy mode for batching updates / context switch */ |
1119 | enum paravirt_lazy_mode { | |
1120 | PARAVIRT_LAZY_NONE, | |
1121 | PARAVIRT_LAZY_MMU, | |
1122 | PARAVIRT_LAZY_CPU, | |
1123 | }; | |
1124 | ||
1125 | enum paravirt_lazy_mode paravirt_get_lazy_mode(void); | |
1126 | void paravirt_enter_lazy_cpu(void); | |
1127 | void paravirt_leave_lazy_cpu(void); | |
1128 | void paravirt_enter_lazy_mmu(void); | |
1129 | void paravirt_leave_lazy_mmu(void); | |
1130 | void paravirt_leave_lazy(enum paravirt_lazy_mode mode); | |
1131 | ||
9226d125 | 1132 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
f8822f42 JF |
1133 | static inline void arch_enter_lazy_cpu_mode(void) |
1134 | { | |
8965c1c0 | 1135 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter); |
f8822f42 JF |
1136 | } |
1137 | ||
1138 | static inline void arch_leave_lazy_cpu_mode(void) | |
1139 | { | |
8965c1c0 | 1140 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave); |
f8822f42 JF |
1141 | } |
1142 | ||
1143 | static inline void arch_flush_lazy_cpu_mode(void) | |
1144 | { | |
8965c1c0 JF |
1145 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) { |
1146 | arch_leave_lazy_cpu_mode(); | |
1147 | arch_enter_lazy_cpu_mode(); | |
1148 | } | |
f8822f42 JF |
1149 | } |
1150 | ||
9226d125 ZA |
1151 | |
1152 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f8822f42 JF |
1153 | static inline void arch_enter_lazy_mmu_mode(void) |
1154 | { | |
8965c1c0 | 1155 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
1156 | } |
1157 | ||
1158 | static inline void arch_leave_lazy_mmu_mode(void) | |
1159 | { | |
8965c1c0 | 1160 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
1161 | } |
1162 | ||
1163 | static inline void arch_flush_lazy_mmu_mode(void) | |
1164 | { | |
8965c1c0 JF |
1165 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) { |
1166 | arch_leave_lazy_mmu_mode(); | |
1167 | arch_enter_lazy_mmu_mode(); | |
1168 | } | |
f8822f42 | 1169 | } |
9226d125 | 1170 | |
45876233 JF |
1171 | void _paravirt_nop(void); |
1172 | #define paravirt_nop ((void *)_paravirt_nop) | |
1173 | ||
139ec7c4 | 1174 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
98de032b | 1175 | struct paravirt_patch_site { |
139ec7c4 RR |
1176 | u8 *instr; /* original instructions */ |
1177 | u8 instrtype; /* type of this instruction */ | |
1178 | u8 len; /* length of original instruction */ | |
1179 | u16 clobbers; /* what registers you may clobber */ | |
1180 | }; | |
1181 | ||
98de032b JF |
1182 | extern struct paravirt_patch_site __parainstructions[], |
1183 | __parainstructions_end[]; | |
1184 | ||
2e47d3e6 GOC |
1185 | #ifdef CONFIG_X86_32 |
1186 | #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;" | |
1187 | #define PV_RESTORE_REGS "popl %%edx; popl %%ecx" | |
1188 | #define PV_FLAGS_ARG "0" | |
1189 | #define PV_EXTRA_CLOBBERS | |
1190 | #define PV_VEXTRA_CLOBBERS | |
1191 | #else | |
1192 | /* We save some registers, but all of them, that's too much. We clobber all | |
1193 | * caller saved registers but the argument parameter */ | |
1194 | #define PV_SAVE_REGS "pushq %%rdi;" | |
1195 | #define PV_RESTORE_REGS "popq %%rdi;" | |
1196 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx" | |
1197 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx" | |
1198 | #define PV_FLAGS_ARG "D" | |
1199 | #endif | |
1200 | ||
139ec7c4 RR |
1201 | static inline unsigned long __raw_local_save_flags(void) |
1202 | { | |
1203 | unsigned long f; | |
1204 | ||
2e47d3e6 | 1205 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1206 | PARAVIRT_CALL |
2e47d3e6 | 1207 | PV_RESTORE_REGS) |
d5822035 | 1208 | : "=a"(f) |
93b1eab3 | 1209 | : paravirt_type(pv_irq_ops.save_fl), |
42c24fa2 | 1210 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1211 | : "memory", "cc" PV_VEXTRA_CLOBBERS); |
139ec7c4 RR |
1212 | return f; |
1213 | } | |
1214 | ||
1215 | static inline void raw_local_irq_restore(unsigned long f) | |
1216 | { | |
2e47d3e6 | 1217 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1218 | PARAVIRT_CALL |
2e47d3e6 | 1219 | PV_RESTORE_REGS) |
d5822035 | 1220 | : "=a"(f) |
2e47d3e6 | 1221 | : PV_FLAGS_ARG(f), |
93b1eab3 | 1222 | paravirt_type(pv_irq_ops.restore_fl), |
d5822035 | 1223 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1224 | : "memory", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1225 | } |
1226 | ||
1227 | static inline void raw_local_irq_disable(void) | |
1228 | { | |
2e47d3e6 | 1229 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1230 | PARAVIRT_CALL |
2e47d3e6 | 1231 | PV_RESTORE_REGS) |
d5822035 | 1232 | : |
93b1eab3 | 1233 | : paravirt_type(pv_irq_ops.irq_disable), |
d5822035 | 1234 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1235 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1236 | } |
1237 | ||
1238 | static inline void raw_local_irq_enable(void) | |
1239 | { | |
2e47d3e6 | 1240 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1241 | PARAVIRT_CALL |
2e47d3e6 | 1242 | PV_RESTORE_REGS) |
d5822035 | 1243 | : |
93b1eab3 | 1244 | : paravirt_type(pv_irq_ops.irq_enable), |
d5822035 | 1245 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1246 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1247 | } |
1248 | ||
1249 | static inline unsigned long __raw_local_irq_save(void) | |
1250 | { | |
1251 | unsigned long f; | |
1252 | ||
d5822035 JF |
1253 | f = __raw_local_save_flags(); |
1254 | raw_local_irq_disable(); | |
139ec7c4 RR |
1255 | return f; |
1256 | } | |
1257 | ||
294688c0 | 1258 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 1259 | #undef PARAVIRT_CALL |
1a45b7aa JF |
1260 | #undef __PVOP_CALL |
1261 | #undef __PVOP_VCALL | |
f8822f42 JF |
1262 | #undef PVOP_VCALL0 |
1263 | #undef PVOP_CALL0 | |
1264 | #undef PVOP_VCALL1 | |
1265 | #undef PVOP_CALL1 | |
1266 | #undef PVOP_VCALL2 | |
1267 | #undef PVOP_CALL2 | |
1268 | #undef PVOP_VCALL3 | |
1269 | #undef PVOP_CALL3 | |
1270 | #undef PVOP_VCALL4 | |
1271 | #undef PVOP_CALL4 | |
139ec7c4 | 1272 | |
d3561b7f RR |
1273 | #else /* __ASSEMBLY__ */ |
1274 | ||
658be9d3 | 1275 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
1276 | 771:; \ |
1277 | ops; \ | |
1278 | 772:; \ | |
1279 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
1280 | .align algn; \ |
1281 | word 771b; \ | |
139ec7c4 RR |
1282 | .byte ptype; \ |
1283 | .byte 772b-771b; \ | |
1284 | .short clobbers; \ | |
1285 | .popsection | |
1286 | ||
658be9d3 GOC |
1287 | |
1288 | #ifdef CONFIG_X86_64 | |
6057fc82 GOC |
1289 | #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx |
1290 | #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax | |
1291 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) | |
658be9d3 GOC |
1292 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
1293 | #else | |
6057fc82 GOC |
1294 | #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx |
1295 | #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax | |
1296 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) | |
658be9d3 GOC |
1297 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
1298 | #endif | |
1299 | ||
93b1eab3 JF |
1300 | #define INTERRUPT_RETURN \ |
1301 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
1302 | jmp *%cs:pv_cpu_ops+PV_CPU_iret) | |
d5822035 JF |
1303 | |
1304 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1305 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
6057fc82 | 1306 | PV_SAVE_REGS; \ |
93b1eab3 | 1307 | call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \ |
6057fc82 | 1308 | PV_RESTORE_REGS;) \ |
d5822035 JF |
1309 | |
1310 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1311 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
6057fc82 | 1312 | PV_SAVE_REGS; \ |
93b1eab3 | 1313 | call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \ |
6057fc82 | 1314 | PV_RESTORE_REGS;) |
d5822035 | 1315 | |
6abcd98f GOC |
1316 | #define ENABLE_INTERRUPTS_SYSCALL_RET \ |
1317 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\ | |
1318 | CLBR_NONE, \ | |
1319 | jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret) | |
139ec7c4 | 1320 | |
2e47d3e6 | 1321 | |
6057fc82 | 1322 | #ifdef CONFIG_X86_32 |
139ec7c4 | 1323 | #define GET_CR0_INTO_EAX \ |
42c24fa2 | 1324 | push %ecx; push %edx; \ |
93b1eab3 | 1325 | call *pv_cpu_ops+PV_CPU_read_cr0; \ |
42c24fa2 | 1326 | pop %edx; pop %ecx |
4a8c4c4e | 1327 | #else |
e801f864 GOC |
1328 | #define SWAPGS \ |
1329 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
1330 | PV_SAVE_REGS; \ | |
1331 | call *pv_cpu_ops+PV_CPU_swapgs; \ | |
1332 | PV_RESTORE_REGS \ | |
1333 | ) | |
1334 | ||
4a8c4c4e GOC |
1335 | #define GET_CR2_INTO_RCX \ |
1336 | call *pv_mmu_ops+PV_MMU_read_cr2; \ | |
1337 | movq %rax, %rcx; \ | |
1338 | xorq %rax, %rax; | |
1339 | ||
6057fc82 | 1340 | #endif |
139ec7c4 | 1341 | |
d3561b7f RR |
1342 | #endif /* __ASSEMBLY__ */ |
1343 | #endif /* CONFIG_PARAVIRT */ | |
1344 | #endif /* __ASM_PARAVIRT_H */ |