Commit | Line | Data |
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d3561b7f RR |
1 | #ifndef __ASM_PARAVIRT_H |
2 | #define __ASM_PARAVIRT_H | |
3 | /* Various instructions on x86 need to be replaced for | |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
da181a8b | 7 | #include <asm/page.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
139ec7c4 | 10 | /* Bitmask of what can be clobbered: usually at least eax. */ |
21438f7c GOC |
11 | #define CLBR_NONE 0 |
12 | #define CLBR_EAX (1 << 0) | |
13 | #define CLBR_ECX (1 << 1) | |
14 | #define CLBR_EDX (1 << 2) | |
15 | ||
16 | #ifdef CONFIG_X86_64 | |
17 | #define CLBR_RSI (1 << 3) | |
18 | #define CLBR_RDI (1 << 4) | |
19 | #define CLBR_R8 (1 << 5) | |
20 | #define CLBR_R9 (1 << 6) | |
21 | #define CLBR_R10 (1 << 7) | |
22 | #define CLBR_R11 (1 << 8) | |
23 | #define CLBR_ANY ((1 << 9) - 1) | |
24 | #include <asm/desc_defs.h> | |
25 | #else | |
26 | /* CLBR_ANY should match all regs platform has. For i386, that's just it */ | |
27 | #define CLBR_ANY ((1 << 3) - 1) | |
28 | #endif /* X86_64 */ | |
139ec7c4 | 29 | |
d3561b7f | 30 | #ifndef __ASSEMBLY__ |
3dc494e8 | 31 | #include <linux/types.h> |
d4c10477 | 32 | #include <linux/cpumask.h> |
ce6234b5 | 33 | #include <asm/kmap_types.h> |
8d947344 | 34 | #include <asm/desc_defs.h> |
3dc494e8 | 35 | |
ce6234b5 | 36 | struct page; |
d3561b7f | 37 | struct thread_struct; |
6b68f01b | 38 | struct desc_ptr; |
d3561b7f | 39 | struct tss_struct; |
da181a8b | 40 | struct mm_struct; |
90a0a06a | 41 | struct desc_struct; |
294688c0 | 42 | |
93b1eab3 JF |
43 | /* general info */ |
44 | struct pv_info { | |
d3561b7f | 45 | unsigned int kernel_rpl; |
5311ab62 | 46 | int shared_kernel_pmd; |
93b1eab3 | 47 | int paravirt_enabled; |
d3561b7f | 48 | const char *name; |
93b1eab3 | 49 | }; |
d3561b7f | 50 | |
93b1eab3 | 51 | struct pv_init_ops { |
139ec7c4 | 52 | /* |
93b1eab3 JF |
53 | * Patch may replace one of the defined code sequences with |
54 | * arbitrary code, subject to the same register constraints. | |
55 | * This generally means the code is not free to clobber any | |
56 | * registers other than EAX. The patch function should return | |
57 | * the number of bytes of code generated, as we nop pad the | |
58 | * rest in generic code. | |
139ec7c4 | 59 | */ |
ab144f5e AK |
60 | unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, |
61 | unsigned long addr, unsigned len); | |
139ec7c4 | 62 | |
294688c0 | 63 | /* Basic arch-specific setup */ |
d3561b7f RR |
64 | void (*arch_setup)(void); |
65 | char *(*memory_setup)(void); | |
6996d3b6 JF |
66 | void (*post_allocator_init)(void); |
67 | ||
294688c0 | 68 | /* Print a banner to identify the environment */ |
d3561b7f | 69 | void (*banner)(void); |
93b1eab3 JF |
70 | }; |
71 | ||
72 | ||
8965c1c0 | 73 | struct pv_lazy_ops { |
93b1eab3 | 74 | /* Set deferred update mode, used for batching operations. */ |
8965c1c0 JF |
75 | void (*enter)(void); |
76 | void (*leave)(void); | |
93b1eab3 JF |
77 | }; |
78 | ||
79 | struct pv_time_ops { | |
80 | void (*time_init)(void); | |
d3561b7f | 81 | |
294688c0 | 82 | /* Set and set time of day */ |
d3561b7f RR |
83 | unsigned long (*get_wallclock)(void); |
84 | int (*set_wallclock)(unsigned long); | |
d3561b7f | 85 | |
93b1eab3 JF |
86 | unsigned long long (*sched_clock)(void); |
87 | unsigned long (*get_cpu_khz)(void); | |
88 | }; | |
d3561b7f | 89 | |
93b1eab3 | 90 | struct pv_cpu_ops { |
294688c0 | 91 | /* hooks for various privileged instructions */ |
1a1eecd1 AK |
92 | unsigned long (*get_debugreg)(int regno); |
93 | void (*set_debugreg)(int regno, unsigned long value); | |
d3561b7f | 94 | |
1a1eecd1 | 95 | void (*clts)(void); |
d3561b7f | 96 | |
1a1eecd1 AK |
97 | unsigned long (*read_cr0)(void); |
98 | void (*write_cr0)(unsigned long); | |
d3561b7f | 99 | |
1a1eecd1 AK |
100 | unsigned long (*read_cr4_safe)(void); |
101 | unsigned long (*read_cr4)(void); | |
102 | void (*write_cr4)(unsigned long); | |
d3561b7f | 103 | |
4c9890c2 GOC |
104 | #ifdef CONFIG_X86_64 |
105 | unsigned long (*read_cr8)(void); | |
106 | void (*write_cr8)(unsigned long); | |
107 | #endif | |
108 | ||
294688c0 | 109 | /* Segment descriptor handling */ |
1a1eecd1 | 110 | void (*load_tr_desc)(void); |
6b68f01b GOC |
111 | void (*load_gdt)(const struct desc_ptr *); |
112 | void (*load_idt)(const struct desc_ptr *); | |
113 | void (*store_gdt)(struct desc_ptr *); | |
114 | void (*store_idt)(struct desc_ptr *); | |
1a1eecd1 AK |
115 | void (*set_ldt)(const void *desc, unsigned entries); |
116 | unsigned long (*store_tr)(void); | |
117 | void (*load_tls)(struct thread_struct *t, unsigned int cpu); | |
75b8bb3e GOC |
118 | void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum, |
119 | const void *desc); | |
90a0a06a | 120 | void (*write_gdt_entry)(struct desc_struct *, |
014b15be | 121 | int entrynum, const void *desc, int size); |
8d947344 GOC |
122 | void (*write_idt_entry)(gate_desc *, |
123 | int entrynum, const gate_desc *gate); | |
faca6227 | 124 | void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t); |
d3561b7f | 125 | |
1a1eecd1 | 126 | void (*set_iopl_mask)(unsigned mask); |
93b1eab3 JF |
127 | |
128 | void (*wbinvd)(void); | |
1a1eecd1 | 129 | void (*io_delay)(void); |
d3561b7f | 130 | |
93b1eab3 JF |
131 | /* cpuid emulation, mostly so that caps bits can be disabled */ |
132 | void (*cpuid)(unsigned int *eax, unsigned int *ebx, | |
133 | unsigned int *ecx, unsigned int *edx); | |
134 | ||
135 | /* MSR, PMC and TSR operations. | |
136 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | |
137 | u64 (*read_msr)(unsigned int msr, int *err); | |
c9dcda5c | 138 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); |
93b1eab3 JF |
139 | |
140 | u64 (*read_tsc)(void); | |
b8d1fae7 | 141 | u64 (*read_pmc)(int counter); |
e5aaac44 | 142 | unsigned long long (*read_tscp)(unsigned int *aux); |
93b1eab3 JF |
143 | |
144 | /* These two are jmp to, not actually called. */ | |
6abcd98f | 145 | void (*irq_enable_syscall_ret)(void); |
93b1eab3 | 146 | void (*iret)(void); |
8965c1c0 | 147 | |
e801f864 GOC |
148 | void (*swapgs)(void); |
149 | ||
8965c1c0 | 150 | struct pv_lazy_ops lazy_mode; |
93b1eab3 JF |
151 | }; |
152 | ||
153 | struct pv_irq_ops { | |
154 | void (*init_IRQ)(void); | |
155 | ||
294688c0 | 156 | /* |
93b1eab3 JF |
157 | * Get/set interrupt state. save_fl and restore_fl are only |
158 | * expected to use X86_EFLAGS_IF; all other bits | |
159 | * returned from save_fl are undefined, and may be ignored by | |
160 | * restore_fl. | |
294688c0 | 161 | */ |
93b1eab3 JF |
162 | unsigned long (*save_fl)(void); |
163 | void (*restore_fl)(unsigned long); | |
164 | void (*irq_disable)(void); | |
165 | void (*irq_enable)(void); | |
166 | void (*safe_halt)(void); | |
167 | void (*halt)(void); | |
168 | }; | |
d6dd61c8 | 169 | |
93b1eab3 | 170 | struct pv_apic_ops { |
13623d79 | 171 | #ifdef CONFIG_X86_LOCAL_APIC |
294688c0 JF |
172 | /* |
173 | * Direct APIC operations, principally for VMI. Ideally | |
174 | * these shouldn't be in this interface. | |
175 | */ | |
42e0a9aa TG |
176 | void (*apic_write)(unsigned long reg, u32 v); |
177 | void (*apic_write_atomic)(unsigned long reg, u32 v); | |
178 | u32 (*apic_read)(unsigned long reg); | |
bbab4f3b ZA |
179 | void (*setup_boot_clock)(void); |
180 | void (*setup_secondary_clock)(void); | |
294688c0 JF |
181 | |
182 | void (*startup_ipi_hook)(int phys_apicid, | |
183 | unsigned long start_eip, | |
184 | unsigned long start_esp); | |
13623d79 | 185 | #endif |
93b1eab3 JF |
186 | }; |
187 | ||
188 | struct pv_mmu_ops { | |
189 | /* | |
190 | * Called before/after init_mm pagetable setup. setup_start | |
191 | * may reset %cr3, and may pre-install parts of the pagetable; | |
192 | * pagetable setup is expected to preserve any existing | |
193 | * mapping. | |
194 | */ | |
195 | void (*pagetable_setup_start)(pgd_t *pgd_base); | |
196 | void (*pagetable_setup_done)(pgd_t *pgd_base); | |
197 | ||
198 | unsigned long (*read_cr2)(void); | |
199 | void (*write_cr2)(unsigned long); | |
200 | ||
201 | unsigned long (*read_cr3)(void); | |
202 | void (*write_cr3)(unsigned long); | |
203 | ||
204 | /* | |
205 | * Hooks for intercepting the creation/use/destruction of an | |
206 | * mm_struct. | |
207 | */ | |
208 | void (*activate_mm)(struct mm_struct *prev, | |
209 | struct mm_struct *next); | |
210 | void (*dup_mmap)(struct mm_struct *oldmm, | |
211 | struct mm_struct *mm); | |
212 | void (*exit_mmap)(struct mm_struct *mm); | |
213 | ||
13623d79 | 214 | |
294688c0 | 215 | /* TLB operations */ |
1a1eecd1 AK |
216 | void (*flush_tlb_user)(void); |
217 | void (*flush_tlb_kernel)(void); | |
f8822f42 | 218 | void (*flush_tlb_single)(unsigned long addr); |
d4c10477 JF |
219 | void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, |
220 | unsigned long va); | |
1a1eecd1 | 221 | |
eba0045f JF |
222 | /* Hooks for allocating and freeing a pagetable top-level */ |
223 | int (*pgd_alloc)(struct mm_struct *mm); | |
224 | void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd); | |
225 | ||
226 | /* | |
227 | * Hooks for allocating/releasing pagetable pages when they're | |
228 | * attached to a pagetable | |
229 | */ | |
6944a9c8 JF |
230 | void (*alloc_pte)(struct mm_struct *mm, u32 pfn); |
231 | void (*alloc_pmd)(struct mm_struct *mm, u32 pfn); | |
232 | void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); | |
2761fa09 | 233 | void (*alloc_pud)(struct mm_struct *mm, u32 pfn); |
6944a9c8 JF |
234 | void (*release_pte)(u32 pfn); |
235 | void (*release_pmd)(u32 pfn); | |
2761fa09 | 236 | void (*release_pud)(u32 pfn); |
1a1eecd1 | 237 | |
294688c0 | 238 | /* Pagetable manipulation functions */ |
1a1eecd1 | 239 | void (*set_pte)(pte_t *ptep, pte_t pteval); |
294688c0 JF |
240 | void (*set_pte_at)(struct mm_struct *mm, unsigned long addr, |
241 | pte_t *ptep, pte_t pteval); | |
1a1eecd1 | 242 | void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval); |
49cd740b JP |
243 | void (*pte_update)(struct mm_struct *mm, unsigned long addr, |
244 | pte_t *ptep); | |
294688c0 JF |
245 | void (*pte_update_defer)(struct mm_struct *mm, |
246 | unsigned long addr, pte_t *ptep); | |
3dc494e8 | 247 | |
08b882c6 JF |
248 | pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr, |
249 | pte_t *ptep); | |
250 | void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr, | |
251 | pte_t *ptep, pte_t pte); | |
252 | ||
5b8dd1e9 | 253 | pteval_t (*pte_val)(pte_t); |
a15af1c9 | 254 | pteval_t (*pte_flags)(pte_t); |
5b8dd1e9 JF |
255 | pte_t (*make_pte)(pteval_t pte); |
256 | ||
257 | pgdval_t (*pgd_val)(pgd_t); | |
258 | pgd_t (*make_pgd)(pgdval_t pgd); | |
259 | ||
260 | #if PAGETABLE_LEVELS >= 3 | |
da181a8b | 261 | #ifdef CONFIG_X86_PAE |
1a1eecd1 | 262 | void (*set_pte_atomic)(pte_t *ptep, pte_t pteval); |
93b1eab3 JF |
263 | void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, |
264 | pte_t *ptep, pte_t pte); | |
49cd740b JP |
265 | void (*pte_clear)(struct mm_struct *mm, unsigned long addr, |
266 | pte_t *ptep); | |
1a1eecd1 | 267 | void (*pmd_clear)(pmd_t *pmdp); |
3dc494e8 | 268 | |
5b8dd1e9 | 269 | #endif /* CONFIG_X86_PAE */ |
3dc494e8 | 270 | |
5b8dd1e9 | 271 | void (*set_pud)(pud_t *pudp, pud_t pudval); |
3dc494e8 | 272 | |
5b8dd1e9 JF |
273 | pmdval_t (*pmd_val)(pmd_t); |
274 | pmd_t (*make_pmd)(pmdval_t pmd); | |
275 | ||
276 | #if PAGETABLE_LEVELS == 4 | |
277 | pudval_t (*pud_val)(pud_t); | |
278 | pud_t (*make_pud)(pudval_t pud); | |
9042219c EH |
279 | |
280 | void (*set_pgd)(pgd_t *pudp, pgd_t pgdval); | |
5b8dd1e9 JF |
281 | #endif /* PAGETABLE_LEVELS == 4 */ |
282 | #endif /* PAGETABLE_LEVELS >= 3 */ | |
da181a8b | 283 | |
93b1eab3 JF |
284 | #ifdef CONFIG_HIGHPTE |
285 | void *(*kmap_atomic_pte)(struct page *page, enum km_type type); | |
286 | #endif | |
8965c1c0 JF |
287 | |
288 | struct pv_lazy_ops lazy_mode; | |
aeaaa59c JF |
289 | |
290 | /* dom0 ops */ | |
291 | ||
292 | /* Sometimes the physical address is a pfn, and sometimes its | |
293 | an mfn. We can tell which is which from the index. */ | |
294 | void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx, | |
295 | unsigned long phys, pgprot_t flags); | |
93b1eab3 | 296 | }; |
9226d125 | 297 | |
93b1eab3 JF |
298 | /* This contains all the paravirt structures: we get a convenient |
299 | * number for each function using the offset which we use to indicate | |
300 | * what to patch. */ | |
49cd740b | 301 | struct paravirt_patch_template { |
93b1eab3 | 302 | struct pv_init_ops pv_init_ops; |
93b1eab3 JF |
303 | struct pv_time_ops pv_time_ops; |
304 | struct pv_cpu_ops pv_cpu_ops; | |
305 | struct pv_irq_ops pv_irq_ops; | |
306 | struct pv_apic_ops pv_apic_ops; | |
307 | struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f RR |
308 | }; |
309 | ||
93b1eab3 JF |
310 | extern struct pv_info pv_info; |
311 | extern struct pv_init_ops pv_init_ops; | |
93b1eab3 JF |
312 | extern struct pv_time_ops pv_time_ops; |
313 | extern struct pv_cpu_ops pv_cpu_ops; | |
314 | extern struct pv_irq_ops pv_irq_ops; | |
315 | extern struct pv_apic_ops pv_apic_ops; | |
316 | extern struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f | 317 | |
d5822035 | 318 | #define PARAVIRT_PATCH(x) \ |
93b1eab3 | 319 | (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) |
d5822035 | 320 | |
93b1eab3 JF |
321 | #define paravirt_type(op) \ |
322 | [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ | |
323 | [paravirt_opptr] "m" (op) | |
d5822035 JF |
324 | #define paravirt_clobber(clobber) \ |
325 | [paravirt_clobber] "i" (clobber) | |
326 | ||
294688c0 JF |
327 | /* |
328 | * Generate some code, and mark it as patchable by the | |
329 | * apply_paravirt() alternate instruction patcher. | |
330 | */ | |
d5822035 JF |
331 | #define _paravirt_alt(insn_string, type, clobber) \ |
332 | "771:\n\t" insn_string "\n" "772:\n" \ | |
333 | ".pushsection .parainstructions,\"a\"\n" \ | |
658be9d3 GOC |
334 | _ASM_ALIGN "\n" \ |
335 | _ASM_PTR " 771b\n" \ | |
d5822035 JF |
336 | " .byte " type "\n" \ |
337 | " .byte 772b-771b\n" \ | |
338 | " .short " clobber "\n" \ | |
339 | ".popsection\n" | |
340 | ||
294688c0 | 341 | /* Generate patchable code, with the default asm parameters. */ |
f8822f42 | 342 | #define paravirt_alt(insn_string) \ |
d5822035 JF |
343 | _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]") |
344 | ||
2f485ef5 GOC |
345 | /* Simple instruction patching code. */ |
346 | #define DEF_NATIVE(ops, name, code) \ | |
347 | extern const char start_##ops##_##name[], end_##ops##_##name[]; \ | |
348 | asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":") | |
349 | ||
63f70270 JF |
350 | unsigned paravirt_patch_nop(void); |
351 | unsigned paravirt_patch_ignore(unsigned len); | |
ab144f5e AK |
352 | unsigned paravirt_patch_call(void *insnbuf, |
353 | const void *target, u16 tgt_clobbers, | |
354 | unsigned long addr, u16 site_clobbers, | |
63f70270 | 355 | unsigned len); |
93b1eab3 | 356 | unsigned paravirt_patch_jmp(void *insnbuf, const void *target, |
ab144f5e AK |
357 | unsigned long addr, unsigned len); |
358 | unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, | |
359 | unsigned long addr, unsigned len); | |
63f70270 | 360 | |
ab144f5e | 361 | unsigned paravirt_patch_insns(void *insnbuf, unsigned len, |
63f70270 JF |
362 | const char *start, const char *end); |
363 | ||
2f485ef5 GOC |
364 | unsigned native_patch(u8 type, u16 clobbers, void *ibuf, |
365 | unsigned long addr, unsigned len); | |
366 | ||
d572929c | 367 | int paravirt_disable_iospace(void); |
63f70270 | 368 | |
294688c0 JF |
369 | /* |
370 | * This generates an indirect call based on the operation type number. | |
371 | * The type number, computed in PARAVIRT_PATCH, is derived from the | |
93b1eab3 JF |
372 | * offset into the paravirt_patch_template structure, and can therefore be |
373 | * freely converted back into a structure offset. | |
294688c0 | 374 | */ |
93b1eab3 | 375 | #define PARAVIRT_CALL "call *%[paravirt_opptr];" |
294688c0 JF |
376 | |
377 | /* | |
93b1eab3 JF |
378 | * These macros are intended to wrap calls through one of the paravirt |
379 | * ops structs, so that they can be later identified and patched at | |
294688c0 JF |
380 | * runtime. |
381 | * | |
382 | * Normally, a call to a pv_op function is a simple indirect call: | |
a4746364 | 383 | * (pv_op_struct.operations)(args...). |
294688c0 JF |
384 | * |
385 | * Unfortunately, this is a relatively slow operation for modern CPUs, | |
386 | * because it cannot necessarily determine what the destination | |
387 | * address is. In this case, the address is a runtime constant, so at | |
388 | * the very least we can patch the call to e a simple direct call, or | |
389 | * ideally, patch an inline implementation into the callsite. (Direct | |
390 | * calls are essentially free, because the call and return addresses | |
391 | * are completely predictable.) | |
392 | * | |
a4746364 | 393 | * For i386, these macros rely on the standard gcc "regparm(3)" calling |
294688c0 JF |
394 | * convention, in which the first three arguments are placed in %eax, |
395 | * %edx, %ecx (in that order), and the remaining arguments are placed | |
396 | * on the stack. All caller-save registers (eax,edx,ecx) are expected | |
397 | * to be modified (either clobbered or used for return values). | |
a4746364 GOC |
398 | * X86_64, on the other hand, already specifies a register-based calling |
399 | * conventions, returning at %rax, with parameteres going on %rdi, %rsi, | |
400 | * %rdx, and %rcx. Note that for this reason, x86_64 does not need any | |
401 | * special handling for dealing with 4 arguments, unlike i386. | |
402 | * However, x86_64 also have to clobber all caller saved registers, which | |
403 | * unfortunately, are quite a bit (r8 - r11) | |
294688c0 JF |
404 | * |
405 | * The call instruction itself is marked by placing its start address | |
406 | * and size into the .parainstructions section, so that | |
407 | * apply_paravirt() in arch/i386/kernel/alternative.c can do the | |
93b1eab3 | 408 | * appropriate patching under the control of the backend pv_init_ops |
294688c0 JF |
409 | * implementation. |
410 | * | |
411 | * Unfortunately there's no way to get gcc to generate the args setup | |
412 | * for the call, and then allow the call itself to be generated by an | |
413 | * inline asm. Because of this, we must do the complete arg setup and | |
414 | * return value handling from within these macros. This is fairly | |
415 | * cumbersome. | |
416 | * | |
417 | * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments. | |
418 | * It could be extended to more arguments, but there would be little | |
419 | * to be gained from that. For each number of arguments, there are | |
420 | * the two VCALL and CALL variants for void and non-void functions. | |
421 | * | |
422 | * When there is a return value, the invoker of the macro must specify | |
423 | * the return type. The macro then uses sizeof() on that type to | |
424 | * determine whether its a 32 or 64 bit value, and places the return | |
425 | * in the right register(s) (just %eax for 32-bit, and %edx:%eax for | |
a4746364 GOC |
426 | * 64-bit). For x86_64 machines, it just returns at %rax regardless of |
427 | * the return value size. | |
294688c0 JF |
428 | * |
429 | * 64-bit arguments are passed as a pair of adjacent 32-bit arguments | |
a4746364 GOC |
430 | * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments |
431 | * in low,high order | |
294688c0 JF |
432 | * |
433 | * Small structures are passed and returned in registers. The macro | |
434 | * calling convention can't directly deal with this, so the wrapper | |
435 | * functions must do this. | |
436 | * | |
437 | * These PVOP_* macros are only defined within this header. This | |
438 | * means that all uses must be wrapped in inline functions. This also | |
439 | * makes sure the incoming and outgoing types are always correct. | |
440 | */ | |
a4746364 GOC |
441 | #ifdef CONFIG_X86_32 |
442 | #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx | |
443 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS | |
444 | #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \ | |
445 | "=c" (__ecx) | |
446 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS | |
447 | #define EXTRA_CLOBBERS | |
448 | #define VEXTRA_CLOBBERS | |
449 | #else | |
450 | #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx | |
451 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax | |
452 | #define PVOP_VCALL_CLOBBERS "=D" (__edi), \ | |
453 | "=S" (__esi), "=d" (__edx), \ | |
454 | "=c" (__ecx) | |
455 | ||
456 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax) | |
457 | ||
458 | #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11" | |
459 | #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11" | |
460 | #endif | |
461 | ||
97349135 JF |
462 | #ifdef CONFIG_PARAVIRT_DEBUG |
463 | #define PVOP_TEST_NULL(op) BUG_ON(op == NULL) | |
464 | #else | |
465 | #define PVOP_TEST_NULL(op) ((void)op) | |
466 | #endif | |
467 | ||
1a45b7aa | 468 | #define __PVOP_CALL(rettype, op, pre, post, ...) \ |
f8822f42 | 469 | ({ \ |
1a45b7aa | 470 | rettype __ret; \ |
a4746364 | 471 | PVOP_CALL_ARGS; \ |
97349135 | 472 | PVOP_TEST_NULL(op); \ |
a4746364 GOC |
473 | /* This is 32-bit specific, but is okay in 64-bit */ \ |
474 | /* since this condition will never hold */ \ | |
1a45b7aa JF |
475 | if (sizeof(rettype) > sizeof(unsigned long)) { \ |
476 | asm volatile(pre \ | |
477 | paravirt_alt(PARAVIRT_CALL) \ | |
478 | post \ | |
a4746364 | 479 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
480 | : paravirt_type(op), \ |
481 | paravirt_clobber(CLBR_ANY), \ | |
482 | ##__VA_ARGS__ \ | |
a4746364 | 483 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 484 | __ret = (rettype)((((u64)__edx) << 32) | __eax); \ |
f8822f42 | 485 | } else { \ |
1a45b7aa | 486 | asm volatile(pre \ |
f8822f42 | 487 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 488 | post \ |
a4746364 | 489 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
490 | : paravirt_type(op), \ |
491 | paravirt_clobber(CLBR_ANY), \ | |
492 | ##__VA_ARGS__ \ | |
a4746364 | 493 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 494 | __ret = (rettype)__eax; \ |
f8822f42 JF |
495 | } \ |
496 | __ret; \ | |
497 | }) | |
1a45b7aa | 498 | #define __PVOP_VCALL(op, pre, post, ...) \ |
f8822f42 | 499 | ({ \ |
a4746364 | 500 | PVOP_VCALL_ARGS; \ |
97349135 | 501 | PVOP_TEST_NULL(op); \ |
1a45b7aa | 502 | asm volatile(pre \ |
f8822f42 | 503 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 504 | post \ |
a4746364 | 505 | : PVOP_VCALL_CLOBBERS \ |
1a45b7aa JF |
506 | : paravirt_type(op), \ |
507 | paravirt_clobber(CLBR_ANY), \ | |
508 | ##__VA_ARGS__ \ | |
a4746364 | 509 | : "memory", "cc" VEXTRA_CLOBBERS); \ |
f8822f42 JF |
510 | }) |
511 | ||
1a45b7aa JF |
512 | #define PVOP_CALL0(rettype, op) \ |
513 | __PVOP_CALL(rettype, op, "", "") | |
514 | #define PVOP_VCALL0(op) \ | |
515 | __PVOP_VCALL(op, "", "") | |
516 | ||
517 | #define PVOP_CALL1(rettype, op, arg1) \ | |
a4746364 | 518 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa | 519 | #define PVOP_VCALL1(op, arg1) \ |
a4746364 | 520 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa JF |
521 | |
522 | #define PVOP_CALL2(rettype, op, arg1, arg2) \ | |
a4746364 GOC |
523 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
524 | "1" ((unsigned long)(arg2))) | |
1a45b7aa | 525 | #define PVOP_VCALL2(op, arg1, arg2) \ |
a4746364 GOC |
526 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
527 | "1" ((unsigned long)(arg2))) | |
1a45b7aa JF |
528 | |
529 | #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \ | |
a4746364 GOC |
530 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
531 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 532 | #define PVOP_VCALL3(op, arg1, arg2, arg3) \ |
a4746364 GOC |
533 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
534 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 535 | |
a4746364 GOC |
536 | /* This is the only difference in x86_64. We can make it much simpler */ |
537 | #ifdef CONFIG_X86_32 | |
1a45b7aa JF |
538 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ |
539 | __PVOP_CALL(rettype, op, \ | |
540 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
541 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
542 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
543 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
544 | __PVOP_VCALL(op, \ | |
545 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
546 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
547 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
a4746364 GOC |
548 | #else |
549 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ | |
550 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ | |
551 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
552 | "3"((unsigned long)(arg4))) | |
553 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
554 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ | |
555 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
556 | "3"((unsigned long)(arg4))) | |
557 | #endif | |
1a45b7aa | 558 | |
f8822f42 JF |
559 | static inline int paravirt_enabled(void) |
560 | { | |
93b1eab3 | 561 | return pv_info.paravirt_enabled; |
f8822f42 | 562 | } |
d3561b7f | 563 | |
faca6227 | 564 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
565 | struct thread_struct *thread) |
566 | { | |
faca6227 | 567 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
568 | } |
569 | ||
93b1eab3 | 570 | #define ARCH_SETUP pv_init_ops.arch_setup(); |
d3561b7f RR |
571 | static inline unsigned long get_wallclock(void) |
572 | { | |
93b1eab3 | 573 | return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); |
d3561b7f RR |
574 | } |
575 | ||
576 | static inline int set_wallclock(unsigned long nowtime) | |
577 | { | |
93b1eab3 | 578 | return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); |
d3561b7f RR |
579 | } |
580 | ||
e30fab3a | 581 | static inline void (*choose_time_init(void))(void) |
d3561b7f | 582 | { |
93b1eab3 | 583 | return pv_time_ops.time_init; |
d3561b7f RR |
584 | } |
585 | ||
586 | /* The paravirtualized CPUID instruction. */ | |
587 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
588 | unsigned int *ecx, unsigned int *edx) | |
589 | { | |
93b1eab3 | 590 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
591 | } |
592 | ||
593 | /* | |
594 | * These special macros can be used to get or set a debugging register | |
595 | */ | |
f8822f42 JF |
596 | static inline unsigned long paravirt_get_debugreg(int reg) |
597 | { | |
93b1eab3 | 598 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
599 | } |
600 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
601 | static inline void set_debugreg(unsigned long val, int reg) | |
602 | { | |
93b1eab3 | 603 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 604 | } |
d3561b7f | 605 | |
f8822f42 JF |
606 | static inline void clts(void) |
607 | { | |
93b1eab3 | 608 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 609 | } |
d3561b7f | 610 | |
f8822f42 JF |
611 | static inline unsigned long read_cr0(void) |
612 | { | |
93b1eab3 | 613 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 614 | } |
d3561b7f | 615 | |
f8822f42 JF |
616 | static inline void write_cr0(unsigned long x) |
617 | { | |
93b1eab3 | 618 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
619 | } |
620 | ||
621 | static inline unsigned long read_cr2(void) | |
622 | { | |
93b1eab3 | 623 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
624 | } |
625 | ||
626 | static inline void write_cr2(unsigned long x) | |
627 | { | |
93b1eab3 | 628 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
629 | } |
630 | ||
631 | static inline unsigned long read_cr3(void) | |
632 | { | |
93b1eab3 | 633 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 634 | } |
d3561b7f | 635 | |
f8822f42 JF |
636 | static inline void write_cr3(unsigned long x) |
637 | { | |
93b1eab3 | 638 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 639 | } |
d3561b7f | 640 | |
f8822f42 JF |
641 | static inline unsigned long read_cr4(void) |
642 | { | |
93b1eab3 | 643 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
644 | } |
645 | static inline unsigned long read_cr4_safe(void) | |
646 | { | |
93b1eab3 | 647 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 648 | } |
d3561b7f | 649 | |
f8822f42 JF |
650 | static inline void write_cr4(unsigned long x) |
651 | { | |
93b1eab3 | 652 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 653 | } |
3dc494e8 | 654 | |
94ea03cd | 655 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
656 | static inline unsigned long read_cr8(void) |
657 | { | |
658 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
659 | } | |
660 | ||
661 | static inline void write_cr8(unsigned long x) | |
662 | { | |
663 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
664 | } | |
94ea03cd | 665 | #endif |
4c9890c2 | 666 | |
d3561b7f RR |
667 | static inline void raw_safe_halt(void) |
668 | { | |
93b1eab3 | 669 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
670 | } |
671 | ||
672 | static inline void halt(void) | |
673 | { | |
93b1eab3 | 674 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
f8822f42 JF |
675 | } |
676 | ||
677 | static inline void wbinvd(void) | |
678 | { | |
93b1eab3 | 679 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 680 | } |
d3561b7f | 681 | |
93b1eab3 | 682 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 683 | |
f8822f42 JF |
684 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
685 | { | |
93b1eab3 | 686 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 JF |
687 | } |
688 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | |
689 | { | |
93b1eab3 | 690 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
691 | } |
692 | ||
90a0a06a | 693 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
49cd740b JP |
694 | #define rdmsr(msr, val1, val2) \ |
695 | do { \ | |
f8822f42 JF |
696 | int _err; \ |
697 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
698 | val1 = (u32)_l; \ | |
699 | val2 = _l >> 32; \ | |
49cd740b | 700 | } while (0) |
d3561b7f | 701 | |
49cd740b JP |
702 | #define wrmsr(msr, val1, val2) \ |
703 | do { \ | |
f8822f42 | 704 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 705 | } while (0) |
d3561b7f | 706 | |
49cd740b JP |
707 | #define rdmsrl(msr, val) \ |
708 | do { \ | |
f8822f42 JF |
709 | int _err; \ |
710 | val = paravirt_read_msr(msr, &_err); \ | |
49cd740b | 711 | } while (0) |
d3561b7f | 712 | |
49cd740b JP |
713 | #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
714 | #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) | |
d3561b7f RR |
715 | |
716 | /* rdmsr with exception handling */ | |
49cd740b JP |
717 | #define rdmsr_safe(msr, a, b) \ |
718 | ({ \ | |
f8822f42 JF |
719 | int _err; \ |
720 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
721 | (*a) = (u32)_l; \ | |
722 | (*b) = _l >> 32; \ | |
49cd740b JP |
723 | _err; \ |
724 | }) | |
d3561b7f | 725 | |
1de87bd4 AK |
726 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
727 | { | |
728 | int err; | |
729 | ||
730 | *p = paravirt_read_msr(msr, &err); | |
731 | return err; | |
732 | } | |
f8822f42 JF |
733 | |
734 | static inline u64 paravirt_read_tsc(void) | |
735 | { | |
93b1eab3 | 736 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 737 | } |
d3561b7f | 738 | |
49cd740b JP |
739 | #define rdtscl(low) \ |
740 | do { \ | |
f8822f42 JF |
741 | u64 _l = paravirt_read_tsc(); \ |
742 | low = (int)_l; \ | |
49cd740b | 743 | } while (0) |
d3561b7f | 744 | |
f8822f42 | 745 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 746 | |
688340ea JF |
747 | static inline unsigned long long paravirt_sched_clock(void) |
748 | { | |
93b1eab3 | 749 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 750 | } |
93b1eab3 | 751 | #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) |
6cb9a835 | 752 | |
f8822f42 JF |
753 | static inline unsigned long long paravirt_read_pmc(int counter) |
754 | { | |
93b1eab3 | 755 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 756 | } |
d3561b7f | 757 | |
49cd740b JP |
758 | #define rdpmc(counter, low, high) \ |
759 | do { \ | |
f8822f42 JF |
760 | u64 _l = paravirt_read_pmc(counter); \ |
761 | low = (u32)_l; \ | |
762 | high = _l >> 32; \ | |
49cd740b | 763 | } while (0) |
3dc494e8 | 764 | |
e5aaac44 GOC |
765 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
766 | { | |
767 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | |
768 | } | |
769 | ||
770 | #define rdtscp(low, high, aux) \ | |
771 | do { \ | |
772 | int __aux; \ | |
773 | unsigned long __val = paravirt_rdtscp(&__aux); \ | |
774 | (low) = (u32)__val; \ | |
775 | (high) = (u32)(__val >> 32); \ | |
776 | (aux) = __aux; \ | |
777 | } while (0) | |
778 | ||
779 | #define rdtscpll(val, aux) \ | |
780 | do { \ | |
781 | unsigned long __aux; \ | |
782 | val = paravirt_rdtscp(&__aux); \ | |
783 | (aux) = __aux; \ | |
784 | } while (0) | |
785 | ||
f8822f42 JF |
786 | static inline void load_TR_desc(void) |
787 | { | |
93b1eab3 | 788 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 789 | } |
6b68f01b | 790 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 791 | { |
93b1eab3 | 792 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 793 | } |
6b68f01b | 794 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 795 | { |
93b1eab3 | 796 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
797 | } |
798 | static inline void set_ldt(const void *addr, unsigned entries) | |
799 | { | |
93b1eab3 | 800 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 801 | } |
6b68f01b | 802 | static inline void store_gdt(struct desc_ptr *dtr) |
f8822f42 | 803 | { |
93b1eab3 | 804 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 | 805 | } |
6b68f01b | 806 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 807 | { |
93b1eab3 | 808 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
809 | } |
810 | static inline unsigned long paravirt_store_tr(void) | |
811 | { | |
93b1eab3 | 812 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
813 | } |
814 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
815 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
816 | { | |
93b1eab3 | 817 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 818 | } |
75b8bb3e GOC |
819 | |
820 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, | |
821 | const void *desc) | |
f8822f42 | 822 | { |
75b8bb3e | 823 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 824 | } |
014b15be GOC |
825 | |
826 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
827 | void *desc, int type) | |
f8822f42 | 828 | { |
014b15be | 829 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 830 | } |
014b15be | 831 | |
8d947344 | 832 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 833 | { |
8d947344 | 834 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
835 | } |
836 | static inline void set_iopl_mask(unsigned mask) | |
837 | { | |
93b1eab3 | 838 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 839 | } |
3dc494e8 | 840 | |
d3561b7f | 841 | /* The paravirtualized I/O functions */ |
49cd740b JP |
842 | static inline void slow_down_io(void) |
843 | { | |
93b1eab3 | 844 | pv_cpu_ops.io_delay(); |
d3561b7f | 845 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
846 | pv_cpu_ops.io_delay(); |
847 | pv_cpu_ops.io_delay(); | |
848 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
849 | #endif |
850 | } | |
851 | ||
13623d79 RR |
852 | #ifdef CONFIG_X86_LOCAL_APIC |
853 | /* | |
854 | * Basic functions accessing APICs. | |
855 | */ | |
42e0a9aa | 856 | static inline void apic_write(unsigned long reg, u32 v) |
13623d79 | 857 | { |
93b1eab3 | 858 | PVOP_VCALL2(pv_apic_ops.apic_write, reg, v); |
13623d79 RR |
859 | } |
860 | ||
42e0a9aa | 861 | static inline void apic_write_atomic(unsigned long reg, u32 v) |
13623d79 | 862 | { |
93b1eab3 | 863 | PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v); |
13623d79 RR |
864 | } |
865 | ||
42e0a9aa | 866 | static inline u32 apic_read(unsigned long reg) |
13623d79 | 867 | { |
93b1eab3 | 868 | return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg); |
13623d79 | 869 | } |
bbab4f3b ZA |
870 | |
871 | static inline void setup_boot_clock(void) | |
872 | { | |
93b1eab3 | 873 | PVOP_VCALL0(pv_apic_ops.setup_boot_clock); |
bbab4f3b ZA |
874 | } |
875 | ||
876 | static inline void setup_secondary_clock(void) | |
877 | { | |
93b1eab3 | 878 | PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); |
bbab4f3b | 879 | } |
13623d79 RR |
880 | #endif |
881 | ||
6996d3b6 JF |
882 | static inline void paravirt_post_allocator_init(void) |
883 | { | |
93b1eab3 JF |
884 | if (pv_init_ops.post_allocator_init) |
885 | (*pv_init_ops.post_allocator_init)(); | |
6996d3b6 JF |
886 | } |
887 | ||
b239fb25 JF |
888 | static inline void paravirt_pagetable_setup_start(pgd_t *base) |
889 | { | |
93b1eab3 | 890 | (*pv_mmu_ops.pagetable_setup_start)(base); |
b239fb25 JF |
891 | } |
892 | ||
893 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
894 | { | |
93b1eab3 | 895 | (*pv_mmu_ops.pagetable_setup_done)(base); |
b239fb25 | 896 | } |
3dc494e8 | 897 | |
ae5da273 ZA |
898 | #ifdef CONFIG_SMP |
899 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
900 | unsigned long start_esp) | |
901 | { | |
93b1eab3 JF |
902 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
903 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
904 | } |
905 | #endif | |
13623d79 | 906 | |
d6dd61c8 JF |
907 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
908 | struct mm_struct *next) | |
909 | { | |
93b1eab3 | 910 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
911 | } |
912 | ||
913 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
914 | struct mm_struct *mm) | |
915 | { | |
93b1eab3 | 916 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
917 | } |
918 | ||
919 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
920 | { | |
93b1eab3 | 921 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
922 | } |
923 | ||
f8822f42 JF |
924 | static inline void __flush_tlb(void) |
925 | { | |
93b1eab3 | 926 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
927 | } |
928 | static inline void __flush_tlb_global(void) | |
929 | { | |
93b1eab3 | 930 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
931 | } |
932 | static inline void __flush_tlb_single(unsigned long addr) | |
933 | { | |
93b1eab3 | 934 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 935 | } |
da181a8b | 936 | |
d4c10477 JF |
937 | static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, |
938 | unsigned long va) | |
939 | { | |
93b1eab3 | 940 | PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); |
d4c10477 JF |
941 | } |
942 | ||
eba0045f JF |
943 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
944 | { | |
945 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
946 | } | |
947 | ||
948 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
949 | { | |
950 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
951 | } | |
952 | ||
6944a9c8 | 953 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 954 | { |
6944a9c8 | 955 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 956 | } |
6944a9c8 | 957 | static inline void paravirt_release_pte(unsigned pfn) |
f8822f42 | 958 | { |
6944a9c8 | 959 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 960 | } |
c119ecce | 961 | |
6944a9c8 | 962 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 963 | { |
6944a9c8 | 964 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 965 | } |
c119ecce | 966 | |
6944a9c8 JF |
967 | static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn, |
968 | unsigned start, unsigned count) | |
f8822f42 | 969 | { |
6944a9c8 | 970 | PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count); |
f8822f42 | 971 | } |
6944a9c8 | 972 | static inline void paravirt_release_pmd(unsigned pfn) |
da181a8b | 973 | { |
6944a9c8 | 974 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
975 | } |
976 | ||
2761fa09 JF |
977 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn) |
978 | { | |
979 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
980 | } | |
981 | static inline void paravirt_release_pud(unsigned pfn) | |
982 | { | |
983 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
984 | } | |
985 | ||
ce6234b5 JF |
986 | #ifdef CONFIG_HIGHPTE |
987 | static inline void *kmap_atomic_pte(struct page *page, enum km_type type) | |
988 | { | |
989 | unsigned long ret; | |
93b1eab3 | 990 | ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type); |
ce6234b5 JF |
991 | return (void *)ret; |
992 | } | |
993 | #endif | |
994 | ||
f8822f42 JF |
995 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
996 | pte_t *ptep) | |
da181a8b | 997 | { |
93b1eab3 | 998 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b RR |
999 | } |
1000 | ||
f8822f42 JF |
1001 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
1002 | pte_t *ptep) | |
da181a8b | 1003 | { |
93b1eab3 | 1004 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
1005 | } |
1006 | ||
773221f4 | 1007 | static inline pte_t __pte(pteval_t val) |
da181a8b | 1008 | { |
773221f4 JF |
1009 | pteval_t ret; |
1010 | ||
1011 | if (sizeof(pteval_t) > sizeof(long)) | |
1012 | ret = PVOP_CALL2(pteval_t, | |
1013 | pv_mmu_ops.make_pte, | |
1014 | val, (u64)val >> 32); | |
1015 | else | |
1016 | ret = PVOP_CALL1(pteval_t, | |
1017 | pv_mmu_ops.make_pte, | |
1018 | val); | |
1019 | ||
c8e5393a | 1020 | return (pte_t) { .pte = ret }; |
da181a8b RR |
1021 | } |
1022 | ||
773221f4 JF |
1023 | static inline pteval_t pte_val(pte_t pte) |
1024 | { | |
1025 | pteval_t ret; | |
1026 | ||
1027 | if (sizeof(pteval_t) > sizeof(long)) | |
1028 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val, | |
1029 | pte.pte, (u64)pte.pte >> 32); | |
1030 | else | |
1031 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val, | |
1032 | pte.pte); | |
1033 | ||
1034 | return ret; | |
1035 | } | |
1036 | ||
a15af1c9 JF |
1037 | static inline pteval_t pte_flags(pte_t pte) |
1038 | { | |
1039 | pteval_t ret; | |
1040 | ||
1041 | if (sizeof(pteval_t) > sizeof(long)) | |
1042 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags, | |
1043 | pte.pte, (u64)pte.pte >> 32); | |
1044 | else | |
1045 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags, | |
1046 | pte.pte); | |
1047 | ||
1048 | return ret; | |
1049 | } | |
1050 | ||
ef38503e | 1051 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 1052 | { |
ef38503e JF |
1053 | pgdval_t ret; |
1054 | ||
1055 | if (sizeof(pgdval_t) > sizeof(long)) | |
1056 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd, | |
1057 | val, (u64)val >> 32); | |
1058 | else | |
1059 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd, | |
1060 | val); | |
1061 | ||
1062 | return (pgd_t) { ret }; | |
1063 | } | |
1064 | ||
1065 | static inline pgdval_t pgd_val(pgd_t pgd) | |
1066 | { | |
1067 | pgdval_t ret; | |
1068 | ||
1069 | if (sizeof(pgdval_t) > sizeof(long)) | |
1070 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val, | |
1071 | pgd.pgd, (u64)pgd.pgd >> 32); | |
1072 | else | |
1073 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val, | |
1074 | pgd.pgd); | |
1075 | ||
1076 | return ret; | |
f8822f42 JF |
1077 | } |
1078 | ||
08b882c6 JF |
1079 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1080 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
1081 | pte_t *ptep) | |
1082 | { | |
1083 | pteval_t ret; | |
1084 | ||
1085 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
1086 | mm, addr, ptep); | |
1087 | ||
1088 | return (pte_t) { .pte = ret }; | |
1089 | } | |
1090 | ||
1091 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
1092 | pte_t *ptep, pte_t pte) | |
1093 | { | |
1094 | if (sizeof(pteval_t) > sizeof(long)) | |
1095 | /* 5 arg words */ | |
1096 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
1097 | else | |
1098 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
1099 | mm, addr, ptep, pte.pte); | |
1100 | } | |
1101 | ||
4eed80cd JF |
1102 | static inline void set_pte(pte_t *ptep, pte_t pte) |
1103 | { | |
1104 | if (sizeof(pteval_t) > sizeof(long)) | |
1105 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
1106 | pte.pte, (u64)pte.pte >> 32); | |
1107 | else | |
1108 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
1109 | pte.pte); | |
1110 | } | |
1111 | ||
1112 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1113 | pte_t *ptep, pte_t pte) | |
1114 | { | |
1115 | if (sizeof(pteval_t) > sizeof(long)) | |
1116 | /* 5 arg words */ | |
1117 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
1118 | else | |
1119 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
1120 | } | |
1121 | ||
60b3f626 JF |
1122 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
1123 | { | |
1124 | pmdval_t val = native_pmd_val(pmd); | |
1125 | ||
1126 | if (sizeof(pmdval_t) > sizeof(long)) | |
1127 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
1128 | else | |
1129 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
1130 | } | |
1131 | ||
1fe91514 GOC |
1132 | #if PAGETABLE_LEVELS >= 3 |
1133 | static inline pmd_t __pmd(pmdval_t val) | |
1134 | { | |
1135 | pmdval_t ret; | |
1136 | ||
1137 | if (sizeof(pmdval_t) > sizeof(long)) | |
1138 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd, | |
1139 | val, (u64)val >> 32); | |
1140 | else | |
1141 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd, | |
1142 | val); | |
1143 | ||
1144 | return (pmd_t) { ret }; | |
1145 | } | |
1146 | ||
1147 | static inline pmdval_t pmd_val(pmd_t pmd) | |
1148 | { | |
1149 | pmdval_t ret; | |
1150 | ||
1151 | if (sizeof(pmdval_t) > sizeof(long)) | |
1152 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val, | |
1153 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1154 | else | |
1155 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val, | |
1156 | pmd.pmd); | |
1157 | ||
1158 | return ret; | |
1159 | } | |
1160 | ||
1161 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
1162 | { | |
1163 | pudval_t val = native_pud_val(pud); | |
1164 | ||
1165 | if (sizeof(pudval_t) > sizeof(long)) | |
1166 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
1167 | val, (u64)val >> 32); | |
1168 | else | |
1169 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
1170 | val); | |
1171 | } | |
9042219c EH |
1172 | #if PAGETABLE_LEVELS == 4 |
1173 | static inline pud_t __pud(pudval_t val) | |
1174 | { | |
1175 | pudval_t ret; | |
1176 | ||
1177 | if (sizeof(pudval_t) > sizeof(long)) | |
1178 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud, | |
1179 | val, (u64)val >> 32); | |
1180 | else | |
1181 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud, | |
1182 | val); | |
1183 | ||
1184 | return (pud_t) { ret }; | |
1185 | } | |
1186 | ||
1187 | static inline pudval_t pud_val(pud_t pud) | |
1188 | { | |
1189 | pudval_t ret; | |
1190 | ||
1191 | if (sizeof(pudval_t) > sizeof(long)) | |
1192 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val, | |
1193 | pud.pud, (u64)pud.pud >> 32); | |
1194 | else | |
1195 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val, | |
1196 | pud.pud); | |
1197 | ||
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
1202 | { | |
1203 | pgdval_t val = native_pgd_val(pgd); | |
1204 | ||
1205 | if (sizeof(pgdval_t) > sizeof(long)) | |
1206 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
1207 | val, (u64)val >> 32); | |
1208 | else | |
1209 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
1210 | val); | |
1211 | } | |
1212 | ||
1213 | static inline void pgd_clear(pgd_t *pgdp) | |
1214 | { | |
1215 | set_pgd(pgdp, __pgd(0)); | |
1216 | } | |
1217 | ||
1218 | static inline void pud_clear(pud_t *pudp) | |
1219 | { | |
1220 | set_pud(pudp, __pud(0)); | |
1221 | } | |
1222 | ||
1223 | #endif /* PAGETABLE_LEVELS == 4 */ | |
1224 | ||
1fe91514 GOC |
1225 | #endif /* PAGETABLE_LEVELS >= 3 */ |
1226 | ||
4eed80cd JF |
1227 | #ifdef CONFIG_X86_PAE |
1228 | /* Special-case pte-setting operations for PAE, which can't update a | |
1229 | 64-bit pte atomically */ | |
1230 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1231 | { | |
1232 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
1233 | pte.pte, pte.pte >> 32); | |
1234 | } | |
1235 | ||
1236 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1237 | pte_t *ptep, pte_t pte) | |
1238 | { | |
1239 | /* 5 arg words */ | |
1240 | pv_mmu_ops.set_pte_present(mm, addr, ptep, pte); | |
1241 | } | |
1242 | ||
1243 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1244 | pte_t *ptep) | |
1245 | { | |
1246 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
1247 | } | |
60b3f626 JF |
1248 | |
1249 | static inline void pmd_clear(pmd_t *pmdp) | |
1250 | { | |
1251 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
1252 | } | |
4eed80cd JF |
1253 | #else /* !CONFIG_X86_PAE */ |
1254 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1255 | { | |
1256 | set_pte(ptep, pte); | |
1257 | } | |
1258 | ||
1259 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1260 | pte_t *ptep, pte_t pte) | |
1261 | { | |
1262 | set_pte(ptep, pte); | |
1263 | } | |
1264 | ||
1265 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1266 | pte_t *ptep) | |
1267 | { | |
1268 | set_pte_at(mm, addr, ptep, __pte(0)); | |
1269 | } | |
60b3f626 JF |
1270 | |
1271 | static inline void pmd_clear(pmd_t *pmdp) | |
1272 | { | |
1273 | set_pmd(pmdp, __pmd(0)); | |
1274 | } | |
4eed80cd JF |
1275 | #endif /* CONFIG_X86_PAE */ |
1276 | ||
8965c1c0 JF |
1277 | /* Lazy mode for batching updates / context switch */ |
1278 | enum paravirt_lazy_mode { | |
1279 | PARAVIRT_LAZY_NONE, | |
1280 | PARAVIRT_LAZY_MMU, | |
1281 | PARAVIRT_LAZY_CPU, | |
1282 | }; | |
1283 | ||
1284 | enum paravirt_lazy_mode paravirt_get_lazy_mode(void); | |
1285 | void paravirt_enter_lazy_cpu(void); | |
1286 | void paravirt_leave_lazy_cpu(void); | |
1287 | void paravirt_enter_lazy_mmu(void); | |
1288 | void paravirt_leave_lazy_mmu(void); | |
1289 | void paravirt_leave_lazy(enum paravirt_lazy_mode mode); | |
1290 | ||
9226d125 | 1291 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
f8822f42 JF |
1292 | static inline void arch_enter_lazy_cpu_mode(void) |
1293 | { | |
8965c1c0 | 1294 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter); |
f8822f42 JF |
1295 | } |
1296 | ||
1297 | static inline void arch_leave_lazy_cpu_mode(void) | |
1298 | { | |
8965c1c0 | 1299 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave); |
f8822f42 JF |
1300 | } |
1301 | ||
1302 | static inline void arch_flush_lazy_cpu_mode(void) | |
1303 | { | |
8965c1c0 JF |
1304 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) { |
1305 | arch_leave_lazy_cpu_mode(); | |
1306 | arch_enter_lazy_cpu_mode(); | |
1307 | } | |
f8822f42 JF |
1308 | } |
1309 | ||
9226d125 ZA |
1310 | |
1311 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f8822f42 JF |
1312 | static inline void arch_enter_lazy_mmu_mode(void) |
1313 | { | |
8965c1c0 | 1314 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
1315 | } |
1316 | ||
1317 | static inline void arch_leave_lazy_mmu_mode(void) | |
1318 | { | |
8965c1c0 | 1319 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
1320 | } |
1321 | ||
1322 | static inline void arch_flush_lazy_mmu_mode(void) | |
1323 | { | |
8965c1c0 JF |
1324 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) { |
1325 | arch_leave_lazy_mmu_mode(); | |
1326 | arch_enter_lazy_mmu_mode(); | |
1327 | } | |
f8822f42 | 1328 | } |
9226d125 | 1329 | |
aeaaa59c JF |
1330 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
1331 | unsigned long phys, pgprot_t flags) | |
1332 | { | |
1333 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
1334 | } | |
1335 | ||
45876233 JF |
1336 | void _paravirt_nop(void); |
1337 | #define paravirt_nop ((void *)_paravirt_nop) | |
1338 | ||
139ec7c4 | 1339 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
98de032b | 1340 | struct paravirt_patch_site { |
139ec7c4 RR |
1341 | u8 *instr; /* original instructions */ |
1342 | u8 instrtype; /* type of this instruction */ | |
1343 | u8 len; /* length of original instruction */ | |
1344 | u16 clobbers; /* what registers you may clobber */ | |
1345 | }; | |
1346 | ||
98de032b JF |
1347 | extern struct paravirt_patch_site __parainstructions[], |
1348 | __parainstructions_end[]; | |
1349 | ||
2e47d3e6 GOC |
1350 | #ifdef CONFIG_X86_32 |
1351 | #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;" | |
1352 | #define PV_RESTORE_REGS "popl %%edx; popl %%ecx" | |
1353 | #define PV_FLAGS_ARG "0" | |
1354 | #define PV_EXTRA_CLOBBERS | |
1355 | #define PV_VEXTRA_CLOBBERS | |
1356 | #else | |
1357 | /* We save some registers, but all of them, that's too much. We clobber all | |
1358 | * caller saved registers but the argument parameter */ | |
1359 | #define PV_SAVE_REGS "pushq %%rdi;" | |
1360 | #define PV_RESTORE_REGS "popq %%rdi;" | |
1361 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx" | |
1362 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx" | |
1363 | #define PV_FLAGS_ARG "D" | |
1364 | #endif | |
1365 | ||
139ec7c4 RR |
1366 | static inline unsigned long __raw_local_save_flags(void) |
1367 | { | |
1368 | unsigned long f; | |
1369 | ||
2e47d3e6 | 1370 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1371 | PARAVIRT_CALL |
2e47d3e6 | 1372 | PV_RESTORE_REGS) |
d5822035 | 1373 | : "=a"(f) |
93b1eab3 | 1374 | : paravirt_type(pv_irq_ops.save_fl), |
42c24fa2 | 1375 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1376 | : "memory", "cc" PV_VEXTRA_CLOBBERS); |
139ec7c4 RR |
1377 | return f; |
1378 | } | |
1379 | ||
1380 | static inline void raw_local_irq_restore(unsigned long f) | |
1381 | { | |
2e47d3e6 | 1382 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1383 | PARAVIRT_CALL |
2e47d3e6 | 1384 | PV_RESTORE_REGS) |
d5822035 | 1385 | : "=a"(f) |
2e47d3e6 | 1386 | : PV_FLAGS_ARG(f), |
93b1eab3 | 1387 | paravirt_type(pv_irq_ops.restore_fl), |
d5822035 | 1388 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1389 | : "memory", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1390 | } |
1391 | ||
1392 | static inline void raw_local_irq_disable(void) | |
1393 | { | |
2e47d3e6 | 1394 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1395 | PARAVIRT_CALL |
2e47d3e6 | 1396 | PV_RESTORE_REGS) |
d5822035 | 1397 | : |
93b1eab3 | 1398 | : paravirt_type(pv_irq_ops.irq_disable), |
d5822035 | 1399 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1400 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1401 | } |
1402 | ||
1403 | static inline void raw_local_irq_enable(void) | |
1404 | { | |
2e47d3e6 | 1405 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1406 | PARAVIRT_CALL |
2e47d3e6 | 1407 | PV_RESTORE_REGS) |
d5822035 | 1408 | : |
93b1eab3 | 1409 | : paravirt_type(pv_irq_ops.irq_enable), |
d5822035 | 1410 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1411 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1412 | } |
1413 | ||
1414 | static inline unsigned long __raw_local_irq_save(void) | |
1415 | { | |
1416 | unsigned long f; | |
1417 | ||
d5822035 JF |
1418 | f = __raw_local_save_flags(); |
1419 | raw_local_irq_disable(); | |
139ec7c4 RR |
1420 | return f; |
1421 | } | |
1422 | ||
294688c0 | 1423 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 1424 | #undef PARAVIRT_CALL |
1a45b7aa JF |
1425 | #undef __PVOP_CALL |
1426 | #undef __PVOP_VCALL | |
f8822f42 JF |
1427 | #undef PVOP_VCALL0 |
1428 | #undef PVOP_CALL0 | |
1429 | #undef PVOP_VCALL1 | |
1430 | #undef PVOP_CALL1 | |
1431 | #undef PVOP_VCALL2 | |
1432 | #undef PVOP_CALL2 | |
1433 | #undef PVOP_VCALL3 | |
1434 | #undef PVOP_CALL3 | |
1435 | #undef PVOP_VCALL4 | |
1436 | #undef PVOP_CALL4 | |
139ec7c4 | 1437 | |
d3561b7f RR |
1438 | #else /* __ASSEMBLY__ */ |
1439 | ||
658be9d3 | 1440 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
1441 | 771:; \ |
1442 | ops; \ | |
1443 | 772:; \ | |
1444 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
1445 | .align algn; \ |
1446 | word 771b; \ | |
139ec7c4 RR |
1447 | .byte ptype; \ |
1448 | .byte 772b-771b; \ | |
1449 | .short clobbers; \ | |
1450 | .popsection | |
1451 | ||
658be9d3 GOC |
1452 | |
1453 | #ifdef CONFIG_X86_64 | |
6057fc82 GOC |
1454 | #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx |
1455 | #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax | |
1456 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) | |
658be9d3 | 1457 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 1458 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 1459 | #else |
6057fc82 GOC |
1460 | #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx |
1461 | #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax | |
1462 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) | |
658be9d3 | 1463 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 1464 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
1465 | #endif |
1466 | ||
93b1eab3 JF |
1467 | #define INTERRUPT_RETURN \ |
1468 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 1469 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
1470 | |
1471 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1472 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
491eccb7 JF |
1473 | PV_SAVE_REGS; \ |
1474 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ | |
6057fc82 | 1475 | PV_RESTORE_REGS;) \ |
d5822035 JF |
1476 | |
1477 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1478 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
491eccb7 JF |
1479 | PV_SAVE_REGS; \ |
1480 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ | |
6057fc82 | 1481 | PV_RESTORE_REGS;) |
d5822035 | 1482 | |
6abcd98f GOC |
1483 | #define ENABLE_INTERRUPTS_SYSCALL_RET \ |
1484 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\ | |
1485 | CLBR_NONE, \ | |
491eccb7 | 1486 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)) |
139ec7c4 | 1487 | |
2e47d3e6 | 1488 | |
6057fc82 | 1489 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
1490 | #define GET_CR0_INTO_EAX \ |
1491 | push %ecx; push %edx; \ | |
1492 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 1493 | pop %edx; pop %ecx |
4a8c4c4e | 1494 | #else |
e801f864 GOC |
1495 | #define SWAPGS \ |
1496 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
1497 | PV_SAVE_REGS; \ | |
491eccb7 | 1498 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \ |
e801f864 GOC |
1499 | PV_RESTORE_REGS \ |
1500 | ) | |
1501 | ||
491eccb7 JF |
1502 | #define GET_CR2_INTO_RCX \ |
1503 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \ | |
1504 | movq %rax, %rcx; \ | |
4a8c4c4e GOC |
1505 | xorq %rax, %rax; |
1506 | ||
6057fc82 | 1507 | #endif |
139ec7c4 | 1508 | |
d3561b7f RR |
1509 | #endif /* __ASSEMBLY__ */ |
1510 | #endif /* CONFIG_PARAVIRT */ | |
1511 | #endif /* __ASM_PARAVIRT_H */ |