Commit | Line | Data |
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77ef50a5 VN |
1 | #ifndef ASM_X86__PROCESSOR_H |
2 | #define ASM_X86__PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9 | ||
2f66dcc9 GOC |
10 | #include <asm/vm86.h> |
11 | #include <asm/math_emu.h> | |
12 | #include <asm/segment.h> | |
2f66dcc9 GOC |
13 | #include <asm/types.h> |
14 | #include <asm/sigcontext.h> | |
15 | #include <asm/current.h> | |
16 | #include <asm/cpufeature.h> | |
c72dcf83 | 17 | #include <asm/system.h> |
2f66dcc9 | 18 | #include <asm/page.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
93fa7636 | 23 | #include <asm/ds.h> |
4d46a89e | 24 | |
2f66dcc9 | 25 | #include <linux/personality.h> |
5300db88 GOC |
26 | #include <linux/cpumask.h> |
27 | #include <linux/cache.h> | |
2f66dcc9 GOC |
28 | #include <linux/threads.h> |
29 | #include <linux/init.h> | |
c72dcf83 | 30 | |
0ccb8acc GOC |
31 | /* |
32 | * Default implementation of macro that returns current | |
33 | * instruction pointer ("program counter"). | |
34 | */ | |
35 | static inline void *current_text_addr(void) | |
36 | { | |
37 | void *pc; | |
4d46a89e IM |
38 | |
39 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
40 | ||
0ccb8acc GOC |
41 | return pc; |
42 | } | |
43 | ||
dbcb4660 | 44 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
45 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
46 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 47 | #else |
4d46a89e IM |
48 | # define ARCH_MIN_TASKALIGN 16 |
49 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 | |
dbcb4660 GOC |
50 | #endif |
51 | ||
5300db88 GOC |
52 | /* |
53 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
54 | * Members of this structure are referenced in head.S, so think twice | |
55 | * before touching them. [mj] | |
56 | */ | |
57 | ||
58 | struct cpuinfo_x86 { | |
4d46a89e IM |
59 | __u8 x86; /* CPU family */ |
60 | __u8 x86_vendor; /* CPU vendor */ | |
61 | __u8 x86_model; | |
62 | __u8 x86_mask; | |
5300db88 | 63 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
64 | char wp_works_ok; /* It doesn't on 386's */ |
65 | ||
66 | /* Problems on some 486Dx4's and old 386's: */ | |
67 | char hlt_works_ok; | |
68 | char hard_math; | |
69 | char rfu; | |
70 | char fdiv_bug; | |
71 | char f00f_bug; | |
72 | char coma_bug; | |
73 | char pad0; | |
5300db88 | 74 | #else |
4d46a89e IM |
75 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
76 | int x86_tlbsize; | |
77 | __u8 x86_virt_bits; | |
78 | __u8 x86_phys_bits; | |
11fdd252 | 79 | #endif |
4d46a89e IM |
80 | /* CPUID returned core id bits: */ |
81 | __u8 x86_coreid_bits; | |
82 | /* Max extended CPUID function supported: */ | |
83 | __u32 extended_cpuid_level; | |
4d46a89e IM |
84 | /* Maximum supported CPUID level, -1=no CPUID: */ |
85 | int cpuid_level; | |
86 | __u32 x86_capability[NCAPINTS]; | |
87 | char x86_vendor_id[16]; | |
88 | char x86_model_id[64]; | |
89 | /* in KB - valid for CPUS which support this call: */ | |
90 | int x86_cache_size; | |
91 | int x86_cache_alignment; /* In bytes */ | |
92 | int x86_power; | |
93 | unsigned long loops_per_jiffy; | |
5300db88 | 94 | #ifdef CONFIG_SMP |
4d46a89e IM |
95 | /* cpus sharing the last level cache: */ |
96 | cpumask_t llc_shared_map; | |
5300db88 | 97 | #endif |
4d46a89e IM |
98 | /* cpuid returned max cores value: */ |
99 | u16 x86_max_cores; | |
100 | u16 apicid; | |
01aaea1a | 101 | u16 initial_apicid; |
4d46a89e | 102 | u16 x86_clflush_size; |
5300db88 | 103 | #ifdef CONFIG_SMP |
4d46a89e IM |
104 | /* number of cores as seen by the OS: */ |
105 | u16 booted_cores; | |
106 | /* Physical processor id: */ | |
107 | u16 phys_proc_id; | |
108 | /* Core id: */ | |
109 | u16 cpu_core_id; | |
110 | /* Index into per_cpu list: */ | |
111 | u16 cpu_index; | |
5300db88 GOC |
112 | #endif |
113 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); | |
114 | ||
4d46a89e IM |
115 | #define X86_VENDOR_INTEL 0 |
116 | #define X86_VENDOR_CYRIX 1 | |
117 | #define X86_VENDOR_AMD 2 | |
118 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
119 | #define X86_VENDOR_CENTAUR 5 |
120 | #define X86_VENDOR_TRANSMETA 7 | |
121 | #define X86_VENDOR_NSC 8 | |
122 | #define X86_VENDOR_NUM 9 | |
123 | ||
124 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 125 | |
1a53905a GOC |
126 | /* |
127 | * capabilities of CPUs | |
128 | */ | |
4d46a89e IM |
129 | extern struct cpuinfo_x86 boot_cpu_data; |
130 | extern struct cpuinfo_x86 new_cpu_data; | |
131 | ||
132 | extern struct tss_struct doublefault_tss; | |
133 | extern __u32 cleared_cpu_caps[NCAPINTS]; | |
5300db88 GOC |
134 | |
135 | #ifdef CONFIG_SMP | |
136 | DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info); | |
137 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) | |
94a1e869 | 138 | #define current_cpu_data __get_cpu_var(cpu_info) |
5300db88 GOC |
139 | #else |
140 | #define cpu_data(cpu) boot_cpu_data | |
141 | #define current_cpu_data boot_cpu_data | |
142 | #endif | |
143 | ||
1c6c727d JS |
144 | extern const struct seq_operations cpuinfo_op; |
145 | ||
3d3f487c GC |
146 | static inline int hlt_works(int cpu) |
147 | { | |
148 | #ifdef CONFIG_X86_32 | |
149 | return cpu_data(cpu).hlt_works_ok; | |
150 | #else | |
151 | return 1; | |
152 | #endif | |
153 | } | |
154 | ||
4d46a89e IM |
155 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
156 | ||
157 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a53905a | 158 | |
8fd329a1 JS |
159 | extern struct pt_regs *idle_regs(struct pt_regs *); |
160 | ||
f580366f | 161 | extern void early_cpu_init(void); |
1a53905a GOC |
162 | extern void identify_boot_cpu(void); |
163 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 GOC |
164 | extern void print_cpu_info(struct cpuinfo_x86 *); |
165 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); | |
166 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
167 | extern unsigned short num_cache_leaves; | |
168 | ||
bbb65d2d | 169 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 170 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 171 | |
c758ecf6 | 172 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 173 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
174 | { |
175 | /* ecx is often an input as well as an output. */ | |
cca2e6f8 JP |
176 | asm("cpuid" |
177 | : "=a" (*eax), | |
178 | "=b" (*ebx), | |
179 | "=c" (*ecx), | |
180 | "=d" (*edx) | |
181 | : "0" (*eax), "2" (*ecx)); | |
c758ecf6 GOC |
182 | } |
183 | ||
c72dcf83 GOC |
184 | static inline void load_cr3(pgd_t *pgdir) |
185 | { | |
186 | write_cr3(__pa(pgdir)); | |
187 | } | |
c758ecf6 | 188 | |
ca241c75 GOC |
189 | #ifdef CONFIG_X86_32 |
190 | /* This is the TSS defined by the hardware. */ | |
191 | struct x86_hw_tss { | |
4d46a89e IM |
192 | unsigned short back_link, __blh; |
193 | unsigned long sp0; | |
194 | unsigned short ss0, __ss0h; | |
195 | unsigned long sp1; | |
196 | /* ss1 caches MSR_IA32_SYSENTER_CS: */ | |
197 | unsigned short ss1, __ss1h; | |
198 | unsigned long sp2; | |
199 | unsigned short ss2, __ss2h; | |
200 | unsigned long __cr3; | |
201 | unsigned long ip; | |
202 | unsigned long flags; | |
203 | unsigned long ax; | |
204 | unsigned long cx; | |
205 | unsigned long dx; | |
206 | unsigned long bx; | |
207 | unsigned long sp; | |
208 | unsigned long bp; | |
209 | unsigned long si; | |
210 | unsigned long di; | |
211 | unsigned short es, __esh; | |
212 | unsigned short cs, __csh; | |
213 | unsigned short ss, __ssh; | |
214 | unsigned short ds, __dsh; | |
215 | unsigned short fs, __fsh; | |
216 | unsigned short gs, __gsh; | |
217 | unsigned short ldt, __ldth; | |
218 | unsigned short trace; | |
219 | unsigned short io_bitmap_base; | |
220 | ||
ca241c75 GOC |
221 | } __attribute__((packed)); |
222 | #else | |
223 | struct x86_hw_tss { | |
4d46a89e IM |
224 | u32 reserved1; |
225 | u64 sp0; | |
226 | u64 sp1; | |
227 | u64 sp2; | |
228 | u64 reserved2; | |
229 | u64 ist[7]; | |
230 | u32 reserved3; | |
231 | u32 reserved4; | |
232 | u16 reserved5; | |
233 | u16 io_bitmap_base; | |
234 | ||
ca241c75 GOC |
235 | } __attribute__((packed)) ____cacheline_aligned; |
236 | #endif | |
237 | ||
238 | /* | |
4d46a89e | 239 | * IO-bitmap sizes: |
ca241c75 | 240 | */ |
4d46a89e IM |
241 | #define IO_BITMAP_BITS 65536 |
242 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
243 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
244 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
245 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
246 | #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 | |
ca241c75 GOC |
247 | |
248 | struct tss_struct { | |
4d46a89e IM |
249 | /* |
250 | * The hardware state: | |
251 | */ | |
252 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
253 | |
254 | /* | |
255 | * The extra 1 is there because the CPU will access an | |
256 | * additional byte beyond the end of the IO permission | |
257 | * bitmap. The extra byte must be all 1 bits, and must | |
258 | * be within the limit. | |
259 | */ | |
4d46a89e | 260 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
ca241c75 GOC |
261 | /* |
262 | * Cache the current maximum and the last task that used the bitmap: | |
263 | */ | |
4d46a89e IM |
264 | unsigned long io_bitmap_max; |
265 | struct thread_struct *io_bitmap_owner; | |
266 | ||
ca241c75 | 267 | /* |
4d46a89e | 268 | * .. and then another 0x100 bytes for the emergency kernel stack: |
ca241c75 | 269 | */ |
4d46a89e IM |
270 | unsigned long stack[64]; |
271 | ||
84e65b0a | 272 | } ____cacheline_aligned; |
ca241c75 GOC |
273 | |
274 | DECLARE_PER_CPU(struct tss_struct, init_tss); | |
275 | ||
4d46a89e IM |
276 | /* |
277 | * Save the original ist values for checking stack pointers during debugging | |
278 | */ | |
1a53905a | 279 | struct orig_ist { |
4d46a89e | 280 | unsigned long ist[7]; |
1a53905a GOC |
281 | }; |
282 | ||
99f8ecdf | 283 | #define MXCSR_DEFAULT 0x1f80 |
46265df0 | 284 | |
99f8ecdf | 285 | struct i387_fsave_struct { |
ca9cda2f IM |
286 | u32 cwd; /* FPU Control Word */ |
287 | u32 swd; /* FPU Status Word */ | |
288 | u32 twd; /* FPU Tag Word */ | |
289 | u32 fip; /* FPU IP Offset */ | |
290 | u32 fcs; /* FPU IP Selector */ | |
291 | u32 foo; /* FPU Operand Pointer Offset */ | |
292 | u32 fos; /* FPU Operand Pointer Selector */ | |
293 | ||
294 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
4d46a89e | 295 | u32 st_space[20]; |
ca9cda2f IM |
296 | |
297 | /* Software status information [not touched by FSAVE ]: */ | |
4d46a89e | 298 | u32 status; |
46265df0 GOC |
299 | }; |
300 | ||
46265df0 | 301 | struct i387_fxsave_struct { |
ca9cda2f IM |
302 | u16 cwd; /* Control Word */ |
303 | u16 swd; /* Status Word */ | |
304 | u16 twd; /* Tag Word */ | |
305 | u16 fop; /* Last Instruction Opcode */ | |
99f8ecdf RM |
306 | union { |
307 | struct { | |
ca9cda2f IM |
308 | u64 rip; /* Instruction Pointer */ |
309 | u64 rdp; /* Data Pointer */ | |
99f8ecdf RM |
310 | }; |
311 | struct { | |
ca9cda2f IM |
312 | u32 fip; /* FPU IP Offset */ |
313 | u32 fcs; /* FPU IP Selector */ | |
314 | u32 foo; /* FPU Operand Offset */ | |
315 | u32 fos; /* FPU Operand Selector */ | |
99f8ecdf RM |
316 | }; |
317 | }; | |
ca9cda2f IM |
318 | u32 mxcsr; /* MXCSR Register State */ |
319 | u32 mxcsr_mask; /* MXCSR Mask */ | |
320 | ||
321 | /* 8*16 bytes for each FP-reg = 128 bytes: */ | |
4d46a89e | 322 | u32 st_space[32]; |
ca9cda2f IM |
323 | |
324 | /* 16*16 bytes for each XMM-reg = 256 bytes: */ | |
4d46a89e | 325 | u32 xmm_space[64]; |
ca9cda2f | 326 | |
bdd8caba SS |
327 | u32 padding[12]; |
328 | ||
329 | union { | |
330 | u32 padding1[12]; | |
331 | u32 sw_reserved[12]; | |
332 | }; | |
4d46a89e | 333 | |
46265df0 GOC |
334 | } __attribute__((aligned(16))); |
335 | ||
99f8ecdf | 336 | struct i387_soft_struct { |
4d46a89e IM |
337 | u32 cwd; |
338 | u32 swd; | |
339 | u32 twd; | |
340 | u32 fip; | |
341 | u32 fcs; | |
342 | u32 foo; | |
343 | u32 fos; | |
344 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
345 | u32 st_space[20]; | |
346 | u8 ftop; | |
347 | u8 changed; | |
348 | u8 lookahead; | |
349 | u8 no_update; | |
350 | u8 rm; | |
351 | u8 alimit; | |
352 | struct info *info; | |
353 | u32 entry_eip; | |
99f8ecdf RM |
354 | }; |
355 | ||
dc1e35c6 SS |
356 | struct xsave_hdr_struct { |
357 | u64 xstate_bv; | |
358 | u64 reserved1[2]; | |
359 | u64 reserved2[5]; | |
360 | } __attribute__((packed)); | |
361 | ||
362 | struct xsave_struct { | |
363 | struct i387_fxsave_struct i387; | |
364 | struct xsave_hdr_struct xsave_hdr; | |
365 | /* new processor state extensions will go here */ | |
366 | } __attribute__ ((packed, aligned (64))); | |
367 | ||
61c4628b | 368 | union thread_xstate { |
99f8ecdf | 369 | struct i387_fsave_struct fsave; |
46265df0 | 370 | struct i387_fxsave_struct fxsave; |
4d46a89e | 371 | struct i387_soft_struct soft; |
b359e8a4 | 372 | struct xsave_struct xsave; |
46265df0 GOC |
373 | }; |
374 | ||
fe676203 | 375 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 376 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
96a388de | 377 | #endif |
c758ecf6 | 378 | |
683e0253 | 379 | extern void print_cpu_info(struct cpuinfo_x86 *); |
61c4628b | 380 | extern unsigned int xstate_size; |
aa283f49 SS |
381 | extern void free_thread_xstate(struct task_struct *); |
382 | extern struct kmem_cache *task_xstate_cachep; | |
683e0253 GOC |
383 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
384 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
385 | extern unsigned short num_cache_leaves; | |
386 | ||
cb38d377 | 387 | struct thread_struct { |
4d46a89e IM |
388 | /* Cached TLS descriptors: */ |
389 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
390 | unsigned long sp0; | |
391 | unsigned long sp; | |
cb38d377 | 392 | #ifdef CONFIG_X86_32 |
4d46a89e | 393 | unsigned long sysenter_cs; |
cb38d377 | 394 | #else |
4d46a89e IM |
395 | unsigned long usersp; /* Copy from PDA */ |
396 | unsigned short es; | |
397 | unsigned short ds; | |
398 | unsigned short fsindex; | |
399 | unsigned short gsindex; | |
cb38d377 | 400 | #endif |
4d46a89e IM |
401 | unsigned long ip; |
402 | unsigned long fs; | |
403 | unsigned long gs; | |
404 | /* Hardware debugging registers: */ | |
405 | unsigned long debugreg0; | |
406 | unsigned long debugreg1; | |
407 | unsigned long debugreg2; | |
408 | unsigned long debugreg3; | |
409 | unsigned long debugreg6; | |
410 | unsigned long debugreg7; | |
411 | /* Fault info: */ | |
412 | unsigned long cr2; | |
413 | unsigned long trap_no; | |
414 | unsigned long error_code; | |
61c4628b SS |
415 | /* floating point and extended processor state */ |
416 | union thread_xstate *xstate; | |
cb38d377 | 417 | #ifdef CONFIG_X86_32 |
4d46a89e | 418 | /* Virtual 86 mode info */ |
cb38d377 GOC |
419 | struct vm86_struct __user *vm86_info; |
420 | unsigned long screen_bitmap; | |
4d46a89e IM |
421 | unsigned long v86flags; |
422 | unsigned long v86mask; | |
423 | unsigned long saved_sp0; | |
424 | unsigned int saved_fs; | |
425 | unsigned int saved_gs; | |
cb38d377 | 426 | #endif |
4d46a89e IM |
427 | /* IO permissions: */ |
428 | unsigned long *io_bitmap_ptr; | |
429 | unsigned long iopl; | |
430 | /* Max allowed port in the bitmap, in bytes: */ | |
431 | unsigned io_bitmap_max; | |
cb38d377 GOC |
432 | /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ |
433 | unsigned long debugctlmsr; | |
93fa7636 MM |
434 | #ifdef CONFIG_X86_DS |
435 | /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */ | |
436 | struct ds_context *ds_ctx; | |
437 | #endif /* CONFIG_X86_DS */ | |
438 | #ifdef CONFIG_X86_PTRACE_BTS | |
439 | /* the signal to send on a bts buffer overflow */ | |
440 | unsigned int bts_ovfl_signal; | |
441 | #endif /* CONFIG_X86_PTRACE_BTS */ | |
cb38d377 GOC |
442 | }; |
443 | ||
1b46cbe0 GOC |
444 | static inline unsigned long native_get_debugreg(int regno) |
445 | { | |
4d46a89e | 446 | unsigned long val = 0; /* Damn you, gcc! */ |
1b46cbe0 GOC |
447 | |
448 | switch (regno) { | |
449 | case 0: | |
cca2e6f8 JP |
450 | asm("mov %%db0, %0" :"=r" (val)); |
451 | break; | |
1b46cbe0 | 452 | case 1: |
cca2e6f8 JP |
453 | asm("mov %%db1, %0" :"=r" (val)); |
454 | break; | |
1b46cbe0 | 455 | case 2: |
cca2e6f8 JP |
456 | asm("mov %%db2, %0" :"=r" (val)); |
457 | break; | |
1b46cbe0 | 458 | case 3: |
cca2e6f8 JP |
459 | asm("mov %%db3, %0" :"=r" (val)); |
460 | break; | |
1b46cbe0 | 461 | case 6: |
cca2e6f8 JP |
462 | asm("mov %%db6, %0" :"=r" (val)); |
463 | break; | |
1b46cbe0 | 464 | case 7: |
cca2e6f8 JP |
465 | asm("mov %%db7, %0" :"=r" (val)); |
466 | break; | |
1b46cbe0 GOC |
467 | default: |
468 | BUG(); | |
469 | } | |
470 | return val; | |
471 | } | |
472 | ||
473 | static inline void native_set_debugreg(int regno, unsigned long value) | |
474 | { | |
475 | switch (regno) { | |
476 | case 0: | |
4d46a89e | 477 | asm("mov %0, %%db0" ::"r" (value)); |
1b46cbe0 GOC |
478 | break; |
479 | case 1: | |
4d46a89e | 480 | asm("mov %0, %%db1" ::"r" (value)); |
1b46cbe0 GOC |
481 | break; |
482 | case 2: | |
4d46a89e | 483 | asm("mov %0, %%db2" ::"r" (value)); |
1b46cbe0 GOC |
484 | break; |
485 | case 3: | |
4d46a89e | 486 | asm("mov %0, %%db3" ::"r" (value)); |
1b46cbe0 GOC |
487 | break; |
488 | case 6: | |
4d46a89e | 489 | asm("mov %0, %%db6" ::"r" (value)); |
1b46cbe0 GOC |
490 | break; |
491 | case 7: | |
4d46a89e | 492 | asm("mov %0, %%db7" ::"r" (value)); |
1b46cbe0 GOC |
493 | break; |
494 | default: | |
495 | BUG(); | |
496 | } | |
497 | } | |
498 | ||
62d7d7ed GOC |
499 | /* |
500 | * Set IOPL bits in EFLAGS from given mask | |
501 | */ | |
502 | static inline void native_set_iopl_mask(unsigned mask) | |
503 | { | |
504 | #ifdef CONFIG_X86_32 | |
505 | unsigned int reg; | |
4d46a89e | 506 | |
cca2e6f8 JP |
507 | asm volatile ("pushfl;" |
508 | "popl %0;" | |
509 | "andl %1, %0;" | |
510 | "orl %2, %0;" | |
511 | "pushl %0;" | |
512 | "popfl" | |
513 | : "=&r" (reg) | |
514 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
515 | #endif |
516 | } | |
517 | ||
4d46a89e IM |
518 | static inline void |
519 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
520 | { |
521 | tss->x86_tss.sp0 = thread->sp0; | |
522 | #ifdef CONFIG_X86_32 | |
4d46a89e | 523 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
524 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
525 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
526 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
527 | } | |
528 | #endif | |
529 | } | |
1b46cbe0 | 530 | |
e801f864 GOC |
531 | static inline void native_swapgs(void) |
532 | { | |
533 | #ifdef CONFIG_X86_64 | |
534 | asm volatile("swapgs" ::: "memory"); | |
535 | #endif | |
536 | } | |
537 | ||
7818a1e0 GOC |
538 | #ifdef CONFIG_PARAVIRT |
539 | #include <asm/paravirt.h> | |
540 | #else | |
4d46a89e IM |
541 | #define __cpuid native_cpuid |
542 | #define paravirt_enabled() 0 | |
1b46cbe0 GOC |
543 | |
544 | /* | |
545 | * These special macros can be used to get or set a debugging register | |
546 | */ | |
547 | #define get_debugreg(var, register) \ | |
548 | (var) = native_get_debugreg(register) | |
549 | #define set_debugreg(value, register) \ | |
550 | native_set_debugreg(register, value) | |
551 | ||
cca2e6f8 JP |
552 | static inline void load_sp0(struct tss_struct *tss, |
553 | struct thread_struct *thread) | |
7818a1e0 GOC |
554 | { |
555 | native_load_sp0(tss, thread); | |
556 | } | |
557 | ||
62d7d7ed | 558 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
559 | #endif /* CONFIG_PARAVIRT */ |
560 | ||
561 | /* | |
562 | * Save the cr4 feature set we're using (ie | |
563 | * Pentium 4MB enable and PPro Global page | |
564 | * enable), so that any CPU's that boot up | |
565 | * after us can get the correct flags. | |
566 | */ | |
4d46a89e | 567 | extern unsigned long mmu_cr4_features; |
1b46cbe0 GOC |
568 | |
569 | static inline void set_in_cr4(unsigned long mask) | |
570 | { | |
571 | unsigned cr4; | |
4d46a89e | 572 | |
1b46cbe0 GOC |
573 | mmu_cr4_features |= mask; |
574 | cr4 = read_cr4(); | |
575 | cr4 |= mask; | |
576 | write_cr4(cr4); | |
577 | } | |
578 | ||
579 | static inline void clear_in_cr4(unsigned long mask) | |
580 | { | |
581 | unsigned cr4; | |
4d46a89e | 582 | |
1b46cbe0 GOC |
583 | mmu_cr4_features &= ~mask; |
584 | cr4 = read_cr4(); | |
585 | cr4 &= ~mask; | |
586 | write_cr4(cr4); | |
587 | } | |
588 | ||
fc87e906 | 589 | typedef struct { |
4d46a89e | 590 | unsigned long seg; |
fc87e906 GOC |
591 | } mm_segment_t; |
592 | ||
593 | ||
683e0253 GOC |
594 | /* |
595 | * create a kernel thread without removing it from tasklists | |
596 | */ | |
597 | extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | |
598 | ||
599 | /* Free all resources held by a thread. */ | |
600 | extern void release_thread(struct task_struct *); | |
601 | ||
4d46a89e | 602 | /* Prepare to copy thread state - unlazy all lazy state */ |
683e0253 | 603 | extern void prepare_to_copy(struct task_struct *tsk); |
1b46cbe0 | 604 | |
683e0253 | 605 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
606 | |
607 | /* | |
608 | * Generic CPUID function | |
609 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
610 | * resulting in stale register contents being returned. | |
611 | */ | |
612 | static inline void cpuid(unsigned int op, | |
613 | unsigned int *eax, unsigned int *ebx, | |
614 | unsigned int *ecx, unsigned int *edx) | |
615 | { | |
616 | *eax = op; | |
617 | *ecx = 0; | |
618 | __cpuid(eax, ebx, ecx, edx); | |
619 | } | |
620 | ||
621 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
622 | static inline void cpuid_count(unsigned int op, int count, | |
623 | unsigned int *eax, unsigned int *ebx, | |
624 | unsigned int *ecx, unsigned int *edx) | |
625 | { | |
626 | *eax = op; | |
627 | *ecx = count; | |
628 | __cpuid(eax, ebx, ecx, edx); | |
629 | } | |
630 | ||
631 | /* | |
632 | * CPUID functions returning a single datum | |
633 | */ | |
634 | static inline unsigned int cpuid_eax(unsigned int op) | |
635 | { | |
636 | unsigned int eax, ebx, ecx, edx; | |
637 | ||
638 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 639 | |
c758ecf6 GOC |
640 | return eax; |
641 | } | |
4d46a89e | 642 | |
c758ecf6 GOC |
643 | static inline unsigned int cpuid_ebx(unsigned int op) |
644 | { | |
645 | unsigned int eax, ebx, ecx, edx; | |
646 | ||
647 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 648 | |
c758ecf6 GOC |
649 | return ebx; |
650 | } | |
4d46a89e | 651 | |
c758ecf6 GOC |
652 | static inline unsigned int cpuid_ecx(unsigned int op) |
653 | { | |
654 | unsigned int eax, ebx, ecx, edx; | |
655 | ||
656 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 657 | |
c758ecf6 GOC |
658 | return ecx; |
659 | } | |
4d46a89e | 660 | |
c758ecf6 GOC |
661 | static inline unsigned int cpuid_edx(unsigned int op) |
662 | { | |
663 | unsigned int eax, ebx, ecx, edx; | |
664 | ||
665 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 666 | |
c758ecf6 GOC |
667 | return edx; |
668 | } | |
669 | ||
683e0253 GOC |
670 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
671 | static inline void rep_nop(void) | |
672 | { | |
cca2e6f8 | 673 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
674 | } |
675 | ||
4d46a89e IM |
676 | static inline void cpu_relax(void) |
677 | { | |
678 | rep_nop(); | |
679 | } | |
680 | ||
681 | /* Stop speculative execution: */ | |
683e0253 GOC |
682 | static inline void sync_core(void) |
683 | { | |
684 | int tmp; | |
4d46a89e | 685 | |
683e0253 | 686 | asm volatile("cpuid" : "=a" (tmp) : "0" (1) |
cca2e6f8 | 687 | : "ebx", "ecx", "edx", "memory"); |
683e0253 GOC |
688 | } |
689 | ||
cca2e6f8 JP |
690 | static inline void __monitor(const void *eax, unsigned long ecx, |
691 | unsigned long edx) | |
683e0253 | 692 | { |
4d46a89e | 693 | /* "monitor %eax, %ecx, %edx;" */ |
cca2e6f8 JP |
694 | asm volatile(".byte 0x0f, 0x01, 0xc8;" |
695 | :: "a" (eax), "c" (ecx), "d"(edx)); | |
683e0253 GOC |
696 | } |
697 | ||
698 | static inline void __mwait(unsigned long eax, unsigned long ecx) | |
699 | { | |
4d46a89e | 700 | /* "mwait %eax, %ecx;" */ |
cca2e6f8 JP |
701 | asm volatile(".byte 0x0f, 0x01, 0xc9;" |
702 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
703 | } |
704 | ||
705 | static inline void __sti_mwait(unsigned long eax, unsigned long ecx) | |
706 | { | |
7f424a8b | 707 | trace_hardirqs_on(); |
4d46a89e | 708 | /* "mwait %eax, %ecx;" */ |
cca2e6f8 JP |
709 | asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" |
710 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
711 | } |
712 | ||
713 | extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); | |
714 | ||
683e0253 GOC |
715 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
716 | ||
4d46a89e | 717 | extern unsigned long boot_option_idle_override; |
c1e3b377 | 718 | extern unsigned long idle_halt; |
da5e09a1 | 719 | extern unsigned long idle_nomwait; |
683e0253 | 720 | |
394a1505 ML |
721 | /* |
722 | * on systems with caches, caches must be flashed as the absolute | |
723 | * last instruction before going into a suspended halt. Otherwise, | |
724 | * dirty data can linger in the cache and become stale on resume, | |
725 | * leading to strange errors. | |
726 | * | |
727 | * perform a variety of operations to guarantee that the compiler | |
728 | * will not reorder instructions. wbinvd itself is serializing | |
729 | * so the processor will not reorder. | |
730 | * | |
731 | * Systems without cache can just go into halt. | |
732 | */ | |
733 | static inline void wbinvd_halt(void) | |
734 | { | |
735 | mb(); | |
736 | /* check for clflush to determine if wbinvd is legal */ | |
737 | if (cpu_has_clflush) | |
738 | asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); | |
739 | else | |
740 | while (1) | |
741 | halt(); | |
742 | } | |
743 | ||
1a53905a GOC |
744 | extern void enable_sep_cpu(void); |
745 | extern int sysenter_setup(void); | |
746 | ||
747 | /* Defined in head.S */ | |
4d46a89e | 748 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
749 | |
750 | extern void cpu_set_gdt(int); | |
751 | extern void switch_to_new_gdt(void); | |
752 | extern void cpu_init(void); | |
753 | extern void init_gdt(int cpu); | |
754 | ||
5b0e5084 JB |
755 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
756 | { | |
757 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
758 | if (boot_cpu_data.x86 < 6) | |
759 | return; | |
760 | #endif | |
761 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
762 | } | |
763 | ||
4d46a89e IM |
764 | /* |
765 | * from system description table in BIOS. Mostly for MCA use, but | |
766 | * others may find it useful: | |
767 | */ | |
768 | extern unsigned int machine_id; | |
769 | extern unsigned int machine_submodel_id; | |
770 | extern unsigned int BIOS_revision; | |
1a53905a | 771 | |
4d46a89e IM |
772 | /* Boot loader type from the setup header: */ |
773 | extern int bootloader_type; | |
1a53905a | 774 | |
4d46a89e | 775 | extern char ignore_fpu_irq; |
683e0253 GOC |
776 | |
777 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
778 | #define ARCH_HAS_PREFETCHW | |
779 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
780 | ||
ae2e15eb | 781 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
782 | # define BASE_PREFETCH ASM_NOP4 |
783 | # define ARCH_HAS_PREFETCH | |
ae2e15eb | 784 | #else |
4d46a89e | 785 | # define BASE_PREFETCH "prefetcht0 (%1)" |
ae2e15eb GOC |
786 | #endif |
787 | ||
4d46a89e IM |
788 | /* |
789 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
790 | * | |
791 | * It's not worth to care about 3dnow prefetches for the K6 | |
792 | * because they are microcoded there and very slow. | |
793 | */ | |
ae2e15eb GOC |
794 | static inline void prefetch(const void *x) |
795 | { | |
796 | alternative_input(BASE_PREFETCH, | |
797 | "prefetchnta (%1)", | |
798 | X86_FEATURE_XMM, | |
799 | "r" (x)); | |
800 | } | |
801 | ||
4d46a89e IM |
802 | /* |
803 | * 3dnow prefetch to get an exclusive cache line. | |
804 | * Useful for spinlocks to avoid one state transition in the | |
805 | * cache coherency protocol: | |
806 | */ | |
ae2e15eb GOC |
807 | static inline void prefetchw(const void *x) |
808 | { | |
809 | alternative_input(BASE_PREFETCH, | |
810 | "prefetchw (%1)", | |
811 | X86_FEATURE_3DNOW, | |
812 | "r" (x)); | |
813 | } | |
814 | ||
4d46a89e IM |
815 | static inline void spin_lock_prefetch(const void *x) |
816 | { | |
817 | prefetchw(x); | |
818 | } | |
819 | ||
2f66dcc9 GOC |
820 | #ifdef CONFIG_X86_32 |
821 | /* | |
822 | * User space process size: 3GB (default). | |
823 | */ | |
4d46a89e IM |
824 | #define TASK_SIZE PAGE_OFFSET |
825 | #define STACK_TOP TASK_SIZE | |
826 | #define STACK_TOP_MAX STACK_TOP | |
827 | ||
828 | #define INIT_THREAD { \ | |
829 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ | |
830 | .vm86_info = NULL, \ | |
831 | .sysenter_cs = __KERNEL_CS, \ | |
832 | .io_bitmap_ptr = NULL, \ | |
833 | .fs = __KERNEL_PERCPU, \ | |
2f66dcc9 GOC |
834 | } |
835 | ||
836 | /* | |
837 | * Note that the .io_bitmap member must be extra-big. This is because | |
838 | * the CPU will access an additional byte beyond the end of the IO | |
839 | * permission bitmap. The extra byte must be all 1 bits, and must | |
840 | * be within the limit. | |
841 | */ | |
4d46a89e IM |
842 | #define INIT_TSS { \ |
843 | .x86_tss = { \ | |
2f66dcc9 | 844 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ |
4d46a89e IM |
845 | .ss0 = __KERNEL_DS, \ |
846 | .ss1 = __KERNEL_CS, \ | |
847 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ | |
848 | }, \ | |
849 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ | |
2f66dcc9 GOC |
850 | } |
851 | ||
2f66dcc9 GOC |
852 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
853 | ||
854 | #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) | |
855 | #define KSTK_TOP(info) \ | |
856 | ({ \ | |
857 | unsigned long *__ptr = (unsigned long *)(info); \ | |
858 | (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ | |
859 | }) | |
860 | ||
861 | /* | |
862 | * The below -8 is to reserve 8 bytes on top of the ring0 stack. | |
863 | * This is necessary to guarantee that the entire "struct pt_regs" | |
864 | * is accessable even if the CPU haven't stored the SS/ESP registers | |
865 | * on the stack (interrupt gate does not save these registers | |
866 | * when switching to the same priv ring). | |
867 | * Therefore beware: accessing the ss/esp fields of the | |
868 | * "struct pt_regs" is possible, but they may contain the | |
869 | * completely wrong values. | |
870 | */ | |
871 | #define task_pt_regs(task) \ | |
872 | ({ \ | |
873 | struct pt_regs *__regs__; \ | |
874 | __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ | |
875 | __regs__ - 1; \ | |
876 | }) | |
877 | ||
4d46a89e | 878 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
879 | |
880 | #else | |
881 | /* | |
882 | * User space process size. 47bits minus one guard page. | |
883 | */ | |
a5ae1c37 | 884 | #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
885 | |
886 | /* This decides where the kernel will search for a free chunk of vm | |
887 | * space during mmap's. | |
888 | */ | |
4d46a89e IM |
889 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
890 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 891 | |
4d46a89e IM |
892 | #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ |
893 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
894 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ | |
895 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
2f66dcc9 | 896 | |
922a70d3 DH |
897 | #define STACK_TOP TASK_SIZE |
898 | #define STACK_TOP_MAX TASK_SIZE64 | |
899 | ||
2f66dcc9 GOC |
900 | #define INIT_THREAD { \ |
901 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
902 | } | |
903 | ||
904 | #define INIT_TSS { \ | |
905 | .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
906 | } | |
907 | ||
2f66dcc9 GOC |
908 | /* |
909 | * Return saved PC of a blocked thread. | |
910 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
911 | */ | |
4d46a89e | 912 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
2f66dcc9 | 913 | |
4d46a89e IM |
914 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
915 | #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ | |
2f66dcc9 GOC |
916 | #endif /* CONFIG_X86_64 */ |
917 | ||
513ad84b IM |
918 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
919 | unsigned long new_sp); | |
920 | ||
4d46a89e IM |
921 | /* |
922 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
923 | * space during mmap's. |
924 | */ | |
925 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
926 | ||
4d46a89e | 927 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 928 | |
529e25f6 EB |
929 | /* Get/set a process' ability to use the timestamp counter instruction */ |
930 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
931 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
932 | ||
933 | extern int get_tsc_mode(unsigned long adr); | |
934 | extern int set_tsc_mode(unsigned int val); | |
935 | ||
77ef50a5 | 936 | #endif /* ASM_X86__PROCESSOR_H */ |