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c758ecf6 GOC |
1 | #ifndef __ASM_X86_PROCESSOR_H |
2 | #define __ASM_X86_PROCESSOR_H | |
3 | ||
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
58f6f6ea IM |
6 | /* migration helpers, for KVM - will be removed in 2.6.25: */ |
7 | #include <asm/vm86.h> | |
8 | #define Xgt_desc_struct desc_ptr | |
9 | ||
683e0253 GOC |
10 | /* Forward declaration, a strange C thing */ |
11 | struct task_struct; | |
12 | struct mm_struct; | |
13 | ||
2f66dcc9 GOC |
14 | #include <asm/vm86.h> |
15 | #include <asm/math_emu.h> | |
16 | #include <asm/segment.h> | |
2f66dcc9 GOC |
17 | #include <asm/types.h> |
18 | #include <asm/sigcontext.h> | |
19 | #include <asm/current.h> | |
20 | #include <asm/cpufeature.h> | |
c72dcf83 | 21 | #include <asm/system.h> |
2f66dcc9 | 22 | #include <asm/page.h> |
5300db88 | 23 | #include <asm/percpu.h> |
2f66dcc9 GOC |
24 | #include <asm/msr.h> |
25 | #include <asm/desc_defs.h> | |
bd61643e | 26 | #include <asm/nops.h> |
4d46a89e | 27 | |
2f66dcc9 | 28 | #include <linux/personality.h> |
5300db88 GOC |
29 | #include <linux/cpumask.h> |
30 | #include <linux/cache.h> | |
2f66dcc9 GOC |
31 | #include <linux/threads.h> |
32 | #include <linux/init.h> | |
c72dcf83 | 33 | |
0ccb8acc GOC |
34 | /* |
35 | * Default implementation of macro that returns current | |
36 | * instruction pointer ("program counter"). | |
37 | */ | |
38 | static inline void *current_text_addr(void) | |
39 | { | |
40 | void *pc; | |
4d46a89e IM |
41 | |
42 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
43 | ||
0ccb8acc GOC |
44 | return pc; |
45 | } | |
46 | ||
dbcb4660 | 47 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
48 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
49 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 50 | #else |
4d46a89e IM |
51 | # define ARCH_MIN_TASKALIGN 16 |
52 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 | |
dbcb4660 GOC |
53 | #endif |
54 | ||
5300db88 GOC |
55 | /* |
56 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
57 | * Members of this structure are referenced in head.S, so think twice | |
58 | * before touching them. [mj] | |
59 | */ | |
60 | ||
61 | struct cpuinfo_x86 { | |
4d46a89e IM |
62 | __u8 x86; /* CPU family */ |
63 | __u8 x86_vendor; /* CPU vendor */ | |
64 | __u8 x86_model; | |
65 | __u8 x86_mask; | |
5300db88 | 66 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
67 | char wp_works_ok; /* It doesn't on 386's */ |
68 | ||
69 | /* Problems on some 486Dx4's and old 386's: */ | |
70 | char hlt_works_ok; | |
71 | char hard_math; | |
72 | char rfu; | |
73 | char fdiv_bug; | |
74 | char f00f_bug; | |
75 | char coma_bug; | |
76 | char pad0; | |
5300db88 | 77 | #else |
4d46a89e IM |
78 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
79 | int x86_tlbsize; | |
80 | __u8 x86_virt_bits; | |
81 | __u8 x86_phys_bits; | |
82 | /* CPUID returned core id bits: */ | |
83 | __u8 x86_coreid_bits; | |
84 | /* Max extended CPUID function supported: */ | |
85 | __u32 extended_cpuid_level; | |
5300db88 | 86 | #endif |
4d46a89e IM |
87 | /* Maximum supported CPUID level, -1=no CPUID: */ |
88 | int cpuid_level; | |
89 | __u32 x86_capability[NCAPINTS]; | |
90 | char x86_vendor_id[16]; | |
91 | char x86_model_id[64]; | |
92 | /* in KB - valid for CPUS which support this call: */ | |
93 | int x86_cache_size; | |
94 | int x86_cache_alignment; /* In bytes */ | |
95 | int x86_power; | |
96 | unsigned long loops_per_jiffy; | |
5300db88 | 97 | #ifdef CONFIG_SMP |
4d46a89e IM |
98 | /* cpus sharing the last level cache: */ |
99 | cpumask_t llc_shared_map; | |
5300db88 | 100 | #endif |
4d46a89e IM |
101 | /* cpuid returned max cores value: */ |
102 | u16 x86_max_cores; | |
103 | u16 apicid; | |
104 | u16 x86_clflush_size; | |
5300db88 | 105 | #ifdef CONFIG_SMP |
4d46a89e IM |
106 | /* number of cores as seen by the OS: */ |
107 | u16 booted_cores; | |
108 | /* Physical processor id: */ | |
109 | u16 phys_proc_id; | |
110 | /* Core id: */ | |
111 | u16 cpu_core_id; | |
112 | /* Index into per_cpu list: */ | |
113 | u16 cpu_index; | |
5300db88 GOC |
114 | #endif |
115 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); | |
116 | ||
4d46a89e IM |
117 | #define X86_VENDOR_INTEL 0 |
118 | #define X86_VENDOR_CYRIX 1 | |
119 | #define X86_VENDOR_AMD 2 | |
120 | #define X86_VENDOR_UMC 3 | |
121 | #define X86_VENDOR_NEXGEN 4 | |
122 | #define X86_VENDOR_CENTAUR 5 | |
123 | #define X86_VENDOR_TRANSMETA 7 | |
124 | #define X86_VENDOR_NSC 8 | |
125 | #define X86_VENDOR_NUM 9 | |
126 | ||
127 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 128 | |
1a53905a GOC |
129 | /* |
130 | * capabilities of CPUs | |
131 | */ | |
4d46a89e IM |
132 | extern struct cpuinfo_x86 boot_cpu_data; |
133 | extern struct cpuinfo_x86 new_cpu_data; | |
134 | ||
135 | extern struct tss_struct doublefault_tss; | |
136 | extern __u32 cleared_cpu_caps[NCAPINTS]; | |
5300db88 GOC |
137 | |
138 | #ifdef CONFIG_SMP | |
139 | DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info); | |
140 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) | |
141 | #define current_cpu_data cpu_data(smp_processor_id()) | |
142 | #else | |
143 | #define cpu_data(cpu) boot_cpu_data | |
144 | #define current_cpu_data boot_cpu_data | |
145 | #endif | |
146 | ||
4d46a89e IM |
147 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
148 | ||
149 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a53905a GOC |
150 | |
151 | extern void identify_cpu(struct cpuinfo_x86 *); | |
152 | extern void identify_boot_cpu(void); | |
153 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 GOC |
154 | extern void print_cpu_info(struct cpuinfo_x86 *); |
155 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); | |
156 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
157 | extern unsigned short num_cache_leaves; | |
158 | ||
1a53905a GOC |
159 | #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64) |
160 | extern void detect_ht(struct cpuinfo_x86 *c); | |
161 | #else | |
162 | static inline void detect_ht(struct cpuinfo_x86 *c) {} | |
163 | #endif | |
164 | ||
c758ecf6 | 165 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 166 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
167 | { |
168 | /* ecx is often an input as well as an output. */ | |
169 | __asm__("cpuid" | |
170 | : "=a" (*eax), | |
171 | "=b" (*ebx), | |
172 | "=c" (*ecx), | |
173 | "=d" (*edx) | |
174 | : "0" (*eax), "2" (*ecx)); | |
175 | } | |
176 | ||
c72dcf83 GOC |
177 | static inline void load_cr3(pgd_t *pgdir) |
178 | { | |
179 | write_cr3(__pa(pgdir)); | |
180 | } | |
c758ecf6 | 181 | |
ca241c75 GOC |
182 | #ifdef CONFIG_X86_32 |
183 | /* This is the TSS defined by the hardware. */ | |
184 | struct x86_hw_tss { | |
4d46a89e IM |
185 | unsigned short back_link, __blh; |
186 | unsigned long sp0; | |
187 | unsigned short ss0, __ss0h; | |
188 | unsigned long sp1; | |
189 | /* ss1 caches MSR_IA32_SYSENTER_CS: */ | |
190 | unsigned short ss1, __ss1h; | |
191 | unsigned long sp2; | |
192 | unsigned short ss2, __ss2h; | |
193 | unsigned long __cr3; | |
194 | unsigned long ip; | |
195 | unsigned long flags; | |
196 | unsigned long ax; | |
197 | unsigned long cx; | |
198 | unsigned long dx; | |
199 | unsigned long bx; | |
200 | unsigned long sp; | |
201 | unsigned long bp; | |
202 | unsigned long si; | |
203 | unsigned long di; | |
204 | unsigned short es, __esh; | |
205 | unsigned short cs, __csh; | |
206 | unsigned short ss, __ssh; | |
207 | unsigned short ds, __dsh; | |
208 | unsigned short fs, __fsh; | |
209 | unsigned short gs, __gsh; | |
210 | unsigned short ldt, __ldth; | |
211 | unsigned short trace; | |
212 | unsigned short io_bitmap_base; | |
213 | ||
ca241c75 GOC |
214 | } __attribute__((packed)); |
215 | #else | |
216 | struct x86_hw_tss { | |
4d46a89e IM |
217 | u32 reserved1; |
218 | u64 sp0; | |
219 | u64 sp1; | |
220 | u64 sp2; | |
221 | u64 reserved2; | |
222 | u64 ist[7]; | |
223 | u32 reserved3; | |
224 | u32 reserved4; | |
225 | u16 reserved5; | |
226 | u16 io_bitmap_base; | |
227 | ||
ca241c75 GOC |
228 | } __attribute__((packed)) ____cacheline_aligned; |
229 | #endif | |
230 | ||
231 | /* | |
4d46a89e | 232 | * IO-bitmap sizes: |
ca241c75 | 233 | */ |
4d46a89e IM |
234 | #define IO_BITMAP_BITS 65536 |
235 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
236 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
237 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
238 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
239 | #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 | |
ca241c75 GOC |
240 | |
241 | struct tss_struct { | |
4d46a89e IM |
242 | /* |
243 | * The hardware state: | |
244 | */ | |
245 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
246 | |
247 | /* | |
248 | * The extra 1 is there because the CPU will access an | |
249 | * additional byte beyond the end of the IO permission | |
250 | * bitmap. The extra byte must be all 1 bits, and must | |
251 | * be within the limit. | |
252 | */ | |
4d46a89e | 253 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
ca241c75 GOC |
254 | /* |
255 | * Cache the current maximum and the last task that used the bitmap: | |
256 | */ | |
4d46a89e IM |
257 | unsigned long io_bitmap_max; |
258 | struct thread_struct *io_bitmap_owner; | |
259 | ||
ca241c75 | 260 | /* |
4d46a89e | 261 | * Pad the TSS to be cacheline-aligned (size is 0x100): |
ca241c75 | 262 | */ |
4d46a89e | 263 | unsigned long __cacheline_filler[35]; |
ca241c75 | 264 | /* |
4d46a89e | 265 | * .. and then another 0x100 bytes for the emergency kernel stack: |
ca241c75 | 266 | */ |
4d46a89e IM |
267 | unsigned long stack[64]; |
268 | ||
ca241c75 GOC |
269 | } __attribute__((packed)); |
270 | ||
271 | DECLARE_PER_CPU(struct tss_struct, init_tss); | |
272 | ||
4d46a89e IM |
273 | /* |
274 | * Save the original ist values for checking stack pointers during debugging | |
275 | */ | |
1a53905a | 276 | struct orig_ist { |
4d46a89e | 277 | unsigned long ist[7]; |
1a53905a GOC |
278 | }; |
279 | ||
99f8ecdf | 280 | #define MXCSR_DEFAULT 0x1f80 |
46265df0 | 281 | |
99f8ecdf | 282 | struct i387_fsave_struct { |
4d46a89e IM |
283 | u32 cwd; |
284 | u32 swd; | |
285 | u32 twd; | |
286 | u32 fip; | |
287 | u32 fcs; | |
288 | u32 foo; | |
289 | u32 fos; | |
290 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
291 | u32 st_space[20]; | |
292 | /* Software status information: */ | |
293 | u32 status; | |
46265df0 GOC |
294 | }; |
295 | ||
46265df0 | 296 | struct i387_fxsave_struct { |
4d46a89e IM |
297 | u16 cwd; |
298 | u16 swd; | |
299 | u16 twd; | |
300 | u16 fop; | |
99f8ecdf RM |
301 | union { |
302 | struct { | |
303 | u64 rip; | |
304 | u64 rdp; | |
305 | }; | |
306 | struct { | |
307 | u32 fip; | |
308 | u32 fcs; | |
309 | u32 foo; | |
310 | u32 fos; | |
311 | }; | |
312 | }; | |
4d46a89e IM |
313 | u32 mxcsr; |
314 | u32 mxcsr_mask; | |
315 | /* 8*16 bytes for each FP-reg = 128 bytes: */ | |
316 | u32 st_space[32]; | |
317 | /* 16*16 bytes for each XMM-reg = 256 bytes: */ | |
318 | u32 xmm_space[64]; | |
319 | u32 padding[24]; | |
320 | ||
46265df0 GOC |
321 | } __attribute__((aligned(16))); |
322 | ||
99f8ecdf | 323 | struct i387_soft_struct { |
4d46a89e IM |
324 | u32 cwd; |
325 | u32 swd; | |
326 | u32 twd; | |
327 | u32 fip; | |
328 | u32 fcs; | |
329 | u32 foo; | |
330 | u32 fos; | |
331 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
332 | u32 st_space[20]; | |
333 | u8 ftop; | |
334 | u8 changed; | |
335 | u8 lookahead; | |
336 | u8 no_update; | |
337 | u8 rm; | |
338 | u8 alimit; | |
339 | struct info *info; | |
340 | u32 entry_eip; | |
99f8ecdf RM |
341 | }; |
342 | ||
46265df0 | 343 | union i387_union { |
99f8ecdf | 344 | struct i387_fsave_struct fsave; |
46265df0 | 345 | struct i387_fxsave_struct fxsave; |
4d46a89e | 346 | struct i387_soft_struct soft; |
46265df0 GOC |
347 | }; |
348 | ||
99f8ecdf | 349 | #ifdef CONFIG_X86_32 |
2f66dcc9 | 350 | DECLARE_PER_CPU(u8, cpu_llc_id); |
99f8ecdf | 351 | #else |
2f66dcc9 | 352 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
96a388de | 353 | #endif |
c758ecf6 | 354 | |
683e0253 GOC |
355 | extern void print_cpu_info(struct cpuinfo_x86 *); |
356 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); | |
357 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
358 | extern unsigned short num_cache_leaves; | |
359 | ||
cb38d377 | 360 | struct thread_struct { |
4d46a89e IM |
361 | /* Cached TLS descriptors: */ |
362 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
363 | unsigned long sp0; | |
364 | unsigned long sp; | |
cb38d377 | 365 | #ifdef CONFIG_X86_32 |
4d46a89e | 366 | unsigned long sysenter_cs; |
cb38d377 | 367 | #else |
4d46a89e IM |
368 | unsigned long usersp; /* Copy from PDA */ |
369 | unsigned short es; | |
370 | unsigned short ds; | |
371 | unsigned short fsindex; | |
372 | unsigned short gsindex; | |
cb38d377 | 373 | #endif |
4d46a89e IM |
374 | unsigned long ip; |
375 | unsigned long fs; | |
376 | unsigned long gs; | |
377 | /* Hardware debugging registers: */ | |
378 | unsigned long debugreg0; | |
379 | unsigned long debugreg1; | |
380 | unsigned long debugreg2; | |
381 | unsigned long debugreg3; | |
382 | unsigned long debugreg6; | |
383 | unsigned long debugreg7; | |
384 | /* Fault info: */ | |
385 | unsigned long cr2; | |
386 | unsigned long trap_no; | |
387 | unsigned long error_code; | |
388 | /* Floating point info: */ | |
cb38d377 GOC |
389 | union i387_union i387 __attribute__((aligned(16)));; |
390 | #ifdef CONFIG_X86_32 | |
4d46a89e | 391 | /* Virtual 86 mode info */ |
cb38d377 GOC |
392 | struct vm86_struct __user *vm86_info; |
393 | unsigned long screen_bitmap; | |
4d46a89e IM |
394 | unsigned long v86flags; |
395 | unsigned long v86mask; | |
396 | unsigned long saved_sp0; | |
397 | unsigned int saved_fs; | |
398 | unsigned int saved_gs; | |
cb38d377 | 399 | #endif |
4d46a89e IM |
400 | /* IO permissions: */ |
401 | unsigned long *io_bitmap_ptr; | |
402 | unsigned long iopl; | |
403 | /* Max allowed port in the bitmap, in bytes: */ | |
404 | unsigned io_bitmap_max; | |
cb38d377 GOC |
405 | /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ |
406 | unsigned long debugctlmsr; | |
407 | /* Debug Store - if not 0 points to a DS Save Area configuration; | |
408 | * goes into MSR_IA32_DS_AREA */ | |
409 | unsigned long ds_area_msr; | |
410 | }; | |
411 | ||
1b46cbe0 GOC |
412 | static inline unsigned long native_get_debugreg(int regno) |
413 | { | |
4d46a89e | 414 | unsigned long val = 0; /* Damn you, gcc! */ |
1b46cbe0 GOC |
415 | |
416 | switch (regno) { | |
417 | case 0: | |
418 | asm("mov %%db0, %0" :"=r" (val)); break; | |
419 | case 1: | |
420 | asm("mov %%db1, %0" :"=r" (val)); break; | |
421 | case 2: | |
422 | asm("mov %%db2, %0" :"=r" (val)); break; | |
423 | case 3: | |
424 | asm("mov %%db3, %0" :"=r" (val)); break; | |
425 | case 6: | |
426 | asm("mov %%db6, %0" :"=r" (val)); break; | |
427 | case 7: | |
428 | asm("mov %%db7, %0" :"=r" (val)); break; | |
429 | default: | |
430 | BUG(); | |
431 | } | |
432 | return val; | |
433 | } | |
434 | ||
435 | static inline void native_set_debugreg(int regno, unsigned long value) | |
436 | { | |
437 | switch (regno) { | |
438 | case 0: | |
4d46a89e | 439 | asm("mov %0, %%db0" ::"r" (value)); |
1b46cbe0 GOC |
440 | break; |
441 | case 1: | |
4d46a89e | 442 | asm("mov %0, %%db1" ::"r" (value)); |
1b46cbe0 GOC |
443 | break; |
444 | case 2: | |
4d46a89e | 445 | asm("mov %0, %%db2" ::"r" (value)); |
1b46cbe0 GOC |
446 | break; |
447 | case 3: | |
4d46a89e | 448 | asm("mov %0, %%db3" ::"r" (value)); |
1b46cbe0 GOC |
449 | break; |
450 | case 6: | |
4d46a89e | 451 | asm("mov %0, %%db6" ::"r" (value)); |
1b46cbe0 GOC |
452 | break; |
453 | case 7: | |
4d46a89e | 454 | asm("mov %0, %%db7" ::"r" (value)); |
1b46cbe0 GOC |
455 | break; |
456 | default: | |
457 | BUG(); | |
458 | } | |
459 | } | |
460 | ||
62d7d7ed GOC |
461 | /* |
462 | * Set IOPL bits in EFLAGS from given mask | |
463 | */ | |
464 | static inline void native_set_iopl_mask(unsigned mask) | |
465 | { | |
466 | #ifdef CONFIG_X86_32 | |
467 | unsigned int reg; | |
4d46a89e | 468 | |
62d7d7ed GOC |
469 | __asm__ __volatile__ ("pushfl;" |
470 | "popl %0;" | |
471 | "andl %1, %0;" | |
472 | "orl %2, %0;" | |
473 | "pushl %0;" | |
474 | "popfl" | |
475 | : "=&r" (reg) | |
476 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
477 | #endif | |
478 | } | |
479 | ||
4d46a89e IM |
480 | static inline void |
481 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
482 | { |
483 | tss->x86_tss.sp0 = thread->sp0; | |
484 | #ifdef CONFIG_X86_32 | |
4d46a89e | 485 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
486 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
487 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
488 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
489 | } | |
490 | #endif | |
491 | } | |
1b46cbe0 | 492 | |
e801f864 GOC |
493 | static inline void native_swapgs(void) |
494 | { | |
495 | #ifdef CONFIG_X86_64 | |
496 | asm volatile("swapgs" ::: "memory"); | |
497 | #endif | |
498 | } | |
499 | ||
7818a1e0 GOC |
500 | #ifdef CONFIG_PARAVIRT |
501 | #include <asm/paravirt.h> | |
502 | #else | |
4d46a89e IM |
503 | #define __cpuid native_cpuid |
504 | #define paravirt_enabled() 0 | |
1b46cbe0 GOC |
505 | |
506 | /* | |
507 | * These special macros can be used to get or set a debugging register | |
508 | */ | |
509 | #define get_debugreg(var, register) \ | |
510 | (var) = native_get_debugreg(register) | |
511 | #define set_debugreg(value, register) \ | |
512 | native_set_debugreg(register, value) | |
513 | ||
4d46a89e IM |
514 | static inline void |
515 | load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
516 | { |
517 | native_load_sp0(tss, thread); | |
518 | } | |
519 | ||
62d7d7ed | 520 | #define set_iopl_mask native_set_iopl_mask |
e801f864 | 521 | #define SWAPGS swapgs |
1b46cbe0 GOC |
522 | #endif /* CONFIG_PARAVIRT */ |
523 | ||
524 | /* | |
525 | * Save the cr4 feature set we're using (ie | |
526 | * Pentium 4MB enable and PPro Global page | |
527 | * enable), so that any CPU's that boot up | |
528 | * after us can get the correct flags. | |
529 | */ | |
4d46a89e | 530 | extern unsigned long mmu_cr4_features; |
1b46cbe0 GOC |
531 | |
532 | static inline void set_in_cr4(unsigned long mask) | |
533 | { | |
534 | unsigned cr4; | |
4d46a89e | 535 | |
1b46cbe0 GOC |
536 | mmu_cr4_features |= mask; |
537 | cr4 = read_cr4(); | |
538 | cr4 |= mask; | |
539 | write_cr4(cr4); | |
540 | } | |
541 | ||
542 | static inline void clear_in_cr4(unsigned long mask) | |
543 | { | |
544 | unsigned cr4; | |
4d46a89e | 545 | |
1b46cbe0 GOC |
546 | mmu_cr4_features &= ~mask; |
547 | cr4 = read_cr4(); | |
548 | cr4 &= ~mask; | |
549 | write_cr4(cr4); | |
550 | } | |
551 | ||
683e0253 | 552 | struct microcode_header { |
4d46a89e IM |
553 | unsigned int hdrver; |
554 | unsigned int rev; | |
555 | unsigned int date; | |
556 | unsigned int sig; | |
557 | unsigned int cksum; | |
558 | unsigned int ldrver; | |
559 | unsigned int pf; | |
560 | unsigned int datasize; | |
561 | unsigned int totalsize; | |
562 | unsigned int reserved[3]; | |
683e0253 GOC |
563 | }; |
564 | ||
565 | struct microcode { | |
4d46a89e IM |
566 | struct microcode_header hdr; |
567 | unsigned int bits[0]; | |
683e0253 GOC |
568 | }; |
569 | ||
4d46a89e IM |
570 | typedef struct microcode microcode_t; |
571 | typedef struct microcode_header microcode_header_t; | |
683e0253 GOC |
572 | |
573 | /* microcode format is extended from prescott processors */ | |
574 | struct extended_signature { | |
4d46a89e IM |
575 | unsigned int sig; |
576 | unsigned int pf; | |
577 | unsigned int cksum; | |
683e0253 GOC |
578 | }; |
579 | ||
580 | struct extended_sigtable { | |
4d46a89e IM |
581 | unsigned int count; |
582 | unsigned int cksum; | |
583 | unsigned int reserved[3]; | |
683e0253 GOC |
584 | struct extended_signature sigs[0]; |
585 | }; | |
586 | ||
fc87e906 | 587 | typedef struct { |
4d46a89e | 588 | unsigned long seg; |
fc87e906 GOC |
589 | } mm_segment_t; |
590 | ||
591 | ||
683e0253 GOC |
592 | /* |
593 | * create a kernel thread without removing it from tasklists | |
594 | */ | |
595 | extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | |
596 | ||
597 | /* Free all resources held by a thread. */ | |
598 | extern void release_thread(struct task_struct *); | |
599 | ||
4d46a89e | 600 | /* Prepare to copy thread state - unlazy all lazy state */ |
683e0253 | 601 | extern void prepare_to_copy(struct task_struct *tsk); |
1b46cbe0 | 602 | |
683e0253 | 603 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
604 | |
605 | /* | |
606 | * Generic CPUID function | |
607 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
608 | * resulting in stale register contents being returned. | |
609 | */ | |
610 | static inline void cpuid(unsigned int op, | |
611 | unsigned int *eax, unsigned int *ebx, | |
612 | unsigned int *ecx, unsigned int *edx) | |
613 | { | |
614 | *eax = op; | |
615 | *ecx = 0; | |
616 | __cpuid(eax, ebx, ecx, edx); | |
617 | } | |
618 | ||
619 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
620 | static inline void cpuid_count(unsigned int op, int count, | |
621 | unsigned int *eax, unsigned int *ebx, | |
622 | unsigned int *ecx, unsigned int *edx) | |
623 | { | |
624 | *eax = op; | |
625 | *ecx = count; | |
626 | __cpuid(eax, ebx, ecx, edx); | |
627 | } | |
628 | ||
629 | /* | |
630 | * CPUID functions returning a single datum | |
631 | */ | |
632 | static inline unsigned int cpuid_eax(unsigned int op) | |
633 | { | |
634 | unsigned int eax, ebx, ecx, edx; | |
635 | ||
636 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 637 | |
c758ecf6 GOC |
638 | return eax; |
639 | } | |
4d46a89e | 640 | |
c758ecf6 GOC |
641 | static inline unsigned int cpuid_ebx(unsigned int op) |
642 | { | |
643 | unsigned int eax, ebx, ecx, edx; | |
644 | ||
645 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 646 | |
c758ecf6 GOC |
647 | return ebx; |
648 | } | |
4d46a89e | 649 | |
c758ecf6 GOC |
650 | static inline unsigned int cpuid_ecx(unsigned int op) |
651 | { | |
652 | unsigned int eax, ebx, ecx, edx; | |
653 | ||
654 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 655 | |
c758ecf6 GOC |
656 | return ecx; |
657 | } | |
4d46a89e | 658 | |
c758ecf6 GOC |
659 | static inline unsigned int cpuid_edx(unsigned int op) |
660 | { | |
661 | unsigned int eax, ebx, ecx, edx; | |
662 | ||
663 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 664 | |
c758ecf6 GOC |
665 | return edx; |
666 | } | |
667 | ||
683e0253 GOC |
668 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
669 | static inline void rep_nop(void) | |
670 | { | |
4d46a89e | 671 | __asm__ __volatile__("rep; nop" ::: "memory"); |
683e0253 GOC |
672 | } |
673 | ||
4d46a89e IM |
674 | static inline void cpu_relax(void) |
675 | { | |
676 | rep_nop(); | |
677 | } | |
678 | ||
679 | /* Stop speculative execution: */ | |
683e0253 GOC |
680 | static inline void sync_core(void) |
681 | { | |
682 | int tmp; | |
4d46a89e | 683 | |
683e0253 GOC |
684 | asm volatile("cpuid" : "=a" (tmp) : "0" (1) |
685 | : "ebx", "ecx", "edx", "memory"); | |
686 | } | |
687 | ||
4d46a89e IM |
688 | static inline void |
689 | __monitor(const void *eax, unsigned long ecx, unsigned long edx) | |
683e0253 | 690 | { |
4d46a89e | 691 | /* "monitor %eax, %ecx, %edx;" */ |
683e0253 | 692 | asm volatile( |
4d46a89e IM |
693 | ".byte 0x0f, 0x01, 0xc8;" |
694 | :: "a" (eax), "c" (ecx), "d"(edx)); | |
683e0253 GOC |
695 | } |
696 | ||
697 | static inline void __mwait(unsigned long eax, unsigned long ecx) | |
698 | { | |
4d46a89e | 699 | /* "mwait %eax, %ecx;" */ |
683e0253 | 700 | asm volatile( |
4d46a89e IM |
701 | ".byte 0x0f, 0x01, 0xc9;" |
702 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
703 | } |
704 | ||
705 | static inline void __sti_mwait(unsigned long eax, unsigned long ecx) | |
706 | { | |
4d46a89e | 707 | /* "mwait %eax, %ecx;" */ |
683e0253 | 708 | asm volatile( |
4d46a89e IM |
709 | "sti; .byte 0x0f, 0x01, 0xc9;" |
710 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
711 | } |
712 | ||
713 | extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); | |
714 | ||
4d46a89e | 715 | extern int force_mwait; |
683e0253 GOC |
716 | |
717 | extern void select_idle_routine(const struct cpuinfo_x86 *c); | |
718 | ||
4d46a89e | 719 | extern unsigned long boot_option_idle_override; |
683e0253 | 720 | |
1a53905a GOC |
721 | extern void enable_sep_cpu(void); |
722 | extern int sysenter_setup(void); | |
723 | ||
724 | /* Defined in head.S */ | |
4d46a89e | 725 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
726 | |
727 | extern void cpu_set_gdt(int); | |
728 | extern void switch_to_new_gdt(void); | |
729 | extern void cpu_init(void); | |
730 | extern void init_gdt(int cpu); | |
731 | ||
4d46a89e IM |
732 | /* |
733 | * from system description table in BIOS. Mostly for MCA use, but | |
734 | * others may find it useful: | |
735 | */ | |
736 | extern unsigned int machine_id; | |
737 | extern unsigned int machine_submodel_id; | |
738 | extern unsigned int BIOS_revision; | |
1a53905a | 739 | |
4d46a89e IM |
740 | /* Boot loader type from the setup header: */ |
741 | extern int bootloader_type; | |
1a53905a | 742 | |
4d46a89e | 743 | extern char ignore_fpu_irq; |
683e0253 GOC |
744 | |
745 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
746 | #define ARCH_HAS_PREFETCHW | |
747 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
748 | ||
ae2e15eb | 749 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
750 | # define BASE_PREFETCH ASM_NOP4 |
751 | # define ARCH_HAS_PREFETCH | |
ae2e15eb | 752 | #else |
4d46a89e | 753 | # define BASE_PREFETCH "prefetcht0 (%1)" |
ae2e15eb GOC |
754 | #endif |
755 | ||
4d46a89e IM |
756 | /* |
757 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
758 | * | |
759 | * It's not worth to care about 3dnow prefetches for the K6 | |
760 | * because they are microcoded there and very slow. | |
761 | */ | |
ae2e15eb GOC |
762 | static inline void prefetch(const void *x) |
763 | { | |
764 | alternative_input(BASE_PREFETCH, | |
765 | "prefetchnta (%1)", | |
766 | X86_FEATURE_XMM, | |
767 | "r" (x)); | |
768 | } | |
769 | ||
4d46a89e IM |
770 | /* |
771 | * 3dnow prefetch to get an exclusive cache line. | |
772 | * Useful for spinlocks to avoid one state transition in the | |
773 | * cache coherency protocol: | |
774 | */ | |
ae2e15eb GOC |
775 | static inline void prefetchw(const void *x) |
776 | { | |
777 | alternative_input(BASE_PREFETCH, | |
778 | "prefetchw (%1)", | |
779 | X86_FEATURE_3DNOW, | |
780 | "r" (x)); | |
781 | } | |
782 | ||
4d46a89e IM |
783 | static inline void spin_lock_prefetch(const void *x) |
784 | { | |
785 | prefetchw(x); | |
786 | } | |
787 | ||
2f66dcc9 GOC |
788 | #ifdef CONFIG_X86_32 |
789 | /* | |
790 | * User space process size: 3GB (default). | |
791 | */ | |
4d46a89e IM |
792 | #define TASK_SIZE PAGE_OFFSET |
793 | #define STACK_TOP TASK_SIZE | |
794 | #define STACK_TOP_MAX STACK_TOP | |
795 | ||
796 | #define INIT_THREAD { \ | |
797 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ | |
798 | .vm86_info = NULL, \ | |
799 | .sysenter_cs = __KERNEL_CS, \ | |
800 | .io_bitmap_ptr = NULL, \ | |
801 | .fs = __KERNEL_PERCPU, \ | |
2f66dcc9 GOC |
802 | } |
803 | ||
804 | /* | |
805 | * Note that the .io_bitmap member must be extra-big. This is because | |
806 | * the CPU will access an additional byte beyond the end of the IO | |
807 | * permission bitmap. The extra byte must be all 1 bits, and must | |
808 | * be within the limit. | |
809 | */ | |
4d46a89e IM |
810 | #define INIT_TSS { \ |
811 | .x86_tss = { \ | |
2f66dcc9 | 812 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ |
4d46a89e IM |
813 | .ss0 = __KERNEL_DS, \ |
814 | .ss1 = __KERNEL_CS, \ | |
815 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ | |
816 | }, \ | |
817 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ | |
2f66dcc9 GOC |
818 | } |
819 | ||
4d46a89e IM |
820 | #define start_thread(regs, new_eip, new_esp) \ |
821 | do { \ | |
2f66dcc9 | 822 | __asm__("movl %0,%%gs": :"r" (0)); \ |
4d46a89e | 823 | regs->fs = 0; \ |
2f66dcc9 | 824 | set_fs(USER_DS); \ |
4d46a89e IM |
825 | regs->ds = __USER_DS; \ |
826 | regs->es = __USER_DS; \ | |
827 | regs->ss = __USER_DS; \ | |
828 | regs->cs = __USER_CS; \ | |
829 | regs->ip = new_eip; \ | |
830 | regs->sp = new_esp; \ | |
2f66dcc9 GOC |
831 | } while (0) |
832 | ||
833 | ||
834 | extern unsigned long thread_saved_pc(struct task_struct *tsk); | |
835 | ||
836 | #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) | |
837 | #define KSTK_TOP(info) \ | |
838 | ({ \ | |
839 | unsigned long *__ptr = (unsigned long *)(info); \ | |
840 | (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ | |
841 | }) | |
842 | ||
843 | /* | |
844 | * The below -8 is to reserve 8 bytes on top of the ring0 stack. | |
845 | * This is necessary to guarantee that the entire "struct pt_regs" | |
846 | * is accessable even if the CPU haven't stored the SS/ESP registers | |
847 | * on the stack (interrupt gate does not save these registers | |
848 | * when switching to the same priv ring). | |
849 | * Therefore beware: accessing the ss/esp fields of the | |
850 | * "struct pt_regs" is possible, but they may contain the | |
851 | * completely wrong values. | |
852 | */ | |
853 | #define task_pt_regs(task) \ | |
854 | ({ \ | |
855 | struct pt_regs *__regs__; \ | |
856 | __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ | |
857 | __regs__ - 1; \ | |
858 | }) | |
859 | ||
4d46a89e | 860 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
861 | |
862 | #else | |
863 | /* | |
864 | * User space process size. 47bits minus one guard page. | |
865 | */ | |
4d46a89e | 866 | #define TASK_SIZE64 (0x800000000000UL - 4096) |
2f66dcc9 GOC |
867 | |
868 | /* This decides where the kernel will search for a free chunk of vm | |
869 | * space during mmap's. | |
870 | */ | |
4d46a89e IM |
871 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
872 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 873 | |
4d46a89e IM |
874 | #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ |
875 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
876 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ | |
877 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
2f66dcc9 | 878 | |
922a70d3 DH |
879 | #define STACK_TOP TASK_SIZE |
880 | #define STACK_TOP_MAX TASK_SIZE64 | |
881 | ||
2f66dcc9 GOC |
882 | #define INIT_THREAD { \ |
883 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
884 | } | |
885 | ||
886 | #define INIT_TSS { \ | |
887 | .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
888 | } | |
889 | ||
890 | #define start_thread(regs, new_rip, new_rsp) do { \ | |
891 | asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \ | |
892 | load_gs_index(0); \ | |
4d46a89e IM |
893 | (regs)->ip = (new_rip); \ |
894 | (regs)->sp = (new_rsp); \ | |
2f66dcc9 | 895 | write_pda(oldrsp, (new_rsp)); \ |
4d46a89e IM |
896 | (regs)->cs = __USER_CS; \ |
897 | (regs)->ss = __USER_DS; \ | |
898 | (regs)->flags = 0x200; \ | |
2f66dcc9 GOC |
899 | set_fs(USER_DS); \ |
900 | } while (0) | |
901 | ||
902 | /* | |
903 | * Return saved PC of a blocked thread. | |
904 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
905 | */ | |
4d46a89e | 906 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
2f66dcc9 | 907 | |
4d46a89e IM |
908 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
909 | #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ | |
2f66dcc9 GOC |
910 | #endif /* CONFIG_X86_64 */ |
911 | ||
4d46a89e IM |
912 | /* |
913 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
914 | * space during mmap's. |
915 | */ | |
916 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
917 | ||
4d46a89e | 918 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 919 | |
c758ecf6 | 920 | #endif |