[deliverable/linux.git] / include / asm-x86 / processor_64.h

/*
 * Copyright (C) 1994 Linus Torvalds
 */

#ifndef __ASM_X86_64_PROCESSOR_H
#define __ASM_X86_64_PROCESSOR_H

#include <asm/segment.h>
#include <asm/page.h>
#include <asm/types.h>
#include <asm/sigcontext.h>
#include <asm/cpufeature.h>
#include <linux/threads.h>
#include <asm/msr.h>
#include <asm/current.h>
#include <asm/system.h>
#include <asm/mmsegment.h>
#include <asm/percpu.h>
#include <linux/personality.h>
#include <linux/cpumask.h>
#include <asm/processor-flags.h>

#define TF_MASK		0x00000100
#define IF_MASK		0x00000200
#define IOPL_MASK	0x00003000
#define NT_MASK		0x00004000
#define VM_MASK		0x00020000
#define AC_MASK		0x00040000
#define VIF_MASK	0x00080000	/* virtual interrupt flag */
#define VIP_MASK	0x00100000	/* virtual interrupt pending */
#define ID_MASK		0x00200000

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;
	return !(desc[0] | desc[1]);
}

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })

/*
 *  CPU type and hardware bug flags. Kept separately for each CPU.
 */

struct cpuinfo_x86 {
	__u8	x86;		/* CPU family */
	__u8	x86_vendor;	/* CPU vendor */
	__u8	x86_model;
	__u8	x86_mask;
	int	cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID */
	__u32	x86_capability[NCAPINTS];
	char	x86_vendor_id[16];
	char	x86_model_id[64];
	int 	x86_cache_size;  /* in KB */
	int	x86_clflush_size;
	int	x86_cache_alignment;
	int	x86_tlbsize;	/* number of 4K pages in DTLB/ITLB combined(in pages)*/
        __u8    x86_virt_bits, x86_phys_bits;
	__u8	x86_max_cores;	/* cpuid returned max cores value */
	__u8	x86_coreid_bits; /* cpuid returned core id bits */
        __u32   x86_power; 	
	__u32   extended_cpuid_level;	/* Max extended CPUID function supported */
	unsigned long loops_per_jiffy;
#ifdef CONFIG_SMP
	cpumask_t llc_shared_map;	/* cpus sharing the last level cache */
#endif
	__u8	apicid;
#ifdef CONFIG_SMP
	__u8	booted_cores;	/* number of cores as seen by OS */
	__u8	phys_proc_id;	/* Physical Processor id. */
	__u8	cpu_core_id;	/* Core id. */
	__u8	cpu_index;	/* index into per_cpu list */
#endif
} ____cacheline_aligned;

#define X86_VENDOR_INTEL 0
#define X86_VENDOR_CYRIX 1
#define X86_VENDOR_AMD 2
#define X86_VENDOR_UMC 3
#define X86_VENDOR_NEXGEN 4
#define X86_VENDOR_CENTAUR 5
#define X86_VENDOR_TRANSMETA 7
#define X86_VENDOR_NUM 8
#define X86_VENDOR_UNKNOWN 0xff

#ifdef CONFIG_SMP
DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
#define cpu_data(cpu)		per_cpu(cpu_info, cpu)
#define current_cpu_data	cpu_data(smp_processor_id())
#else
#define cpu_data(cpu)		boot_cpu_data
#define current_cpu_data	boot_cpu_data
#endif

extern char ignore_irq13;

extern void identify_cpu(struct cpuinfo_x86 *);
extern void print_cpu_info(struct cpuinfo_x86 *);
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
extern unsigned short num_cache_leaves;

/*
 * Save the cr4 feature set we're using (ie
 * Pentium 4MB enable and PPro Global page
 * enable), so that any CPU's that boot up
 * after us can get the correct flags.
 */
extern unsigned long mmu_cr4_features;

static inline void set_in_cr4 (unsigned long mask)
{
	mmu_cr4_features |= mask;
	__asm__("movq %%cr4,%%rax\n\t"
		"orq %0,%%rax\n\t"
		"movq %%rax,%%cr4\n"
		: : "irg" (mask)
		:"ax");
}

static inline void clear_in_cr4 (unsigned long mask)
{
	mmu_cr4_features &= ~mask;
	__asm__("movq %%cr4,%%rax\n\t"
		"andq %0,%%rax\n\t"
		"movq %%rax,%%cr4\n"
		: : "irg" (~mask)
		:"ax");
}


/*
 * User space process size. 47bits minus one guard page.
 */
#define TASK_SIZE64	(0x800000000000UL - 4096)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)

#define TASK_SIZE 		(test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
#define TASK_SIZE_OF(child) 	((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)

#define TASK_UNMAPPED_BASE	PAGE_ALIGN(TASK_SIZE/3)

/*
 * Size of io_bitmap.
 */
#define IO_BITMAP_BITS  65536
#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
#define INVALID_IO_BITMAP_OFFSET 0x8000

struct i387_fxsave_struct {
	u16	cwd;
	u16	swd;
	u16	twd;
	u16	fop;
	u64	rip;
	u64	rdp; 
	u32	mxcsr;
	u32	mxcsr_mask;
	u32	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
	u32	xmm_space[64];	/* 16*16 bytes for each XMM-reg = 256 bytes */
	u32	padding[24];
} __attribute__ ((aligned (16)));

union i387_union {
	struct i387_fxsave_struct	fxsave;
};

struct tss_struct {
	u32 reserved1;
	u64 sp0;
	u64 sp1;
	u64 sp2;
	u64 reserved2;
	u64 ist[7];
	u32 reserved3;
	u32 reserved4;
	u16 reserved5;
	u16 io_bitmap_base;
	/*
	 * The extra 1 is there because the CPU will access an
	 * additional byte beyond the end of the IO permission
	 * bitmap. The extra byte must be all 1 bits, and must
	 * be within the limit. Thus we have:
	 *
	 * 128 bytes, the bitmap itself, for ports 0..0x3ff
	 * 8 bytes, for an extra "long" of ~0UL
	 */
	unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
} __attribute__((packed)) ____cacheline_aligned;


extern struct cpuinfo_x86 boot_cpu_data;
DECLARE_PER_CPU(struct tss_struct,init_tss);
/* Save the original ist values for checking stack pointers during debugging */
struct orig_ist {
	unsigned long ist[7];
};
DECLARE_PER_CPU(struct orig_ist, orig_ist);

#ifdef CONFIG_X86_VSMP
#define ARCH_MIN_TASKALIGN	(1 << INTERNODE_CACHE_SHIFT)
#define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)
#else
#define ARCH_MIN_TASKALIGN	16
#define ARCH_MIN_MMSTRUCT_ALIGN	0
#endif

struct thread_struct {
	unsigned long	sp0;
	unsigned long	sp;
	unsigned long 	usersp;	/* Copy from PDA */
	unsigned long	fs;
	unsigned long	gs;
	unsigned short	es, ds, fsindex, gsindex;	
/* Hardware debugging registers */
	unsigned long	debugreg0;  
	unsigned long	debugreg1;  
	unsigned long	debugreg2;  
	unsigned long	debugreg3;  
	unsigned long	debugreg6;  
	unsigned long	debugreg7;  
/* fault info */
	unsigned long	cr2, trap_no, error_code;
/* floating point info */
	union i387_union	i387  __attribute__((aligned(16)));
/* IO permissions. the bitmap could be moved into the GDT, that would make
   switch faster for a limited number of ioperm using tasks. -AK */
	int		ioperm;
	unsigned long	*io_bitmap_ptr;
	unsigned io_bitmap_max;
/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
	unsigned long	debugctlmsr;
/* Debug Store - if not 0 points to a DS Save Area configuration;
 *               goes into MSR_IA32_DS_AREA */
	unsigned long	ds_area_msr;
/* cached TLS descriptors. */
	u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
} __attribute__((aligned(16)));

#define INIT_THREAD  { \
	.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
}

#define INIT_TSS  { \
	.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
}

#define INIT_MMAP \
{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }

#define start_thread(regs,new_rip,new_rsp) do { \
	asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));	 \
	load_gs_index(0);							\
	(regs)->ip = (new_rip);						 \
	(regs)->sp = (new_rsp);						 \
	write_pda(oldrsp, (new_rsp));						 \
	(regs)->cs = __USER_CS;							 \
	(regs)->ss = __USER_DS;							 \
	(regs)->flags = 0x200;							 \
	set_fs(USER_DS);							 \
} while(0) 

#define get_debugreg(var, register)				\
		__asm__("movq %%db" #register ", %0"		\
			:"=r" (var))
#define set_debugreg(value, register)			\
		__asm__("movq %0,%%db" #register		\
			: /* no output */			\
			:"r" (value))

struct task_struct;
struct mm_struct;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/* Prepare to copy thread state - unlazy all lazy status */
extern void prepare_to_copy(struct task_struct *tsk);

/*
 * create a kernel thread without removing it from tasklists
 */
extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);

/*
 * Return saved PC of a blocked thread.
 * What is this good for? it will be always the scheduler or ret_from_fork.
 */
#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))

extern unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ip)
#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */


struct microcode_header {
	unsigned int hdrver;
	unsigned int rev;
	unsigned int date;
	unsigned int sig;
	unsigned int cksum;
	unsigned int ldrver;
	unsigned int pf;
	unsigned int datasize;
	unsigned int totalsize;
	unsigned int reserved[3];
};

struct microcode {
	struct microcode_header hdr;
	unsigned int bits[0];
};

typedef struct microcode microcode_t;
typedef struct microcode_header microcode_header_t;

/* microcode format is extended from prescott processors */
struct extended_signature {
	unsigned int sig;
	unsigned int pf;
	unsigned int cksum;
};

struct extended_sigtable {
	unsigned int count;
	unsigned int cksum;
	unsigned int reserved[3];
	struct extended_signature sigs[0];
};


#if defined(CONFIG_MPSC) || defined(CONFIG_MCORE2)
#define ASM_NOP1 P6_NOP1
#define ASM_NOP2 P6_NOP2
#define ASM_NOP3 P6_NOP3
#define ASM_NOP4 P6_NOP4
#define ASM_NOP5 P6_NOP5
#define ASM_NOP6 P6_NOP6
#define ASM_NOP7 P6_NOP7
#define ASM_NOP8 P6_NOP8
#else
#define ASM_NOP1 K8_NOP1
#define ASM_NOP2 K8_NOP2
#define ASM_NOP3 K8_NOP3
#define ASM_NOP4 K8_NOP4
#define ASM_NOP5 K8_NOP5
#define ASM_NOP6 K8_NOP6
#define ASM_NOP7 K8_NOP7
#define ASM_NOP8 K8_NOP8
#endif

/* Opteron nops */
#define K8_NOP1 ".byte 0x90\n"
#define K8_NOP2	".byte 0x66,0x90\n" 
#define K8_NOP3	".byte 0x66,0x66,0x90\n" 
#define K8_NOP4	".byte 0x66,0x66,0x66,0x90\n" 
#define K8_NOP5	K8_NOP3 K8_NOP2 
#define K8_NOP6	K8_NOP3 K8_NOP3
#define K8_NOP7	K8_NOP4 K8_NOP3
#define K8_NOP8	K8_NOP4 K8_NOP4

/* P6 nops */
/* uses eax dependencies (Intel-recommended choice) */
#define P6_NOP1	".byte 0x90\n"
#define P6_NOP2	".byte 0x66,0x90\n"
#define P6_NOP3	".byte 0x0f,0x1f,0x00\n"
#define P6_NOP4	".byte 0x0f,0x1f,0x40,0\n"
#define P6_NOP5	".byte 0x0f,0x1f,0x44,0x00,0\n"
#define P6_NOP6	".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
#define P6_NOP7	".byte 0x0f,0x1f,0x80,0,0,0,0\n"
#define P6_NOP8	".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"

#define ASM_NOP_MAX 8

/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
static inline void rep_nop(void)
{
	__asm__ __volatile__("rep;nop": : :"memory");
}

/* Stop speculative execution */
static inline void sync_core(void)
{ 
	int tmp;
	asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
} 

#define ARCH_HAS_PREFETCHW 1
static inline void prefetchw(void *x) 
{ 
	alternative_input("prefetcht0 (%1)",
			  "prefetchw (%1)",
			  X86_FEATURE_3DNOW,
			  "r" (x));
} 

#define ARCH_HAS_SPINLOCK_PREFETCH 1

#define spin_lock_prefetch(x)  prefetchw(x)

#define cpu_relax()   rep_nop()

static inline void __monitor(const void *eax, unsigned long ecx,
		unsigned long edx)
{
	/* "monitor %eax,%ecx,%edx;" */
	asm volatile(
		".byte 0x0f,0x01,0xc8;"
		: :"a" (eax), "c" (ecx), "d"(edx));
}

static inline void __mwait(unsigned long eax, unsigned long ecx)
{
	/* "mwait %eax,%ecx;" */
	asm volatile(
		".byte 0x0f,0x01,0xc9;"
		: :"a" (eax), "c" (ecx));
}

static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
{
	/* "mwait %eax,%ecx;" */
	asm volatile(
		"sti; .byte 0x0f,0x01,0xc9;"
		: :"a" (eax), "c" (ecx));
}

extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);

extern int force_mwait;

extern void select_idle_routine(const struct cpuinfo_x86 *c);

#define stack_current() \
({								\
	struct thread_info *ti;					\
	asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK));	\
	ti->task;					\
})

#define cache_line_size() (boot_cpu_data.x86_cache_alignment)

extern unsigned long boot_option_idle_override;
/* Boot loader type from the setup header */
extern int bootloader_type;

#define HAVE_ARCH_PICK_MMAP_LAYOUT 1

#endif /* __ASM_X86_64_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1994 Linus Torvalds
	3	*/
	4
	5	#ifndef __ASM_X86_64_PROCESSOR_H
	6	#define __ASM_X86_64_PROCESSOR_H
	7
	8	#include <asm/segment.h>
	9	#include <asm/page.h>
	10	#include <asm/types.h>
	11	#include <asm/sigcontext.h>
	12	#include <asm/cpufeature.h>
1da177e4 LT	13	#include <linux/threads.h>
	14	#include <asm/msr.h>
	15	#include <asm/current.h>
	16	#include <asm/system.h>
	17	#include <asm/mmsegment.h>
	18	#include <asm/percpu.h>
	19	#include <linux/personality.h>
1e9f28fa	20	#include <linux/cpumask.h>
5d02d7ae	21	#include <asm/processor-flags.h>
1da177e4 LT	22
	23	#define TF_MASK 0x00000100
	24	#define IF_MASK 0x00000200
	25	#define IOPL_MASK 0x00003000
	26	#define NT_MASK 0x00004000
	27	#define VM_MASK 0x00020000
	28	#define AC_MASK 0x00040000
	29	#define VIF_MASK 0x00080000 /* virtual interrupt flag */
	30	#define VIP_MASK 0x00100000 /* virtual interrupt pending */
	31	#define ID_MASK 0x00200000
	32
12c3cbbb RM	33	static inline int desc_empty(const void *ptr)
	34	{
	35	const u32 *desc = ptr;
	36	return !(desc[0] \| desc[1]);
	37	}
1da177e4 LT	38
	39	/*
	40	* Default implementation of macro that returns current
	41	* instruction pointer ("program counter").
	42	*/
	43	#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
	44
	45	/*
	46	* CPU type and hardware bug flags. Kept separately for each CPU.
	47	*/
	48
	49	struct cpuinfo_x86 {
	50	__u8 x86; /* CPU family */
	51	__u8 x86_vendor; /* CPU vendor */
	52	__u8 x86_model;
	53	__u8 x86_mask;
	54	int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
	55	__u32 x86_capability[NCAPINTS];
	56	char x86_vendor_id[16];
	57	char x86_model_id[64];
	58	int x86_cache_size; /* in KB */
	59	int x86_clflush_size;
	60	int x86_cache_alignment;
	61	int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
	62	__u8 x86_virt_bits, x86_phys_bits;
94605eff	63	__u8 x86_max_cores; /* cpuid returned max cores value */
a860b63c	64	__u8 x86_coreid_bits; /* cpuid returned core id bits */
1da177e4	65	__u32 x86_power;
ebfcaa96	66	__u32 extended_cpuid_level; /* Max extended CPUID function supported */
1da177e4	67	unsigned long loops_per_jiffy;
1e9f28fa SS	68	#ifdef CONFIG_SMP
	69	cpumask_t llc_shared_map; /* cpus sharing the last level cache */
	70	#endif
94605eff	71	__u8 apicid;
f3fa8ebc	72	#ifdef CONFIG_SMP
94605eff	73	__u8 booted_cores; /* number of cores as seen by OS */
f3fa8ebc RS	74	__u8 phys_proc_id; /* Physical Processor id. */
f3fa8ebc RS	75	__u8 cpu_core_id; /* Core id. */
92cb7612	76	__u8 cpu_index; /* index into per_cpu list */
f3fa8ebc	77	#endif
1da177e4 LT	78	} ____cacheline_aligned;
	79
	80	#define X86_VENDOR_INTEL 0
	81	#define X86_VENDOR_CYRIX 1
	82	#define X86_VENDOR_AMD 2
	83	#define X86_VENDOR_UMC 3
	84	#define X86_VENDOR_NEXGEN 4
	85	#define X86_VENDOR_CENTAUR 5
1da177e4 LT	86	#define X86_VENDOR_TRANSMETA 7
	87	#define X86_VENDOR_NUM 8
	88	#define X86_VENDOR_UNKNOWN 0xff
	89
	90	#ifdef CONFIG_SMP
92cb7612 MT	91	DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
	92	#define cpu_data(cpu) per_cpu(cpu_info, cpu)
	93	#define current_cpu_data cpu_data(smp_processor_id())
1da177e4	94	#else
92cb7612 MT	95	#define cpu_data(cpu) boot_cpu_data
92cb7612 MT	96	#define current_cpu_data boot_cpu_data
1da177e4 LT	97	#endif
	98
	99	extern char ignore_irq13;
	100
	101	extern void identify_cpu(struct cpuinfo_x86 *);
	102	extern void print_cpu_info(struct cpuinfo_x86 *);
1d67953f	103	extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
1da177e4	104	extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
240cd6a8	105	extern unsigned short num_cache_leaves;
1da177e4	106
1da177e4 LT	107	/*
	108	* Save the cr4 feature set we're using (ie
	109	* Pentium 4MB enable and PPro Global page
	110	* enable), so that any CPU's that boot up
	111	* after us can get the correct flags.
	112	*/
	113	extern unsigned long mmu_cr4_features;
	114
	115	static inline void set_in_cr4 (unsigned long mask)
	116	{
	117	mmu_cr4_features \|= mask;
	118	__asm__("movq %%cr4,%%rax\n\t"
	119	"orq %0,%%rax\n\t"
	120	"movq %%rax,%%cr4\n"
	121	: : "irg" (mask)
	122	:"ax");
	123	}
	124
	125	static inline void clear_in_cr4 (unsigned long mask)
	126	{
	127	mmu_cr4_features &= ~mask;
	128	__asm__("movq %%cr4,%%rax\n\t"
	129	"andq %0,%%rax\n\t"
	130	"movq %%rax,%%cr4\n"
	131	: : "irg" (~mask)
	132	:"ax");
	133	}
	134
	135
	136	/*
637716a3	137	* User space process size. 47bits minus one guard page.
1da177e4	138	*/
84929801	139	#define TASK_SIZE64 (0x800000000000UL - 4096)
1da177e4 LT	140
	141	/* This decides where the kernel will search for a free chunk of vm
	142	* space during mmap's.
	143	*/
	144	#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
84929801 SS	145
	146	#define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
	147	#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
	148
	149	#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
1da177e4 LT	150
	151	/*
	152	* Size of io_bitmap.
	153	*/
	154	#define IO_BITMAP_BITS 65536
	155	#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
	156	#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
	157	#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
	158	#define INVALID_IO_BITMAP_OFFSET 0x8000
	159
	160	struct i387_fxsave_struct {
	161	u16 cwd;
	162	u16 swd;
	163	u16 twd;
	164	u16 fop;
	165	u64 rip;
	166	u64 rdp;
	167	u32 mxcsr;
	168	u32 mxcsr_mask;
	169	u32 st_space[32]; /* 816 bytes for each FP-reg = 128 bytes /
bbf30a16	170	u32 xmm_space[64]; /* 1616 bytes for each XMM-reg = 256 bytes /
1da177e4 LT	171	u32 padding[24];
	172	} __attribute__ ((aligned (16)));
	173
	174	union i387_union {
	175	struct i387_fxsave_struct fxsave;
	176	};
	177
	178	struct tss_struct {
	179	u32 reserved1;
faca6227 PA	180	u64 sp0;
	181	u64 sp1;
	182	u64 sp2;
1da177e4 LT	183	u64 reserved2;
	184	u64 ist[7];
	185	u32 reserved3;
	186	u32 reserved4;
	187	u16 reserved5;
	188	u16 io_bitmap_base;
	189	/*
	190	* The extra 1 is there because the CPU will access an
	191	* additional byte beyond the end of the IO permission
	192	* bitmap. The extra byte must be all 1 bits, and must
	193	* be within the limit. Thus we have:
	194	*
	195	* 128 bytes, the bitmap itself, for ports 0..0x3ff
	196	* 8 bytes, for an extra "long" of ~0UL
	197	*/
	198	unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
	199	} __attribute__((packed)) ____cacheline_aligned;
	200
01ebb77b	201
1da177e4 LT	202	extern struct cpuinfo_x86 boot_cpu_data;
1da177e4 LT	203	DECLARE_PER_CPU(struct tss_struct,init_tss);
01ebb77b KO	204	/* Save the original ist values for checking stack pointers during debugging */
	205	struct orig_ist {
	206	unsigned long ist[7];
	207	};
	208	DECLARE_PER_CPU(struct orig_ist, orig_ist);
1da177e4	209
5fd63b30 RT	210	#ifdef CONFIG_X86_VSMP
	211	#define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
	212	#define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
	213	#else
1da177e4	214	#define ARCH_MIN_TASKALIGN 16
5fd63b30 RT	215	#define ARCH_MIN_MMSTRUCT_ALIGN 0
5fd63b30 RT	216	#endif
1da177e4 LT	217
1da177e4 LT	218	struct thread_struct {
faca6227 PA	219	unsigned long sp0;
	220	unsigned long sp;
	221	unsigned long usersp; /* Copy from PDA */
1da177e4 LT	222	unsigned long fs;
	223	unsigned long gs;
	224	unsigned short es, ds, fsindex, gsindex;
	225	/* Hardware debugging registers */
	226	unsigned long debugreg0;
	227	unsigned long debugreg1;
	228	unsigned long debugreg2;
	229	unsigned long debugreg3;
	230	unsigned long debugreg6;
	231	unsigned long debugreg7;
	232	/* fault info */
	233	unsigned long cr2, trap_no, error_code;
	234	/* floating point info */
	235	union i387_union i387 __attribute__((aligned(16)));
	236	/* IO permissions. the bitmap could be moved into the GDT, that would make
	237	switch faster for a limited number of ioperm using tasks. -AK */
	238	int ioperm;
	239	unsigned long *io_bitmap_ptr;
	240	unsigned io_bitmap_max;
7e991604 RM	241	/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
7e991604 RM	242	unsigned long debugctlmsr;
eee3af4a MM	243	/* Debug Store - if not 0 points to a DS Save Area configuration;
	244	* goes into MSR_IA32_DS_AREA */
	245	unsigned long ds_area_msr;
1da177e4 LT	246	/* cached TLS descriptors. */
	247	u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
	248	} __attribute__((aligned(16)));
	249
a0d58c97	250	#define INIT_THREAD { \
faca6227	251	.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
a0d58c97 AK	252	}
	253
	254	#define INIT_TSS { \
faca6227	255	.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
a0d58c97	256	}
1da177e4 LT	257
	258	#define INIT_MMAP \
	259	{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ \| VM_WRITE \| VM_EXEC, 1, NULL, NULL }
	260
1da177e4 LT	261	#define start_thread(regs,new_rip,new_rsp) do { \
	262	asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
	263	load_gs_index(0); \
65ea5b03 PA	264	(regs)->ip = (new_rip); \
65ea5b03 PA	265	(regs)->sp = (new_rsp); \
1da177e4 LT	266	write_pda(oldrsp, (new_rsp)); \
	267	(regs)->cs = __USER_CS; \
	268	(regs)->ss = __USER_DS; \
65ea5b03	269	(regs)->flags = 0x200; \
1da177e4 LT	270	set_fs(USER_DS); \
	271	} while(0)
	272
e9129e56 VH	273	#define get_debugreg(var, register) \
	274	__asm__("movq %%db" #register ", %0" \
	275	:"=r" (var))
	276	#define set_debugreg(value, register) \
	277	__asm__("movq %0,%%db" #register \
	278	: /* no output */ \
	279	:"r" (value))
	280
1da177e4 LT	281	struct task_struct;
	282	struct mm_struct;
	283
	284	/* Free all resources held by a thread. */
	285	extern void release_thread(struct task_struct *);
	286
	287	/* Prepare to copy thread state - unlazy all lazy status */
	288	extern void prepare_to_copy(struct task_struct *tsk);
	289
	290	/*
	291	* create a kernel thread without removing it from tasklists
	292	*/
	293	extern long kernel_thread(int (fn)(void ), void * arg, unsigned long flags);
	294
	295	/*
	296	* Return saved PC of a blocked thread.
	297	* What is this good for? it will be always the scheduler or ret_from_fork.
	298	*/
faca6227	299	#define thread_saved_pc(t) ((unsigned long )((t)->thread.sp - 8))
1da177e4 LT	300
1da177e4 LT	301	extern unsigned long get_wchan(struct task_struct *p);
faca6227	302	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
65ea5b03	303	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ip)
1da177e4 LT	304	#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
	305
	306
	307	struct microcode_header {
	308	unsigned int hdrver;
	309	unsigned int rev;
	310	unsigned int date;
	311	unsigned int sig;
	312	unsigned int cksum;
	313	unsigned int ldrver;
	314	unsigned int pf;
	315	unsigned int datasize;
	316	unsigned int totalsize;
	317	unsigned int reserved[3];
	318	};
	319
	320	struct microcode {
	321	struct microcode_header hdr;
	322	unsigned int bits[0];
	323	};
	324
	325	typedef struct microcode microcode_t;
	326	typedef struct microcode_header microcode_header_t;
	327
	328	/* microcode format is extended from prescott processors */
	329	struct extended_signature {
	330	unsigned int sig;
	331	unsigned int pf;
	332	unsigned int cksum;
	333	};
	334
	335	struct extended_sigtable {
	336	unsigned int count;
	337	unsigned int cksum;
	338	unsigned int reserved[3];
	339	struct extended_signature sigs[0];
	340	};
	341
1da177e4	342
32c464f5 JB	343	#if defined(CONFIG_MPSC) \|\| defined(CONFIG_MCORE2)
	344	#define ASM_NOP1 P6_NOP1
	345	#define ASM_NOP2 P6_NOP2
	346	#define ASM_NOP3 P6_NOP3
	347	#define ASM_NOP4 P6_NOP4
	348	#define ASM_NOP5 P6_NOP5
	349	#define ASM_NOP6 P6_NOP6
	350	#define ASM_NOP7 P6_NOP7
	351	#define ASM_NOP8 P6_NOP8
	352	#else
1da177e4 LT	353	#define ASM_NOP1 K8_NOP1
	354	#define ASM_NOP2 K8_NOP2
	355	#define ASM_NOP3 K8_NOP3
	356	#define ASM_NOP4 K8_NOP4
	357	#define ASM_NOP5 K8_NOP5
	358	#define ASM_NOP6 K8_NOP6
	359	#define ASM_NOP7 K8_NOP7
	360	#define ASM_NOP8 K8_NOP8
32c464f5	361	#endif
1da177e4 LT	362
	363	/* Opteron nops */
	364	#define K8_NOP1 ".byte 0x90\n"
	365	#define K8_NOP2 ".byte 0x66,0x90\n"
	366	#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
	367	#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
	368	#define K8_NOP5 K8_NOP3 K8_NOP2
	369	#define K8_NOP6 K8_NOP3 K8_NOP3
	370	#define K8_NOP7 K8_NOP4 K8_NOP3
	371	#define K8_NOP8 K8_NOP4 K8_NOP4
	372
32c464f5 JB	373	/* P6 nops */
	374	/* uses eax dependencies (Intel-recommended choice) */
	375	#define P6_NOP1 ".byte 0x90\n"
	376	#define P6_NOP2 ".byte 0x66,0x90\n"
	377	#define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
	378	#define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
	379	#define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
	380	#define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
	381	#define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
	382	#define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
	383
1da177e4 LT	384	#define ASM_NOP_MAX 8
	385
	386	/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
9c0aa0f9	387	static inline void rep_nop(void)
1da177e4 LT	388	{
	389	__asm__ __volatile__("rep;nop": : :"memory");
	390	}
	391
	392	/* Stop speculative execution */
9c0aa0f9	393	static inline void sync_core(void)
1da177e4 LT	394	{
	395	int tmp;
	396	asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
	397	}
	398
1da177e4 LT	399	#define ARCH_HAS_PREFETCHW 1
	400	static inline void prefetchw(void *x)
	401	{
19aaabb5	402	alternative_input("prefetcht0 (%1)",
1da177e4 LT	403	"prefetchw (%1)",
	404	X86_FEATURE_3DNOW,
	405	"r" (x));
	406	}
	407
	408	#define ARCH_HAS_SPINLOCK_PREFETCH 1
	409
	410	#define spin_lock_prefetch(x) prefetchw(x)
	411
	412	#define cpu_relax() rep_nop()
	413
1da177e4 LT	414	static inline void __monitor(const void *eax, unsigned long ecx,
	415	unsigned long edx)
	416	{
	417	/* "monitor %eax,%ecx,%edx;" */
	418	asm volatile(
	419	".byte 0x0f,0x01,0xc8;"
	420	: :"a" (eax), "c" (ecx), "d"(edx));
	421	}
	422
	423	static inline void __mwait(unsigned long eax, unsigned long ecx)
	424	{
	425	/* "mwait %eax,%ecx;" */
	426	asm volatile(
	427	".byte 0x0f,0x01,0xc9;"
	428	: :"a" (eax), "c" (ecx));
	429	}
	430
d331e739 VP	431	static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
	432	{
	433	/* "mwait %eax,%ecx;" */
	434	asm volatile(
	435	"sti; .byte 0x0f,0x01,0xc9;"
	436	: :"a" (eax), "c" (ecx));
	437	}
	438
991528d7 VP	439	extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
991528d7 VP	440
fc363672 TG	441	extern int force_mwait;
	442
	443	extern void select_idle_routine(const struct cpuinfo_x86 *c);
	444
1da177e4 LT	445	#define stack_current() \
	446	({ \
	447	struct thread_info *ti; \
	448	asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
	449	ti->task; \
	450	})
	451
	452	#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
	453
	454	extern unsigned long boot_option_idle_override;
	455	/* Boot loader type from the setup header */
	456	extern int bootloader_type;
	457
8817210d AK	458	#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
8817210d AK	459
1da177e4	460	#endif /* __ASM_X86_64_PROCESSOR_H */