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1da177e4 LT |
1 | #ifndef __ASM_SMP_H |
2 | #define __ASM_SMP_H | |
3 | ||
1da177e4 | 4 | #include <linux/cpumask.h> |
43999d9e | 5 | #include <linux/init.h> |
1da177e4 | 6 | |
ae9d983b TG |
7 | /* |
8 | * We need the APIC definitions automatically as part of 'smp.h' | |
9 | */ | |
1da177e4 | 10 | #include <asm/apic.h> |
00f1ea69 | 11 | #include <asm/io_apic.h> |
ae9d983b | 12 | #include <asm/mpspec.h> |
1da177e4 | 13 | #include <asm/pda.h> |
ae9d983b | 14 | #include <asm/thread_info.h> |
1da177e4 | 15 | |
a8ab26fe | 16 | extern cpumask_t cpu_callout_map; |
3c021751 | 17 | extern cpumask_t cpu_initialized; |
a8ab26fe | 18 | |
ae9d983b TG |
19 | extern int smp_num_siblings; |
20 | extern unsigned int num_processors; | |
21 | ||
1da177e4 | 22 | extern void smp_alloc_memory(void); |
884d9e40 AR |
23 | extern void lock_ipi_call_lock(void); |
24 | extern void unlock_ipi_call_lock(void); | |
ae9d983b | 25 | |
66d16ed4 LV |
26 | extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *), |
27 | void *info, int wait); | |
3d483f47 | 28 | |
ef97001f | 29 | extern u16 __initdata x86_cpu_to_apicid_init[]; |
e8c10ef9 | 30 | extern u16 __initdata x86_bios_cpu_apicid_init[]; |
3b419089 | 31 | extern void *x86_cpu_to_apicid_early_ptr; |
e8c10ef9 | 32 | extern void *x86_bios_cpu_apicid_early_ptr; |
ae9d983b | 33 | |
d5a7430d | 34 | DECLARE_PER_CPU(cpumask_t, cpu_sibling_map); |
08357611 | 35 | DECLARE_PER_CPU(cpumask_t, cpu_core_map); |
ef97001f | 36 | DECLARE_PER_CPU(u16, cpu_llc_id); |
37 | DECLARE_PER_CPU(u16, x86_cpu_to_apicid); | |
e8c10ef9 | 38 | DECLARE_PER_CPU(u16, x86_bios_cpu_apicid); |
1da177e4 | 39 | |
ae9d983b | 40 | static inline int cpu_present_to_apicid(int mps_cpu) |
1da177e4 | 41 | { |
e8c10ef9 | 42 | if (cpu_present(mps_cpu)) |
43 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
ae9d983b TG |
44 | else |
45 | return BAD_APICID; | |
1da177e4 LT |
46 | } |
47 | ||
ae9d983b TG |
48 | #ifdef CONFIG_SMP |
49 | ||
50 | #define SMP_TRAMPOLINE_BASE 0x6000 | |
1da177e4 | 51 | |
76e4f660 AR |
52 | extern int __cpu_disable(void); |
53 | extern void __cpu_die(unsigned int cpu); | |
421c7ce6 | 54 | extern void prefill_possible_map(void); |
43999d9e | 55 | extern unsigned __cpuinitdata disabled_cpus; |
1da177e4 | 56 | |
ae9d983b TG |
57 | #define raw_smp_processor_id() read_pda(cpunumber) |
58 | #define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu) | |
92f98b19 | 59 | |
ae9d983b TG |
60 | #define stack_smp_processor_id() \ |
61 | ({ \ | |
62 | struct thread_info *ti; \ | |
63 | __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \ | |
64 | ti->cpu; \ | |
65 | }) | |
dd988528 | 66 | |
1da177e4 | 67 | /* |
ae9d983b TG |
68 | * On x86 all CPUs are mapped 1:1 to the APIC space. This simplifies |
69 | * scheduling and IPI sending and compresses data structures. | |
1da177e4 | 70 | */ |
ae9d983b | 71 | static inline int num_booting_cpus(void) |
1da177e4 | 72 | { |
ae9d983b | 73 | return cpus_weight(cpu_callout_map); |
1da177e4 LT |
74 | } |
75 | ||
ae9d983b TG |
76 | extern void smp_send_reschedule(int cpu); |
77 | ||
78 | #else /* CONFIG_SMP */ | |
79 | ||
80 | extern unsigned int boot_cpu_id; | |
81 | #define cpu_physical_id(cpu) boot_cpu_id | |
1da177e4 | 82 | #define stack_smp_processor_id() 0 |
ae9d983b TG |
83 | |
84 | #endif /* !CONFIG_SMP */ | |
85 | ||
86 | #define safe_smp_processor_id() smp_processor_id() | |
1da177e4 | 87 | |
1da177e4 LT |
88 | static __inline int logical_smp_processor_id(void) |
89 | { | |
90 | /* we don't want to mark this access volatile - bad code generation */ | |
ae9d983b TG |
91 | return GET_APIC_LOGICAL_ID(*(u32 *)(APIC_BASE + APIC_LDR)); |
92 | } | |
93 | ||
94 | static inline int hard_smp_processor_id(void) | |
95 | { | |
96 | /* we don't want to mark this access volatile - bad code generation */ | |
97 | return GET_APIC_ID(*(u32 *)(APIC_BASE + APIC_ID)); | |
1da177e4 | 98 | } |
1da177e4 LT |
99 | |
100 | #endif | |
101 |